JPS60143672A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the high-performance hetero junction element with the improved mutual inductance by forming a P<-> layer by doping a small quantity of P type impurities in a GaAs layer. CONSTITUTION:A GaAs layer 22 in which the doped quantity of P type impurity is made 1X10<16>cm<-3> by molecular beam epitaxy method is grown on a semi-insulating GaAs substrate 21. After that, an A GaAs layer 23 is grown. Doping with P type impurity into the GaAs layer 22 is performed by adding Be during molecular beam epitaxy. At this time, the quantity of doped Be can be increased to about 10<17>cm<-3>. A metal to become a gate electrode 28 is attached to the above epitaxial layer and ions 31 are implanted to 2X10<13>cm<-3> by using this metallic electrode as a mask to form an impurity region 24. The transistor thus fabricated offers the performance that is about 1.5 times the conventional type hetero junction field effect transistor in its mobility and three times in the mutual inductance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device that enables high-speed operation.

[Background of the invention]

Gallium arsenide (GaAs) has significantly higher electron mobility than silicon, making it a material suitable for fabricating high-speed devices. However, since it is difficult to form a high-quality insulating layer, M O8 (M
etal-Oxide-8emi con-ducto
r ) type field effect transistors have not been realized.

However, in recent years, it has been found that when an aluminum gallium arsenide (A/GaAs) crystal doped with donor impurities is used instead of the insulating layer, carriers are induced at the interface and a field effect transistor can be fabricated. FIG. 1 is a band structure diagram of the operating region of this transistor. 13 is an electrode part, 12 is an A/GaAs layer containing impurities, 1
1 is a GaAs layer containing substantially no impurities.
Also, FII indicates a feminine level. In FIG. 1, 15 is this carrier, which is trapped in a two-dimensional potential. This carrier 15 is A/GaAs (12)
Since it is supplied from the donor impurity level (14) inside and travels in GaAs that does not contain impurities, it is separated in location from the ionized donor impurity. As a result, scattering due to impurity potentials is significantly reduced, and high mobility can be achieved. However, when creating a transistor using this high mobility electron, A/GaAs
Due to the large amount of donors doped therein, the gate voltage is not effectively applied to the interface region, resulting in a decrease in transconductance. To prevent this, MO
A/G a A without adding impurities like 8 structure
It is desirable to use s. However, in the case of the Schittky type gate, there is a gap between the source and drain electrodes and the channel, unlike in the case of the MO8 structure.

As a result, if donor impurities are not added to A/GaAs or GaAs, carriers are not induced in this gap, and therefore the channel cannot be connected to the source/drain electrodes, making it impossible to operate as a transistor. .

A self-aligned heterojunction element shown in FIG. 3 has been proposed as an element having a structure that solves this problem and has a high conductance.

In this device, a semiconductor with a wide forbidden band width on the date electrode side in the gap region between the channel and the source and drain electrodes,
In the above example, donor impurities are introduced into A/GaAs,
This field effect transistor is characterized in that no impurities are introduced into the channel portion directly below the gate electrode. With such a structure, the mobility increases because there are no impurities that become scattering centers in the A/GaAs near the channel (21). (3) Since carriers are supplied from donor impurities to the gap, the gate voltage can be effectively applied to the channel and the mutual conductance can be increased.
It has the characteristics that the drain electrode can be connected and operates as a transistor.

In the case of a heterostructure field effect transistor consisting of A/GaAs and GaAs, s GaAs and A/Ga
The difference in conduction band with As at the interface is about 0.3 eV, and the Schittky barrier is about 0.6 eV. Therefore, when using A/G a As without adding impurities,
A channel is not formed when no gate voltage is applied. FIG. 2 shows a band structure diagram in this case. 13, the electrode part 12 is AI! 11 is a GaAs layer, and Fll indicates a smooth level. In the case of FIG. 2, the device is in a normally off state, and a channel is formed by applying a positive voltage to the gate. In other words, it becomes an enhancement type transistor.

However, in this device, since layer 11 is not substantially doped with impurities, this layer may become n-type or p-type depending on variations in the growth conditions when forming layer 11. When the transistor becomes n-type, even when no voltage is applied to the gate, current flows between the source and drain due to carriers generated in this portion, and a normally-off state is not formed.

In addition, since the band bending in this portion 11 is small, even if a negative voltage is applied to the gate, the carrier is GaAs and G
Just being pushed away from the interface with a A /A s to the layer 11 side makes it difficult to form a pinch-off state. Therefore, mutual conductance decreases and device performance deteriorates.

[Purpose of the invention]

The present invention solves the above-mentioned drawbacks of the conventional device and is stable.

The present invention also aims to provide a high-performance heterojunction element.

[Summary of the invention]

In the present invention, the layer 11 shown in FIG.
The above purpose was achieved by layering.

That is, in the present invention, as shown in FIG.
A small amount of P-type impurity 17 is added to the aAs layer 11'.
1016 cm-" or less), and this layer is made into a single P layer to raise the conductor level 18 and prevent carriers from flowing into this portion.

In addition, as shown in FIG. 4, impurities include Ga At A
A similar effect can be achieved by doping only away from the s12 interface. In this case, since there are few impurities at the carrier-induced interface, high mobility can be expected, and it is also possible to increase the concentration of the P-type impurity 17'.

[Embodiments of the invention]

Example 1 The main steps are shown in FIGS. 5(a) to 5(C).

On a semi-insulating GaAs substrate 21, a GaAs layer (22) with a P-type impurity doping amount of about 1 x 10 cm" or less is formed by using a 5-molecular beam epitaxy method to a thickness of about 1 μm (usually 5 cm" or less).
000A to about 1.5 μm. ) to the substrate temperature 5
After growing at 80°0, AI! and an ArGaAs layer (23) with a Ga and state ratio of approximately 0.3:0.7.
It is selected in the range of 0. ) P-type impurity doping into the GaAs layer 22 is performed by adding Be during molecular beam epitaxy. Moreover, the result shown in FIG. 4 is obtained by stopping the addition of Be during the formation of the GaAs layer.

It is also possible to form elements with a band structure. The amount of Be added at this time may be increased to about 10"Cm"". In addition, as P-type impurities, in addition to Be, %Z
n% etc. can also be used.

On the above epitaxial T-, a metal that will become the gate electrode 2B, for example, TiBW, is applied to a thickness of about 1 μm, and then this metal electrode is used as a mask for ion implantation (self-alignment).
m" implantation. In order to remove the lattice defects generated by the ion implantation and activate the ions, annealing was performed at 750°C for 30 minutes. This impurity is shown as 24 in Fig. 5(b). In order to increase the ion activation rate, it is preferable to anneal at a high temperature of 850°C, but in order to prevent blurring of the ArGaAs and GaAs interfaces and to prevent impurity diffusion, the above Annealing is performed at high temperatures.

Note that the donor impurity mentioned above is other than 8i.

Ge, Sn, Te, 8e, S, etc. can be used.

The impurity concentration for ion implantation of approximately 10"-10" cm is set depending on the degree to which carriers are bundled, that is, the required characteristics of the device.The energy of ion implantation is determined depending on the implanted element. It varies, but 50-2
A range of about 00 KeV is used.

Note that, due to, for example, the energy of ion implantation, the impurity layer 24 is lowered to a depth shown in FIG. 5(C).

It may be formed deeper. FIG. 5(d) shows this state.

Next, a source (25) and a drain electrode region (26) are formed by a normal alloying method, connected to the ion implantation layer, and an electrode metal A/(29,30) is formed to form a field effect transistor. Created. Note that 32 indicates carriers induced at the interface (FIG. 5(C)).

Note that the source and drain regions are formed using, for example, A
u-Ge alloy (2000A) -Ni (100 people)-
Au-Ge alloy (3000 people) is laminated on the designated part,
It is formed by heating at 400° for about 0.5 minutes in H2.

The transistor created in this way is made of ArGaAs
Compared to conventional heterojunction field effect transistors made by adding donors on the order of 2×I013cm-3, the performance was improved by about 1.5 times in terms of mobility and about 3 times in terms of mutual conductance. .

Note that GaAs, which is more chemically stable than ArGaAs, is
As with the conventional method, growing a small amount on rGaAs is also effective in increasing transistor fabrication efficiency. Thickness: 300λ to 2000λ
That's about it.

Example 2 An example of fabricating an integrated circuit on a wafer will be described (Figure 6).

The basic configuration of this example is to
Si ions (24) at 50KeV 2 x 1013c
Enter m-3. In this case, it is more preferable to implant ions only into the GaA4As layer 23.

Thereafter, after forming the gate electrode 28, using this as a mask, a second ion implantation is performed under the same conditions as in Example 1 into both regions 27 that are to become transistors, and the impurities are activated by similar annealing. This made it possible to simultaneously create enhancement-type and depletion-type transistors.

Note that the donor impurity mentioned above is other than Si.

Ge, Sn, Te, Se, 8, etc. can be used. To what extent will the impurity concentration of approximately 1013 to 1014 cm ion implantation generate carriers?
That is, it is set according to the required characteristics of the device. The energy of ion implantation varies depending on the implanted element, but 5
A range of 0 to 200 KeVa degrees is used.

In addition, the source and drain regions are formed using, for example, Au.
Ge alloy (2000 people) - Ni (100 people) - Au
-Ge alloy (3000 yen) is laminated on a predetermined portion and heated in H2 at 400° for about 0.5 minutes.

In the above embodiments, a semiconductor device made of GaAs-GaAs8b system has been described, but other materials for forming the heterojunction are also suitable. for example.

A7yGa1. As-A/xGa, As, GaA
s-A/GaAsP.

InP-InGaAsP, InP-InGaAs,
InAs-GaAs8b, etc.

The present invention can be summarized as follows.

1. The first semiconductor layer and the second semiconductor layer are arranged to form a heterojunction, and the forbidden band width of the first semiconductor layer is smaller than that of the second semiconductor layer. In the semiconductor device, the first semiconductor layer serves as an acceptor under the gate electrode. Impurity 1016cm
``contains impurities of less than 1016 cm in the source, or in the region adjacent to the source and drain''
It is characterized by containing the above.

Due to the introduced impurity, carriers are generated in the vicinity of the heterojunction corresponding to the impurity region. The basic principle of carrier generation is the same as that shown in FIG.

2. The first semiconductor layer and the second semiconductor layer are arranged to form a heterojunction, and the forbidden band width of the first semiconductor layer is smaller than that of the second semiconductor layer. A semiconductor device including at least a pair of electrodes electronically connected to a semiconductor layer, and means for controlling carriers generated near the heterojunction, wherein at least the first semiconductor layer (or the first and second semiconductor layers) 016).
cm'' or more.

Due to the introduced impurity, carriers are generated in the vicinity of the heterojunction corresponding to the impurity region.

Further, it is preferable to use the technique described in the first section in combination, that is, to cause the impurity to be contained in the source or the region adjacent to the source and the drain at 10<16>cm<-3> or more.

3. Both of the above semiconductor devices can be used as elements of an integrated circuit.

4. When integrating, each of the semiconductor devices described in the first and second paragraphs is arranged, and the device in the first paragraph operates as a normally-off transistor, and the device in the second paragraph operates as a normally-on transistor. be able to.

5. It is preferable to introduce the above-mentioned impurity to serve as a donor or acceptor using an ion implantation method. In particular, when introducing impurities into the region including the part directly below the date described in Section 2, the average range of ions must be more than 300 mm away from the semiconductor heterojunction, leaving a buffer layer on the gate side. It is better to perform ion implantation.

[Brief explanation of the drawing]

1 and 2 are energy diagrams of a conventional heterojunction field effect transistor. 3 and 4 show energy diagrams of transistors according to the present invention. Figures 5(a) to (c) are cross sections of the device showing the manufacturing process of a field effect transistor, Figure 6f
a) to (d) are cross-sectional views of the device showing manufacturing steps when configuring an integrated circuit. 17, 17' are P-type impurities, 21... Cattle insulating G
a As substrate, 22...G a As... epitaxial layer, 23... A I! Ga As epitaxial layer, 24... 8i impurity introduced in the first ion implantation, 25.26... Source and drain region, 27... S introduced in the second ion implantation
i, 28... Gate electrode, 29... Wiring metal, 3
1...Carriers induced at the interface.搦 J Masayo 2 Danba 3 Waban S Zuman S @ 8 Do Y Procedural amendment (method) Case description 1982 Patent application No. 246969 Name of invention Semiconductor device Amendment person relationship with the case Patent Applicant name (510) Hitachi Manufacturing Co., Ltd.
Target of amendment by the administrator Contents of amendment in the brief explanation of the drawings in the specification Correct r(C)J on page 14, line 6 of the specification of the application to r(d month).

Claims (1)

[Claims] 1. The first semiconductor layer and the second semiconductor layer are arranged to form a heterojunction, and the forbidden band width of the first semiconductor layer is smaller than that of the second semiconductor layer. In a semiconductor device having at least a pair of electrodes electronically connected to a semiconductor layer and a step for controlling carriers generated in the vicinity of the heterojunction, the first semiconductor layer has a P carved structure under the gate electrode. What is claimed is: 1. A semiconductor device characterized in that the semiconductor device contains only 1017 cm -3 or less of gold, and the source or the region adjacent to the source and the drain contains 10"cm" ld of n-carvings.