JPS60143646A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an insulator isolation substrate from warping due to the deposited formation of a silicon support by a method wherein an epitaxially grown insulating film (EGI) is formed on the surface of a semiconductor substrate, wherein grooves to partition insular regions have been formed, and a single crystal silicon layer, which is used as a support, is deposited thereon. CONSTITUTION:V-shaped grooves 3, by which insular regions 6 are partitioned, are formed in a single crystal silicon substrate 1 and after an N<+> type buried diffusion layer was formed on the surface of the substrate 1 inclusive of the V-shaped grooves 3, an EGI7 is made to grow. This EGI7 is used as an epitaxial layer in a spinel structure consisting of MgO and Al2O3. Then, a single crystal or a silicon layer 8 close to the single crystal, which is used as a support, is formed by a CVD method. After then, the silicon layer 8 is shaved up to reach the V-shaped grooves 3 from the side of the silicon substrate 1 and the dielectrically isolated insular regions 6 are formed.

Description

[Detailed description of the invention] Technical field The present invention relates to a method for manufacturing a dielectric isolation substrate.

Prior Art The manufacturing process of a conventional dielectric isolation substrate is shown in FIGS. 1A to 1C. As shown in FIG. Formed by oxidation, etc.

Note that formation I of the insulating film 2: N+ buried diffusion is normally performed first, but this is omitted for simplicity (1). Next, as shown in FIG. B, a thick polysilicon layer 4 serving as a support is deposited on the insulating film 2. In this step, the semiconductor substrate 1 warps due to shrinkage stress acting on the polysilicon layer 4. After that, by polishing etc., the V groove 3 is removed from the semiconductor substrate 1 side.
Most of the single silicon is removed by grinding until reaching , and a dielectric isolation substrate having two C island regions 6 as shown in FIG. C is obtained. When most of the single silicon is removed, the dielectric isolation substrate warps even more as shown in Figure C. If the semiconductor substrate 1 in Figure B is warped, it will greatly affect the accuracy of polishing, etc. for forming the island region in Figure C, and the depth of the island region 6 will vary, resulting in a situation where a considerable portion of the substrate cannot be used. comes out. In addition, various problems arise, such as the inability to perform vacuum chucking during post-processing (double flow), and the difficulty of photolithography during element formation (focus shift during exposure).

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object of the present invention is to prevent an insulator isolation substrate from warping due to the deposition of a silicon support.

Structure and operation of the invention In the present invention, an epitaxially grown insulating film is used as an isolation insulating film, and the silicon layer that is grown on the epitaxially grown insulating film as a support is formed into a single crystal layer (nearly a single crystal layer) to prevent warpage of the insulating isolation substrate. The epitaxially grown insulator (EGI) used in the present invention
ly y'su. wrLinzwlatov is, for example, M
This is an epitaxial layer having a fO-Al, 03 spinel structure.

FIG. 2 shows an embodiment of the present invention, and in FIG.
An oxide film 5 is formed on a (100) single crystal silicon substrate 1, and patterned so that the oxide film 5 remains on the part where the island region is to be formed, as shown in Figure B (= the island region is etched by anisotropic etching). Form a V-groove 3 for partitioning. KOH and isopropyl alcohol are used for anisotropic etching. As shown in Figure C, the oxide film 5 is forashed out, and an N" buried diffusion layer is formed on the substrate surface including the V-groove 3. However, for simplicity, we omit that point.

Next, as shown in the figure, (6) an EGI layer 7 is grown on the surface of the substrate 1 including the V-groove 3. This EGI is MfO-At
, is an epitaxial layer with a spinel structure of 03,
HCI, At, MIC2! , Co, is formed by a quaternary epitaxial growth method. Growth temperature is 9
EGI with good crystallinity can be obtained at about 00 to 1000°C.

EGI having an (ion) crystal orientation plane is obtained on an (ioo) single crystal silicon substrate. Growth temperature is 100
At temperatures above 0°C, the EGI crystal layer becomes slightly disordered, but in the present invention, the silicon growth layer on the EGI is not used as the element formation surface, so even in that case, a single-crystal silicon layer close to C: can be obtained, and stress is reduced. It would be good if this could be eased. EGI layer 7
The film thickness is determined based on pressure resistance, and approximately 2 μm is sufficient. As shown at the end E, a support silicon layer 8 is formed by a conventional CVD growth method for a silicon layer. For example, 5iCl as the source gas or the faster growing 5iHC1
, at about 1150°C to 1200°C. 5iC
1, the growth rate is about 2 μm/min, 5iHCl
, it is about 6 times that amount. The pressure in the reactor was normal pressure. The obtained silicon layer 8 is different from a conventional polysilicon layer, and although it has many defects, (4) a single crystal or a layer close to this can be obtained (single crystal silicon layer). Thereafter, a dielectrically isolated island region 6 is formed by cutting from the silicon substrate 1 side by a conventional method until reaching the V-groove 3.

In the present invention, the groove 3 is not limited to a V-groove, but may have other shapes such as a U-groove.

Effects of the Invention The dielectric isolation substrate obtained by the method of the present invention has much less warpage than the conventional one. Conventionally, the warpage of dielectric isolation substrates was 2
Although it used to be 00 to 300 μm, the method of the present invention reduces it to within several tens of μm. As a result, the polishing accuracy is improved, the depth accuracy of the island region on the wafer is improved, the surface area can be effectively used over the entire surface, and handling in subsequent steps is facilitated.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing conventional dielectric isolation substrate manufacturing steps A to C. FIG. 2 is a process diagram showing dielectric isolation substrate manufacturing steps A and F in the semiconductor device manufacturing method of the present invention. sign, second
In the figure, 1... Single crystal silicon substrate (substrate) (5) 6... V groove 5... Oxide film 6... Island region 7... EGI (layer) 8... (Support ) Silicon layer (single crystal silicon layer)
Patent applicant Fujitsu Ltd. agent Patent attorney Gobe Tamamushi (1 other person) (6) Figure 1 Figure 12

Claims (1)

[Claims] The method is characterized by forming grooves in a semiconductor substrate to define island regions, forming an epitaxially grown insulating film on the surface of the substrate including the grooves, and depositing a monocrystalline silicon layer as a support on the epitaxially grown insulating film. A method for manufacturing a semiconductor device.