JPS60143646A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60143646A JPS60143646A JP24955283A JP24955283A JPS60143646A JP S60143646 A JPS60143646 A JP S60143646A JP 24955283 A JP24955283 A JP 24955283A JP 24955283 A JP24955283 A JP 24955283A JP S60143646 A JPS60143646 A JP S60143646A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- single crystal
- layer
- silicon
- support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 技術分野 本発明は誘電体分離基板の製造方法に関する。[Detailed description of the invention] Technical field The present invention relates to a method for manufacturing a dielectric isolation substrate.
従来技術
従来の誘電体分離基板の製造工程を第1図A〜Cに示す
。図Aのごとく、半導体(Si )基板1に異方性エツ
チングでV溝3を島領域形成予定部を区画するように形
成し、該V溝3を含む半導体基板表面に厚い絶縁膜2を
高圧酸化等で形成する。Prior Art The manufacturing process of a conventional dielectric isolation substrate is shown in FIGS. 1A to 1C. As shown in FIG. Formed by oxidation, etc.
なお、絶縁膜2の形成I:先だち普通N+埋没拡散が行
なわれるが、簡単のためこれは省略して示(1)
ている。次に図Bのごとく、絶縁膜2の上に支持体とな
る厚いポリシリコン層4を堆積する。この工程でポリシ
リコン層4に作用する収縮応力により半導体基板1が反
る。その後ポリッシング等で半導体基板1側からV溝3
に達するまで削って大部分のシングルシリコンを除去し
、図Cに示すようC二島領域6を備える誘電体分離基板
を得る。大部分のシングルシリコンを除去すると誘電体
分離基板は図Cのよう盛=さらに大きく反る。図Bにお
いて半導体基板1が反ると、図Cの島領域形成のための
ポリッシング等の精度に大きく影響し、島領域6の深さ
にバラツキがでてクエへのかなりの部分が使えない事態
がでてくる。また後工程(二流すとき真空でのチャッキ
ングができないとか、素子形成のときのフォトリソグラ
フィが困難になる(露光時のフオ カスずれ)等種々の
障害がでる。Note that formation I of the insulating film 2: N+ buried diffusion is normally performed first, but this is omitted for simplicity (1). Next, as shown in FIG. B, a thick polysilicon layer 4 serving as a support is deposited on the insulating film 2. In this step, the semiconductor substrate 1 warps due to shrinkage stress acting on the polysilicon layer 4. After that, by polishing etc., the V groove 3 is removed from the semiconductor substrate 1 side.
Most of the single silicon is removed by grinding until reaching , and a dielectric isolation substrate having two C island regions 6 as shown in FIG. C is obtained. When most of the single silicon is removed, the dielectric isolation substrate warps even more as shown in Figure C. If the semiconductor substrate 1 in Figure B is warped, it will greatly affect the accuracy of polishing, etc. for forming the island region in Figure C, and the depth of the island region 6 will vary, resulting in a situation where a considerable portion of the substrate cannot be used. comes out. In addition, various problems arise, such as the inability to perform vacuum chucking during post-processing (double flow), and the difficulty of photolithography during element formation (focus shift during exposure).
発明の目的
本発明は上記従来の欠点を解決するためになされたもの
であって、シリコン支持体の堆積形成によって絶縁体分
離基板が反ることを防止することlす1
を目的とする。OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object of the present invention is to prevent an insulator isolation substrate from warping due to the deposition of a silicon support.
発明の構成及び作用
本発明においては、分離用絶縁膜としてエピタキシャル
成長絶縁膜を用い、この上に成長する支持体となるシリ
コン層を単結晶(:近い層にすることにより絶縁体分離
基板の反りを防止するものである。本発明で用いるエピ
タキシャル成長絶縁体(EGI 、 Epitozia
ly y’す。wrLinzwlatovは、例えばM
fO−Al、03のスピネル構造をもつエピタキシャル
層である。Structure and operation of the invention In the present invention, an epitaxially grown insulating film is used as an isolation insulating film, and the silicon layer that is grown on the epitaxially grown insulating film as a support is formed into a single crystal layer (nearly a single crystal layer) to prevent warpage of the insulating isolation substrate. The epitaxially grown insulator (EGI) used in the present invention
ly y'su. wrLinzwlatov is, for example, M
This is an epitaxial layer having a fO-Al, 03 spinel structure.
第2図に本発明の実施例を示しており、図Aにおいて、
(100)の単結晶シリコン基板1上に酸化膜5を形成
し、島領域の形成予定部上に酸化膜5が残るようにパタ
ーニングし、図Bのよう(=異方性エツチングにより島
領域を区画するV溝3を形成する。異方性エツチングに
はKOHとイソプロピルアルコフルを用いる。図Cで酸
化膜5をフォラシュアウトし、V溝3を含む基板表面に
N“埋没拡散層を形成するが簡単のためその点は省略す
る。FIG. 2 shows an embodiment of the present invention, and in FIG.
An oxide film 5 is formed on a (100) single crystal silicon substrate 1, and patterned so that the oxide film 5 remains on the part where the island region is to be formed, as shown in Figure B (= the island region is etched by anisotropic etching). Form a V-groove 3 for partitioning. KOH and isopropyl alcohol are used for anisotropic etching. As shown in Figure C, the oxide film 5 is forashed out, and an N" buried diffusion layer is formed on the substrate surface including the V-groove 3. However, for simplicity, we omit that point.
次に図りにおいて、V溝3を含む基板1の表面に(6)
EGI層7を成長せしめる。このEGIはMfO−At
、03のスピネル構造をもつエピタキシャル層であり、
HCI 、 At 、 MIC2!、 Co、の4元系
のエピタキシャル成長法により形成する。成長温度は9
00〜1000℃位で結晶性の良いEGIが得られる。Next, as shown in the figure, (6) an EGI layer 7 is grown on the surface of the substrate 1 including the V-groove 3. This EGI is MfO-At
, is an epitaxial layer with a spinel structure of 03,
HCI, At, MIC2! , Co, is formed by a quaternary epitaxial growth method. Growth temperature is 9
EGI with good crystallinity can be obtained at about 00 to 1000°C.
(ioo)の単結晶シリコン基板上には(ion)の結
晶方位面をもったEGIが得られる。成長温度が100
0℃以上ではEGIの結晶層はや\乱れるが、本発明に
おいてはEGI上のシリコン成長層を素子形成面とする
のではないから、その場合でも単結晶C:近いシリコン
層が得られ、ストレスが緩和されれば良い。EGI層7
の膜厚は耐圧上決定され、2μ扉位で十分である。その
後口Eに示すごとく普通のシリコン層のCVD成長法に
より、支持体シリコン層8を形成する。例えば、ソース
ガスとして5iCl 、又はより成長が速い5iHC1
,を用い1150℃〜1200℃位で成長する。5iC
1,を用いると成長速度は2μmn/分位、5iHCl
、ではその6倍位である。リアクタの圧力は常圧で行な
った。得られるシリコン層8は従来のポリシリコン層と
異なり、欠陥は多いながら(4)
単結晶乃至これに近い層が得られる(単結晶シリコン層
)。その後、シリコン基板1側より常法によりV溝3に
到るまで削って誘電体分離された島領域6を形成する。EGI having an (ion) crystal orientation plane is obtained on an (ioo) single crystal silicon substrate. Growth temperature is 100
At temperatures above 0°C, the EGI crystal layer becomes slightly disordered, but in the present invention, the silicon growth layer on the EGI is not used as the element formation surface, so even in that case, a single-crystal silicon layer close to C: can be obtained, and stress is reduced. It would be good if this could be eased. EGI layer 7
The film thickness is determined based on pressure resistance, and approximately 2 μm is sufficient. As shown at the end E, a support silicon layer 8 is formed by a conventional CVD growth method for a silicon layer. For example, 5iCl as the source gas or the faster growing 5iHC1
, at about 1150°C to 1200°C. 5iC
1, the growth rate is about 2 μm/min, 5iHCl
, it is about 6 times that amount. The pressure in the reactor was normal pressure. The obtained silicon layer 8 is different from a conventional polysilicon layer, and although it has many defects, (4) a single crystal or a layer close to this can be obtained (single crystal silicon layer). Thereafter, a dielectrically isolated island region 6 is formed by cutting from the silicon substrate 1 side by a conventional method until reaching the V-groove 3.
なお、本発明において溝3はV溝に限らず、U溝など他
の形状でも良い。In the present invention, the groove 3 is not limited to a V-groove, but may have other shapes such as a U-groove.
発明の効果
本発明方法により得られる誘電体分離基板は、従来より
ずっと反りが小さい。従来、誘電体分離基板の反りは2
00〜300μmもあったが、本発明方法によれば数十
μm以内となる。この結果、ポリッシング精度が良くウ
ェハ上の島領域の深さの精度が良くなり、クエへが全面
的C二有効に使え、また後工程での取扱いが容易となる
。Effects of the Invention The dielectric isolation substrate obtained by the method of the present invention has much less warpage than the conventional one. Conventionally, the warpage of dielectric isolation substrates was 2
Although it used to be 00 to 300 μm, the method of the present invention reduces it to within several tens of μm. As a result, the polishing accuracy is improved, the depth accuracy of the island region on the wafer is improved, the surface area can be effectively used over the entire surface, and handling in subsequent steps is facilitated.
第1図は従来の誘電体分離基板の製造工程A〜Cを示す
工程−1
第2図は本発明の半導体装置の製造方法における誘電体
分離基板の製造工程A、Fを示す工程図上な符号、第2
図において、
1・・・単結晶シリコン基板(基板)
(5)
6・・・V溝
5・・・酸化膜
6・・・島領域
7・・・EGI (層)
8・・・(支持体)シリコン層(単結晶化シリコン層)
特許出願人 富士通株式会社
代理人 弁理士 玉蟲久五部(外1名)(6)
第1図
12 図FIG. 1 is a process diagram showing conventional dielectric isolation substrate manufacturing steps A to C. FIG. 2 is a process diagram showing dielectric isolation substrate manufacturing steps A and F in the semiconductor device manufacturing method of the present invention. sign, second
In the figure, 1... Single crystal silicon substrate (substrate) (5) 6... V groove 5... Oxide film 6... Island region 7... EGI (layer) 8... (Support ) Silicon layer (single crystal silicon layer)
Patent applicant Fujitsu Ltd. agent Patent attorney Gobe Tamamushi (1 other person) (6) Figure 1 Figure 12
Claims (1)
基板表面にエピタキシャル成長絶縁膜を形成し、該エピ
タキシャル成長絶縁膜上に支持体としての単結晶化シリ
コン層を堆積することを特徴とする半導体装置の製造方
法。The method is characterized by forming grooves in a semiconductor substrate to define island regions, forming an epitaxially grown insulating film on the surface of the substrate including the grooves, and depositing a monocrystalline silicon layer as a support on the epitaxially grown insulating film. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24955283A JPS60143646A (en) | 1983-12-29 | 1983-12-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24955283A JPS60143646A (en) | 1983-12-29 | 1983-12-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60143646A true JPS60143646A (en) | 1985-07-29 |
Family
ID=17194686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24955283A Pending JPS60143646A (en) | 1983-12-29 | 1983-12-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60143646A (en) |
-
1983
- 1983-12-29 JP JP24955283A patent/JPS60143646A/en active Pending
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