JPS60142536A - Chuck table for semiconductor dicing device - Google Patents
Chuck table for semiconductor dicing deviceInfo
- Publication number
- JPS60142536A JPS60142536A JP25118883A JP25118883A JPS60142536A JP S60142536 A JPS60142536 A JP S60142536A JP 25118883 A JP25118883 A JP 25118883A JP 25118883 A JP25118883 A JP 25118883A JP S60142536 A JPS60142536 A JP S60142536A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- chuck
- chuck table
- adhesive tape
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体ダイシング装置↑のチーヤツクテーブ
ルに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a check table for a semiconductor dicing apparatus↑.
従来半導体ダイシング装置のチャックテーブルは、半導
体を固定するチャック面は平滑な仕上げ加工がなされ、
さらに、真空溝を設は真空チーヤックされる構造となっ
ている。The chuck table of conventional semiconductor dicing equipment has a smooth finish on the chuck surface that fixes the semiconductor.
Furthermore, the vacuum groove is designed to be vacuum checked.
最近半導体のダイ7ングはフルカットダイシングに移行
しつつあるが、この場合半導体は、粘着テープを介して
チーヤックテーブルに真空チャックする方式を一般的に
採用している。しかし従来のチーヤツクテーブルを使用
すると、チーヤック面が平滑に仕上げられているために
、粘着テープがチャック面に密着してしまい、ダイシン
グ後の取り外しが困t1[であると共に、酸チップ同志
が当り、チップのカケやクランクが発生するという問題
があった。これを無くすためにパウダーのような細かい
粒子状の粉をチーヤックテーブルのチャック面に塗布す
るという方法もとられていたが、1回毎塗布する必要が
あったし、粉が半導体に付着し、品質面に悪影響を及は
すことも心配されていた。Recently, semiconductor dicing has been shifting to full-cut dicing, but in this case, semiconductors are generally vacuum chucked onto a check table via adhesive tape. However, when using a conventional chuck table, since the chuck surface is smooth, the adhesive tape sticks to the chuck surface, making it difficult to remove it after dicing, and also causing the acid chips to hit each other. , there were problems with chips chipping and cranking. In order to eliminate this problem, a method of applying fine particles such as powder to the chuck surface of the chuck table was used, but it had to be applied every time, and the powder could adhere to the semiconductor. There were also concerns that this would have a negative impact on quality.
本発明は上記の欠点を解決するもので、フルカットダイ
シングの際の粘着テープ付半導体のチャックテーブルか
らの取り外し作業を容易にし、またチップのカケ、ワレ
の防止、品質信頼性の確保をはかることを目的としたも
のである。The present invention solves the above-mentioned drawbacks, and aims to facilitate the removal of semiconductors with adhesive tape from the chuck table during full-cut dicing, prevent chips from chipping and cracking, and ensure quality reliability. The purpose is to
本発明の半導体ダイシング装置のチャックテーブルは、
半導体をチャックする半導体チャック面がブラスト加工
等により凹凸状に形成されたことを特徴とする。The chuck table of the semiconductor dicing apparatus of the present invention includes:
It is characterized in that the semiconductor chuck surface for chucking the semiconductor is formed into an uneven shape by blasting or the like.
以下、本発明について実施例に基づき詳細に説明する。 Hereinafter, the present invention will be described in detail based on examples.
第1図及び第2図は従来の実施例であり、フルカットさ
れた半導体チップ4はウェハ−リング3に同定された粘
着テープ2に貼りつけられチーヤツクテーブル1に真空
吸着されている。半導体チップ4をチーヤツクテーブル
1から取り外そうとする場合は、壕ず真空を切り、ウェ
ハーリング3′f、持ち上げ、粘着テープ2に貼りつい
fcままで外すことになる。この時チャックテーブル1
の半導体チーヤツク面1aが平滑に仕上げられているた
め、真空欠切ってもしばらくの間粘iテープ2と密着状
罪となっておりスムーズな取外しができない。このため
半導体チップ4が隣接チップと接触し、カケ、クラック
となる。FIGS. 1 and 2 show a conventional embodiment, in which a fully cut semiconductor chip 4 is attached to an adhesive tape 2 attached to a wafer ring 3 and vacuum-adsorbed to a check table 1. FIG. When attempting to remove the semiconductor chip 4 from the check table 1, it is necessary to turn off the vacuum, lift the wafer ring 3'f, and remove the semiconductor chip 4 while it remains stuck to the adhesive tape 2. At this time, chuck table 1
Since the semiconductor cheek surface 1a of the semiconductor cheek 1a is finished smoothly, it remains in close contact with the adhesive tape 2 for a while even when the vacuum is removed, making it impossible to remove it smoothly. As a result, the semiconductor chip 4 comes into contact with an adjacent chip, resulting in chips and cracks.
第3図及び第4図は本発明の実施例であって、チーヤツ
クテーブル1の半導体チーヤツク面1aはサンドブラス
ト等により、細かな凹凸状に加工されており、真空を切
ると、粘着テープ2とは即密着状態は解除される。この
ため、半導体チップ4全ヂーヤツクテーブル1から取り
外すことが容易となり、また、隣接チップと接触するこ
ともなくなり、カケ、ワレもなくなる。3 and 4 show an embodiment of the present invention, in which the semiconductor cheek surface 1a of the cheek table 1 is processed into fine irregularities by sandblasting or the like, and when the vacuum is turned off, the adhesive tape 2 The contact status will be canceled immediately. Therefore, the entire semiconductor chip 4 can be easily removed from the jack table 1, and there is no contact with adjacent chips, thereby eliminating chips and cracks.
以上説明したように粘着テープを使用したフルカットダ
イシングにおいて、フルカットした後の半導体チップの
取り外しが容易になり、チップのカケ、クラックも防止
できる、パウダー等の粉も使わなくて良いため、信頼性
1品質面にも全く開閉がなく安心して使用できる、捷た
、粘着テープ′fC使わないハーフカットダイシングに
おいても、ハーフカット後の半導体ウエノ・−の取り外
しが容易VCなり、作業能率の向上、作業ミスによる欠
点の減少をはかることができる。As explained above, full-cut dicing using adhesive tape makes it easy to remove semiconductor chips after full cutting, prevents chips from chipping and cracking, and eliminates the need to use powder, making it reliable. In terms of quality, there is no opening or closing at all, so you can use it with confidence. Even in half-cut dicing that does not use adhesive tape, it is easy to remove the semiconductor wafer after half-cutting, improving work efficiency. Defects caused by work errors can be reduced.
Q 11’、2+は従来のチャックテーブルにフルカッ
トされた半導体チップが取付いている断面図。
第2図は従来のチャックテーブルを使用してフルカット
した半導体チップをチーヤツクテーブルから取り外す状
Dk示す断面図。
第3図は本発明のチャックテーブルにフルカットされた
半導体チップが取付いている断面図。
第を図は本発明のチーヤツクテーブルを使用してフルカ
ットした半導体チップをチーヤツクテーブルから取り外
す状罪を示す断面図。
1はチーヤツクテーブル断面図
1aけチャック面
1bは真空溝
2は粘着テープ
3はウェハーリング
4にフルカットされた半導体チップ
以 上
出願人 株式会社諏訪精工舎
代理人 弁理士最上 務Q11', 2+ is a cross-sectional view of a conventional chuck table with a fully cut semiconductor chip attached. FIG. 2 is a sectional view showing a state Dk in which a semiconductor chip that has been fully cut using a conventional chuck table is removed from the chuck table. FIG. 3 is a sectional view showing a fully cut semiconductor chip attached to the chuck table of the present invention. The third figure is a cross-sectional view showing how a semiconductor chip that has been fully cut using the check table of the present invention is removed from the check table. 1 is a cross-sectional view of the chuck table 1a, the chuck surface 1b is the vacuum groove 2 is the adhesive tape 3 is the semiconductor chip fully cut into the wafer ring 4, etc. Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami
Claims (1)
−j転する機構と、半導体をチャックするチャック面が
平面となっており、かつ前記半導体チーヤツク面に實空
チーヤツク用のに空溝が設けられて卦り、前記半導体を
真空チャックし往禅運動するチーヤツクテーブルと全備
え、前記チャックテーブルに半導体を真空吸着によりチ
ーヤツクし、前記チャックテーブルの往復運jjijと
、前記ブレードの回転運nO+により半導体を切断する
半導体ダイシング装置において、前記半導体チ・ヤック
面がプラスト加工等により凹凸状に形成されたことを特
徴とする半導体ダイシング装置のチーヤックテーブル。A blade is attached to a blade attachment part, and the blade has a -j rotation mechanism, a chuck surface for chucking the semiconductor is flat, and a hollow groove for a real chuck is provided on the semiconductor chuck surface. and a chuck table that vacuum chucks the semiconductor and moves back and forth, chucks the semiconductor on the chuck table by vacuum suction, and cuts the semiconductor by the reciprocating movement of the chuck table and the rotational movement of the blade. 1. A check table for a semiconductor dicing apparatus, characterized in that the semiconductor check surface is formed into an uneven shape by a plastic process or the like.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25118883A JPS60142536A (en) | 1983-12-28 | 1983-12-28 | Chuck table for semiconductor dicing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25118883A JPS60142536A (en) | 1983-12-28 | 1983-12-28 | Chuck table for semiconductor dicing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60142536A true JPS60142536A (en) | 1985-07-27 |
Family
ID=17218985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25118883A Pending JPS60142536A (en) | 1983-12-28 | 1983-12-28 | Chuck table for semiconductor dicing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60142536A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07169824A (en) * | 1993-12-13 | 1995-07-04 | Anelva Corp | Substrate heating and cooling mechanism |
US7427902B2 (en) | 2005-04-11 | 2008-09-23 | Epson Toyocom Corporation | High-stability piezoelectric oscillator |
JP2016162800A (en) * | 2015-02-27 | 2016-09-05 | 株式会社東京精密 | Dicing device and table for dicing device |
-
1983
- 1983-12-28 JP JP25118883A patent/JPS60142536A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07169824A (en) * | 1993-12-13 | 1995-07-04 | Anelva Corp | Substrate heating and cooling mechanism |
US7427902B2 (en) | 2005-04-11 | 2008-09-23 | Epson Toyocom Corporation | High-stability piezoelectric oscillator |
JP2016162800A (en) * | 2015-02-27 | 2016-09-05 | 株式会社東京精密 | Dicing device and table for dicing device |
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