JPS60140873A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60140873A JPS60140873A JP58250067A JP25006783A JPS60140873A JP S60140873 A JPS60140873 A JP S60140873A JP 58250067 A JP58250067 A JP 58250067A JP 25006783 A JP25006783 A JP 25006783A JP S60140873 A JPS60140873 A JP S60140873A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- forming
- type layer
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は、３次元半導体装置にかかり、特に０Ｍ０３回
路の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a three-dimensional semiconductor device, and particularly to a semiconductor device with an 0M03 circuit.
（２）技術の背景
近年、半導体製造技術の進歩に伴い、高集積度のＬＳＩ
が製造される要請が高まるとともに、３次元半導体装置
が提案されて来た。３次元半導体装置は、ディバイスを
平面的に並べた従来の半導体装置に対して、製造工程が
多くなるが、集積度が向上するという利点がある。(2) Technology background In recent years, with the advancement of semiconductor manufacturing technology, highly integrated LSI
As the demand for manufacturing semiconductor devices increases, three-dimensional semiconductor devices have been proposed. Although three-dimensional semiconductor devices require more manufacturing steps than conventional semiconductor devices in which devices are arranged in a plane, they have the advantage of improved integration.
（３）従来技術と問題点 しかしながら、３次元半導体装置では、高集積１− 一つにＣ 度のため、各ディバイスが極めて近接して形成される。(3) Conventional technology and problems However, in three-dimensional semiconductor devices, highly integrated 1- C in one Due to the high density, each device is formed in close proximity.
従って３次元半導体装置では特に互いに近接したディバ
イスが同時にオンしている場合等には２局所的な発熱が
大となるため１発熱による装置の信頼性が低下し、また
動作特性の劣化をきたすという欠点があった。Therefore, in a three-dimensional semiconductor device, especially when devices close to each other are turned on at the same time, two localized heat generation becomes large, which reduces the reliability of the device due to one heat generation and also causes deterioration of operating characteristics. There were drawbacks.
（４）発明の目的
本発明は上記従来の欠点に鑑み、３次元半導体装置の発
熱による温度上昇の問題を防止することを可能にした半
導体装置を提供することを目的とするものである。(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention aims to provide a semiconductor device that makes it possible to prevent the problem of temperature rise due to heat generation in a three-dimensional semiconductor device.
（５）発明の構成
そしてこの目的は本発明によればｐチャンネルＭＯＳ
Ｆ ＥＴとｎチャンネルＭＯ３ＦＥＴを積層し、上下に
積層したＭＯＳＦＥＴは同時に導通状態にならないこと
を特徴とする半導体装置を提供することによって達成さ
れる。(5) Structure of the invention and this object according to the invention is a p-channel MOS
This is achieved by stacking an FET and an n-channel MO3FET, and providing a semiconductor device characterized in that the MOSFETs stacked one above the other do not become conductive at the same time.
（６）発明の実施例 以下本発明の一実施例を図面に基づいて詳述する。(6) Examples of the invention An embodiment of the present invention will be described below in detail with reference to the drawings.
２−
第１図は本発明による３次元半導体装置の製造方法の工
程図である。2- FIG. 1 is a process diagram of a method for manufacturing a three-dimensional semiconductor device according to the present invention.
同図において＋８）からｆｇ）までは製造工程の順序を
示す。In the figure, +8) to fg) indicate the order of manufacturing steps.
以下製造工程を説明する。The manufacturing process will be explained below.
第１図（ａｌに示す工程に於てｐ型シリコン基Ｉｆｊ、
１上に厚さ ５００人に酸化シリコン膜２（ＳｉＯ２）
を形成し、さらに厚さ１５００人に窒化シリコン膜３（
Ｓｉ３Ｎａ）膜を形成する。次に工程ｆｂｌにおいて、
窒化シリコン膜３をマスクとしてｐ型シリコン基板１を
９５０ °Ｃの雰囲気中でフィールド酸化しシリコン酸
化膜４を形成する。次に第１図（Ｃ）に示す工程でｐ形
シリコン基板１」二に４００人の厚さのゲート酸化膜５
を形成し、さらにノンドープのポリシリコン層６をゲー
ト酸化膜５上に形成する。In the step shown in FIG. 1 (al), p-type silicon base Ifj,
Silicon oxide film 2 (SiO2) on 1 and 500 thick
, and then a silicon nitride film 3 (
Form a Si3Na) film. Next, in step fbl,
Using the silicon nitride film 3 as a mask, the p-type silicon substrate 1 is field oxidized in an atmosphere at 950° C. to form a silicon oxide film 4. Next, in the process shown in FIG.
A non-doped polysilicon layer 6 is further formed on the gate oxide film 5.
第１図（ｄｉに示す工程では工程（ＣＩで形成したゲー
ト酸化膜５及びノンドープシリコン層６上に砒素イオン
（Ａｓ）をイオン注入法により、１５０キロエレクトロ
ンボルト（ＭｅＶ）のエネルギーを加えて３ Ｘ Ｉ
Ｑ”ｃｍ’のドーズ量にて注入しｎ型層７を形成する。In the process shown in FIG. X I
The n-type layer 7 is formed by implanting at a dose of Q"cm".
工程（ｅｌでは気相成長法により酸化シリコン膜４及び
ゲート酸化膜５とｎ型層７」二に３０００人の厚さにＰ
ＳＧ （リン珪酸ガラス）８を成長させ、さらにＰ２Ｏ
３上に５０００人の厚さに酸化シリコン膜９を形成させ
眉間絶縁膜とし、さらに酸化シリコン膜９」二に４００
０人にポリシリコンＮＩＯを成長させる。In the EL process, a silicon oxide film 4, a gate oxide film 5 and an n-type layer 7 are deposited to a thickness of 2 to 3,000 cm using a vapor phase growth method.
SG (phosphosilicate glass) 8 is grown, and then P2O
A silicon oxide film 9 is formed to a thickness of 5,000 mm on 3 to form an insulating film between the eyebrows, and then a silicon oxide film 9 of 400 mm thick is formed on the silicon oxide film 9.
Grow polysilicon NIO on 0 people.
この後、１０５°Ｃで窒素アニールを２０分間行ないＰ
ＳＧ８をリフローする。またポリシリコン層１０にはア
ルゴンレーザを５ｃｍ／ｓのスピードでスキャン照射し
てシリコン（Ｓｉ）の単結晶化させる。After this, nitrogen annealing was performed at 105°C for 20 minutes and P
Reflow SG8. Further, the polysilicon layer 10 is scanned and irradiated with an argon laser at a speed of 5 cm/s to single-crystallize silicon (Si).
次に第１図（ｆｌに示す工程でリン（ｐ）イオンに１０
０キロエレクトロンボルト（ＫｅＶ ）のエネルギーを
加えて＋ ３ Ｘ Ｉ Ｑ１′ｃｍ’のドーズ量にて前
述のシリコンに注入し、ｎ型９９１７層１１を形成して
上層ｐチャンネルＭＯＳトランジスタのｎ型シリコン基
板とする。Next, in the step shown in Figure 1 (fl), phosphorus (p) ions are
The above-mentioned silicon is implanted with an energy of 0 kiloelectron volts (KeV) and at a dose of +3×IQ1'cm' to form an n-type 9917 layer 11 to form the n-type silicon of the upper layer p-channel MOS transistor. Use as a substrate.
第２図ＦＡに示す工程では酸化を行ない酸化シリコン膜
からなるゲート酸化膜１２をｎ型層１１の上に形成し、
このゲート酸化膜１２の上にポリシリコン層を形成し、
さらにポロン（Ｂ）イオンを５０キロエレクトロンボル
トのエネルギーを加えてＩ Ｘ １０” ｃｍ−’のド
ーズ量にて注入しｐ型層１３を形成する。 さらにゲー
ト酸化膜１２及びｐ型Ｊｉｆ１３上に気相成長法により
ＰＳＧＩ４を成長させる。最後にＰＳＧＩ ４に窓開け
してアルミニウム電極（図示せず）をＰＳ’Ｇ１４上に
形成する。In the step shown in FIG. 2FA, oxidation is performed to form a gate oxide film 12 made of a silicon oxide film on the n-type layer 11,
A polysilicon layer is formed on this gate oxide film 12,
Further, poron (B) ions are implanted with an energy of 50 kiloelectron volts at a dose of I x 10"cm-' to form a p-type layer 13. Further, a p-type layer 13 is formed on the gate oxide film 12 and the p-type Jif 13. PSGI 4 is grown by a phase growth method.Finally, a window is opened in PSGI 4 and an aluminum electrode (not shown) is formed on PS'G 14.
本発明の半導体装置の製造方法は上述の工程（ａ）から
（ｇｌによって構成される。The method for manufacturing a semiconductor device of the present invention is comprised of the above-mentioned steps (a) to (gl).
第２図は上述の工程によって製造されたＣＭ○Ｓインハ
ーク構造に電極窓を開口して電極端子及び接地端子を接
続した図である。FIG. 2 is a diagram in which an electrode window is opened in the CM○S in-harc structure manufactured by the above-described process and an electrode terminal and a ground terminal are connected.
第３図はさらに第２図のＣＭＯＳインバータ回路の等価
回路図である。FIG. 3 is further an equivalent circuit diagram of the CMOS inverter circuit of FIG. 2.
第３図においてｐチャンネルＭＯ３ＦＥＴ１５のドレイ
ンとｎチャンネルＭＯ３ＦＥＴ１６のドレインとが接続
して出力端子（ＶＯＬ、Ｔ）となり、ｐチャンネルＭＯ
３ＦＥＴ１５のソースは電源（５−
Ｖ、ｏ）に接続され、ｎチャンネルＭＯＳ Ｆ ＥＴ１
６のソースは接地される。In FIG. 3, the drain of p-channel MO3FET 15 and the drain of n-channel MO3FET 16 are connected to form an output terminal (VOL, T),
The source of 3FET15 is connected to the power supply (5-V, o), and the n-channel MOS FET1
The source of 6 is grounded.
またｐチャンネルＭＯ３ＦＥＴ１５とｎチャンネルＭＯ
３ＦＥＴ１６のゲート端子は共に入力端子（Ｖ、Ｎ）に
接続している。Also, p-channel MO3FET15 and n-channel MO3FET15
The gate terminals of the 3FET 16 are both connected to the input terminals (V, N).
以上の第３図の回路構成を第２図のＣＭＯＳインハーク
半導体装置の構造図と対応すると、出力端子ｖ ｏｕ’
ｒは下層ｎチャンネルＭＯ３ＦＥＴ１６のドレインを形
成するｎ型層７と上ＮｐチャンネルＭＯ３１４Ｔ１５の
ドレインを形成するｐ型層１３に接続し、電源Ｖ０．．
は上層ｐチャンネルＭＯ３ＦＥＴ１５のソースを形成す
るｐ型層１３に接続し、下層ｎチャンネルＭＯ３ＦＥＴ
Ｉ ６（７）ソースを形成するｎ型層７は接地される。If the above circuit configuration in FIG. 3 corresponds to the structural diagram of the CMOS in-hark semiconductor device in FIG. 2, the output terminal v ou'
r is connected to the n-type layer 7 forming the drain of the lower n-channel MO3FET 16 and the p-type layer 13 forming the drain of the upper Np-channel MO314T15, and is connected to the power source V0. ．．
is connected to the p-type layer 13 forming the source of the upper layer p-channel MO3FET 15, and the lower layer n-channel MO3FET
The n-type layer 7 forming the I6(7) source is grounded.
またゲート端子の共通接続は下層ｎチャンネルＭＯ３Ｆ
ＥＴ１６のゲー１〜を形成するｎ型層７と上層ｐチャン
ネルＭＯ３ＦＥＴ１５のゲートを形成するｐ型層１３と
を酸化シリコン９に窓を開は接続することに対応するが
、この接続は第２図には図示されていない。Also, the common connection of the gate terminal is the lower layer n-channel MO3F
This corresponds to connecting the n-type layer 7 forming the gates 1 to 1 of the ET 16 and the p-type layer 13 forming the gate of the upper p-channel MO3FET 15 through a window in the silicon oxide 9, and this connection is shown in FIG. Not shown.
＝６−
本発明では上下層の間に眉間絶縁膜を設け、上層と下層
にｐチャンネル間Ｏ３ＦＥＴ、！＝ｎチャンネルＭＯ３
ＦＥＴを積層構成した３次元のＣＭＯ８集積回路を形成
する。この事により、上層と下層の互いのＭＯＳＦＥＴ
は同時に導通状態になる事はない。=6- In the present invention, a glabellar insulating film is provided between the upper and lower layers, and p-channel inter-channel O3FETs are installed between the upper and lower layers. =n channel MO3
A three-dimensional CMO8 integrated circuit with stacked FETs is formed. This allows the upper and lower layer MOSFETs to
are never in a conductive state at the same time.
本発明の実施例は以上に限るわけではなく、ＣＭＯＳイ
ンバータ回路において１上下の層で上層をｎチャンネル
、下層をｐチャンネルとして構成することも可能である
。The embodiments of the present invention are not limited to the above, and it is also possible to configure a CMOS inverter circuit with one layer above and below, with the upper layer being n-channel and the lower layer being p-channel.
（７）発明の効果
以上、詳細に説明したように１本発明によれば上下層が
同時にオンするＭＯＳトランジスタの組合せを回避する
ことで、集積回路の発熱の問題を解決し、従って集積回
路自体を小さくすることができ、さらに装置自体を小型
化することができるという効果を有する。(7) Effects of the Invention As explained in detail above, according to the present invention, by avoiding the combination of MOS transistors in which the upper and lower layers are turned on at the same time, the problem of heat generation in the integrated circuit is solved, and therefore the integrated circuit itself This has the effect that it is possible to reduce the size of the device, and furthermore, the device itself can be made smaller.
第１図（ａｌ〜ｆｇｌは本発明による積層トランジスタ
を形成する半導体装置の製造方法の工程図、第２図は第
１図の製造方法によって製造されたＣＭＯＳインバータ
回路に端子を接続した構成図、第３図は第２図のＣＭＯ
Ｓインバータ回路構成図の等価回路図である。
１・・・ｐ型シリコン基板 ２．４，９゜１２・・・酸
化シリコン膜 ３・・・
窒化シリコン膜 ５，１２・・・ゲート酸化膜 ７．１
１ ・ ・ ・ｎ型層
８．１４・・・ＰＳＧ ６，１０・
・・ポリシリコン層 １３・・・
ｐ型層 １５・・・ｐチャンネル間Ｏ
３ＦＥＴ １６−ｎチャンネルＭＯ
ＳＦＥＴ
第
３６１FIG. 1 (al to fgl are process diagrams of a method for manufacturing a semiconductor device forming a stacked transistor according to the present invention, and FIG. 2 is a configuration diagram in which terminals are connected to a CMOS inverter circuit manufactured by the manufacturing method of FIG. 1. Figure 3 is the CMO of Figure 2.
FIG. 2 is an equivalent circuit diagram of an S inverter circuit configuration diagram. 1... P-type silicon substrate 2.4,9°12... Silicon oxide film 3... Silicon nitride film 5, 12... Gate oxide film 7.1
1 . . . N-type layer 8.14...PSG 6, 10... Polysilicon layer 13... P-type layer 15... P-channel inter-channel O 3FET 16-n channel MO SFET No. 361
Claims (1)
ＴとｎチャンネルＭＯ３ＦＥＴを上下に積層してなるこ
とを特徴とする半導体装置。In a CMO3 semiconductor device, O3FE between p-channels
A semiconductor device characterized by stacking T and n-channel MO3FETs one above the other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58250067A JPS60140873A (en) | 1983-12-28 | 1983-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58250067A JPS60140873A (en) | 1983-12-28 | 1983-12-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60140873A true JPS60140873A (en) | 1985-07-25 |
Family
ID=17202309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58250067A Pending JPS60140873A (en) | 1983-12-28 | 1983-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60140873A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02263465A (en) * | 1988-11-05 | 1990-10-26 | Mitsubishi Electric Corp | Lamination type semiconductor device and manufacture thereof |
| JPH02271657A (en) * | 1989-04-13 | 1990-11-06 | Nec Corp | Double active layer cmos inverter |
| EP0442296A2 (en) * | 1990-02-16 | 1991-08-21 | Hughes Aircraft Company | A high speed silicon-on-insulator device and process of fabricating same |
| US5140390A (en) * | 1990-02-16 | 1992-08-18 | Hughes Aircraft Company | High speed silicon-on-insulator device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5513944A (en) * | 1978-07-17 | 1980-01-31 | Seiko Epson Corp | C-mos semiconductor device |
| JPS57204171A (en) * | 1981-06-10 | 1982-12-14 | Mitsubishi Electric Corp | Semiconductor device |
| JPS58210656A (en) * | 1982-05-31 | 1983-12-07 | Toshiba Corp | Laminated type cmos inverter device |
-
1983
- 1983-12-28 JP JP58250067A patent/JPS60140873A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5513944A (en) * | 1978-07-17 | 1980-01-31 | Seiko Epson Corp | C-mos semiconductor device |
| JPS57204171A (en) * | 1981-06-10 | 1982-12-14 | Mitsubishi Electric Corp | Semiconductor device |
| JPS58210656A (en) * | 1982-05-31 | 1983-12-07 | Toshiba Corp | Laminated type cmos inverter device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02263465A (en) * | 1988-11-05 | 1990-10-26 | Mitsubishi Electric Corp | Lamination type semiconductor device and manufacture thereof |
| JPH02271657A (en) * | 1989-04-13 | 1990-11-06 | Nec Corp | Double active layer cmos inverter |
| EP0442296A2 (en) * | 1990-02-16 | 1991-08-21 | Hughes Aircraft Company | A high speed silicon-on-insulator device and process of fabricating same |
| US5140390A (en) * | 1990-02-16 | 1992-08-18 | Hughes Aircraft Company | High speed silicon-on-insulator device |
| EP0442296A3 (en) * | 1990-02-16 | 1993-12-15 | Hughes Aircraft Co | A high speed silicon-on-insulator device and process of fabricating same |
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