JPS60140597A - Eprom programmer - Google Patents

Abstract

PURPOSE:To allow the automatic shift of respective modes such as the erase check, writing, the program and the verify check by resetting a ring counter by a one-cycle termination signal where a binary counter generates. CONSTITUTION:The output ''1'' of a two-input OR72 is inputted to a three-input NAND57 from an inverter 73, a ring counter 58 is reset, and an F.F62 is reset from an inverter 61. Then, a termination pilot lamp 21 is lit up. When the EPROM program is normal, the output of a comparison circuit 69 becomes ''1'' and the output of a three-input NOR77 becomes ''0'', and therefore, a signal 22 does not light up. When a binary counter 46 counts 100 clock pulses, the output ''1'' of te ring counter 58 is shifted to a Q4, the ring counter 58 is self-reset from an inverter 79 and the three-input NAND57, and restoration is executed to the initial erase check position. Automation and energy saving can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an EPROM programmer for a sequence controller, and in particular, erase checking, writing, and programming are performed using a ring counter that is shifted by a one-cycle completion signal issued by a binary counter that counts clock pulses. , verify check, and reset modes are automatically shifted in sequence.

The present invention is disclosed in the applicant's patent application No. 022533 of 1973.
Added erase check and verify check functions to the photoelectric EPROM programmer.

A ring counter automates a series of EPR and OM program cycles starting from erase check mode and ending with write, program, verify check and reset modes.

In the EPROM programmer of the present invention, the data manual device uses a known photoelectric or magnetic sheet reader. In the photoelectric type, the program sheet passed between the sheet leader is pasted with light-shielding adhesive tape on a transparent film according to a predetermined time chart, and in the magnetic type, the time chart is pasted on a non-magnetic film. Attach the magnetic tape according to the instructions. All of them are visible just by cutting and pasting, so it is easy to program and change them.

Turn on the power, insert the EPROM into the device, and erase it.
Press the check switch. If there is no abnormality, the ring counter is shifted to the write position in about 01 seconds. Therefore, move the program/-to a predetermined position from one side of the device.
Insert with −j and pull out the sat from the opposite side. During this time, each gate continues to operate from the ring counter to write, program, and verify check.Finally, the ring counter self-resets, the end signal light lights up, and the program ends. This required time is approximately 8 seconds.

If an abnormality is detected in the erase check and verify check, both the abnormality signal and the end signal light up.

Illumination of the end signal indicates that the ring counter has been reset and returned to its initial position. Therefore, replace the EPROM and perform the program operation again.

As described above, the EPROM can be programmed very easily and quickly using this device, and is highly reliable because it has undergone erase and rK verify checks.

SUMMARY OF THE INVENTION An object of the present invention is to provide an EPROM programmer that automates a series of program cycles starting from a ring counter erase check mode.

Another object of the present invention is to provide an EPROM programmer in which the data manual device is an optical two-sheet reader and the programming cycle is automated.

Still another object of the present invention is to provide an EP, R'OM programmer in which the data manual device is a magnetic sheet reader and the programming cycle is automated.

Hereinafter, among the EPROM programmers of the present invention, embodiments of photoelectric EPIt and OM programmers will be described first.

In FIG. 1, 1 is a transparent film, 2 is a write timing clock mark, and 3 is a control line for issuing write and read commands, both of which are printed with light-shielding ink.

4 is a large number of parallel data lines, and 5 is a scale divided into 100 equal parts.

The write timing mark generates a write timing clock pulse as described below.

The R/W line automatically switches between writing and reading, and the Cheetah line creates a time chart directly on the program sheet by pasting light-shielding adhesive tape on it.

The scale m6 of the outer A law of the data line is on the extension line of the 100 equal division scale 5. A time chart is created in parallel by pasting the light-shielding tape 7 according to the scale line 6 (FIG. 2).As is clear from the diagram, the scale line 6 passes through the center between the clock marks. This is to avoid miscounting even if the end of the tape is somewhat poorly finished.

8 is a positioning index when inserting the program film into the device, and 9 is an arrow indicating the film insertion direction. Write clock mark.

A parallel data line of 100 lines and 8 strokes is standard.

Figure 2 shows a time chart of 8 strokes created by pasting light-shielding adhesive tape. The tentative line a-a is the position of the line of action of the sheet leader, which will be described later, when this film is inserted into the device at the position mark 8.

The program film of the photoelectric type EPR and OM programmer has been explained above. The program film of the magnetic type EPII and OM programmer has the same external dimensions as the photoelectric type, but the film 1 is made of non-magnetic material and the timing - The clock mark 2 and the R/W line 3 are each printed with magnetic material, and the data 7 is composed of adhesive magnetic tape.

The magnetic EP, R, OM programmer differs in that it is composed of a film reader that uses a well-known Hall element, and the circuit for programming data into the EPROM and the external structure of the main body are almost all photoelectric type. Since it can be used as is, the following explanation will be based on the photoelectric type EPR,0M programmer.

Figure 3 shows the optical 1'3 PROM programmer of the present invention.
FIG. The main body is constructed by combining front and rear panel boards 10 and 11 and two upper and lower shells 12 and 12 made of metal plates. 13 is a power switch, 14 is a program sheet insertion slot, 15 is a power cord, 16
17 is a fuse, and 17 is an E. 1) A ROM is detachably attached to a connector 19 by a lock lever 18. 2
0 is an erase check switch, 21 is an end indicator light, 22 is an error indicator light, and 23 is a sort leader.

As is clear from the cross-sectional view of FIG. 4, the sheet leader has a light-emitting plate 25 on which the light-emitting elements 24 are arranged and a light-receiving plate 27 on which the light-receiving elements 267 are arranged, which are connected with a mark and solder so as to face each other. A gap 28 is formed through which the sheet passes, and the sheet is inserted into and held in the slits formed in the nine-panel panels 10 and 11. A printed wiring board 29 is fixed to the light emitting board 25,
Further, a printed wiring board 30 is fixed to the light receiving panel 27, and a memo IJ-1, C, a gate IC, and a crystal oscillator 31 are mounted on this.
．． capacitors, resistors and.

Connector 19 for attaching and detaching El"ROM etc. is connected.

As is clear from FIG. 4, a guide part 32 for inserting and holding the printed wiring board 30 into the inner surface of the panel board 1.0.11, and a guide part 33 for inserting and holding the two upper and lower shells 1.2.12', respectively. It is formed.

FIG. 5 is an example of a photoelectric switch array consisting of a light emitting diode 24 and a phototransistor 26. 1st
R corresponding to the R/W line of program sheet 1 in the figure
/W photoelectric switch 1 set, T photoelectric switch 1#l corresponding to write timing clock mark, and corresponding to data line.

D2...D6 8 sets of light wake-up switches 9 A total of 10 sets of photoelectric switch circuits are arranged in a row.

The output of each photoelectric switch circuit is waveform-shaped by a Schmitt circuit 34 and output. In the R/W photoelectric switch and the T photoelectric switch, when the light from the light emitting diode 24 is blocked by the light-blocking portion of the program film 1, the corresponding phototransistor 26 is turned off, and its output becomes 1''', which is the output of the Schmitt circuit 34. becomes °゛0″. In addition, in the transparent part, the corresponding phototransistor 25 is ON and the output is 0'', and the output of the Schmitt circuit 34 is It l I
Becomes I.

On the other hand, in each photoelectric switch of D8, the output of the phototransistor is an emitter follower. Therefore, in the light-shielded part of the program film l, the output of the Schmitt 34 is 1"'. , and "o" in the transparent part.

Figure 6 shows a read-only model that operates from a +5V single-power supply.
FIG. 2 is a circuit diagram of a photoelectric 1) I) FtOM programmer for programming data into the memory EPI"tOMI7.

System power supply Vcc is obtained from AC/DC converter: 35h, EPILOM 17117) VppK supply Mt + 2sVHDC! /DC converter 36 to Vc
Set up C and get the result. The DC/DC converter 36 supplies +25V to the vpp terminal when the signal applied to the human power 37 is "o".

When the signal is °゛1'', the supply is cut off.

The single power supply EPROM 17 applies an N-bit program pulse to each address to be programmed, advances the address sequentially, and completes the program in one loop. At this time, the program pulse applied to GE/PRG is about 50 m5 per l address.

In order to obtain this 50 m5 program pulse, the oscillation frequency of the crystal oscillator 31 is determined, and this is set in the first frequency dividing circuit 38.
After that, the frequency is divided by the second frequency dividing circuit 39, and the frequency divided by 2 is outputted QA, Q.
B. Input QO and QD into 4-person NAND 40. Erase check mode During write mode and verify mode, the second frequency divider circuit is reset.
Divide output is stopped, but QA during program mode
, QB, and output pulses from QO9QD. and the seventh
As can be seen in the timing diagram, it takes 4 manpower for every 8 clock pulses counted by QA.
One read clock pulse is output from 40.

The frequency-divided outputs QA, QB, and QOQD are input to a four-man NOR41. QB and QClQD are each directly connected to the gate 41, but the width is input to the gate 41 via an inverter 42.

Therefore, as explained later, QA, QB, Qo, Q
n], OOO, the gate 41 sets F-F51, QA+Q"+Qo, Qn is 1111, and the gate 40 resets F-I"51.

Program pulse is 87-pRa of EPROM17
'If continue applying. These four rooms are about 50m5.

When the power switch 13 is turned on, the initial reset circuit 43 generates a differential pulse of °'1'' to reset all circuits. Cleared 46.

B, 2 manpower N A, P via ND 47, F4B
is a reseriton, and its Q output "o" allows two people to power N
A, N D49 outputs 1'', resets the second frequency divider circuit 39, stops outputting pulses, and all outputs QA, QB,
QO and QD are each fixed at "o". Therefore, the output of the four-manpower NAN I) 40 is fixed to "]" during the period when the second frequency dividing circuit 39 is reset.

C, F-F48's Q output "o" is also 2-man power NA,
F-F5] via N D 50, and O3/PR of EPROM+7 via inverter 52.
Input "θ'° into the ID P It OM f: data output state.

D, reset P-F1a via 2-man power N A N D 47, and 3-man power N0R54 with its Q output 1''
and two-manpower to close the gates of NA and ND55 respectively.

E, inverter 56, 3 manual power NA, ND 57
The ring counter 58 is reset via the . At that time, the output (q is "'1"', Q, Q2, Q3 and q are °'0', and as described later, the 1 cycle end signal "o
“1” is input every time “1” is input to its clock terminal C.
The position of is Q. −+Q, →Q2→Q3→Q, and is shifted. Q corresponds to erase check (E), Ql corresponds to write (W), Q2 corresponds to program (P), QA corresponds to verify check (V), and Q4 corresponds to reset.

F, F'-F”6 via 2-man power N A N D 59
0 is reset, and the abnormality indicator light 22 remains off.

G, F, ]” 62 is reset via the inverter 61, and the 9 indicator light 21 is turned on.

Attach the EPROM 17 to the connector 19 and press the erase check switch 20. 2 person power ANI
) 63 output is “o”, which is EPROM
input to i to set the data output state. Also 2 manpower N
The output of the A N D 64 becomes °゛1'', which is F'- through the one-shot pulse generation circuit 65 including a delay circuit.
Set F1a, 3-man power NOR, 54 and 2-man power N
Open the gate of A N D 55. On the other hand, positive "o"
is input to the one-shot pulse generation circuit 66 including a delay circuit, and the differential pulse of the output "o" is F, F'60.
and set F-F21.

Therefore, the clock pulse of the first frequency divider circuit 38, whose reset terminal R is grounded and is always in an output state, is sent to the gate 5.
5 and to the clock terminal of the binary counter 46 via the gate 67 which is open.

And address line Q. , Ql...Q6
Specify the address of EPROM17 via
A decouple is output from lines Dl, D2...D. However, the three-state buffer circuit 68, which is connected to the output °'16 of the two-power N A N D 49, closes its gate, and the output V of the ring counter 58, QA, is "1'". Since the gate of circuit 69 is closed, EPR and OM data are output.
, D2...D8 are all input to 8-man power AND70.

If there is even one O'' in the 8-bit 100 words of D8, it will be 8-man power A N D 7
If the output is 0, it becomes "O", and this is applied to the three-man power NO switch 71. Ring counter 58 Q. "o" of output E
" has already been input to the gate 71, so at the falling edge of the timing pulse TP (differential pulse synchronized with the clock pulse), all three outputs become "O", and the gate 71 becomes "O".
l ” is output.And the output of 2-man power 0R72”
1'' sets F-F2O and turns on the abnormality indicator light 22.

On the other hand, the output "'l" of the two-man power 0R72 is output by the inverter 73.
57 to reset the ring counter 58' and also input the inverter 6
1 to reset the F-F62 and turn on the end indicator light 21. Therefore, replace the EPR and OM and check again.

If EPROM17 is normal, 8 person power A N D 70
The output of the 3-man power NOR71 is "°°1".
o”.On the other hand, the V output “1” of the ring counter 58 is input, and the output of the three-man power N0R77 is °゛0.
”The beam is not set.

Then, the binary counter 46 counts 100 clock pulses, and when the three-man power NAND 74 outputs the one cycle end signal "0", the ring counter 5
8's output II], II is shifted from q to Ql. Also] cycle end signal “o” is 2-man power NA
Clear the binary counter 46 via N D 45 and F- via N A N D 47
F1a is recessed l-1. , 3-man power NOR, 54 and 2-man power N A, N'D 55 gates were closed and the output of timing pulse TP was stopped.

The output of 2-man power NA, ND 55 is fixed at "l".

Therefore, insert program sheet 1 from the heavy equipment insertion slot to index 8.
Insert up to The output of R/W photoelectric switch is °゛0″
This is the gate of the differential pulse generation circuit 75.

Rasano and pull out. In the process, a write timing clock pulse is output from the photoelectric switch circuit T, and the binary counter 46 is outputted via the opened gate 67.
input to the clock terminal C of the address line Q, ,Q
, . . . specifies the corresponding address of R and AM76 via q. On the other hand, the output of the gate 67 applies a differential pulse synchronized with the write clock pulse to the R/W i terminal of RA, M 76 via the differential pulse generating circuit 75.

According to the command of the differential pulse, the photoelectric switch D11)2.
. . . From D8, the data of eight parallel steps shown in FIG. 2 is written to the address specified by the binary counter 46.

Then, when binary counter 46 counts 100 write clock pulses, the output of gate 74 is 0''.
Then the binary counter 46 is cleared and the ring
The output cover 1'' of the counter 58 is shifted to Q2(P) and enters the program mode.
passes through the note reader 23, the output of the R/W light awakening switch becomes "1" and the two-man power N A, N
Enter "1" in D49. So a, the ring
The P output cover O''' of the counter Q2 sets the F-F48 through the one-shot pulse generation circuit 77 including the delay circuit and the inverter 78, and manually inputs "1" to the four gates. At II, the gate 49 inputs "0" to the R terminal of the second frequency dividing circuit 39. Therefore, the frequency divided outputs QA, Qa, Q.

and QDs output pulses all at once.

b.9 as evident in the timing diagram of Figure 7.
4 manpower N A for every 8 clock pulses counted by a person
One read clock pulse is output from ND 40, QA, QB, QO and QD are 1000 and gate 41 is set to F-F5], QA, Q.

When QO and Qn are 1111, the gate 40 resets F and P5, and the program pulse is reset to PROM1.
7 continues to be applied to C8/PRG. This period is about 50m
It is 5.

C, since the output of the gate 49 is "o", three steps=1...the gate of the buffer circuit 68 is opened.

d, 1%/W The gate of the differential pulse generation circuit 75 is closed by the output "l" of the optical switch, and T% A,
Since the Y/'w terminal of M76 is also fixed to "]", data input stops and the cheater enters the output state.

e, Q of ring calafter 58, (P) "o" of output P is DC/DC! Input to converter 36 and convert to EP
+25V is supplied to the Vi)l) terminals of RO and M.

The read clock pulse is input to binary counter 46 through gate 67 and its address line Q
,,,Q,...R A, M 7 corresponding to q
6 and EPR, specify the address of 0M17. The data previously written to the RAM is then sequentially programmed into the specified EPROM address in synchronization with the read clock pulse.

When the binary counter 46 counts 100 read clock pulses, the gate adjustment 4 outputs a one cycle end signal "o". This signal causes a, binary
The counter 46 is cleared and the output "'1" of the ring counter 58 is shifted to Q3 (V) to enter the verify check mode.

b. The F-Pi 8 is reset through the gate 47, and the second frequency dividing circuit 39 is reset through the gate 49 to stop the frequency division output, and the output of the 4-man power N A N D 40 is "1".
”.

C, I of the output V of the ring counter Q3 to the gate 64
Input I OII and set F-F'53 to open the gates of 3-man power N0R54 and 2-man power NAND 55.

d, three-state signal at output “1” of gate 49
The gate of the buffer circuit 68 is closed, and "'0" of the output V of the ring counter Q3 is input to the comparator circuit 69 to open the gate.

The clock pulse of the first divider circuit, 38, is input to the binary counter 46 via gate 55 and gate 67 to its address line Q. IQ+...Displays the address of RAM 76 and EPROM]7 corresponding to Q6.

The data written in the RAMK and the data programmed in the EPROM are respectively output and compared by a comparison circuit 69. If they do not match, "0" is applied to the N0R77. Since "0" of the Q3 output V of the ring counter 58 has already been input to the gate 77, all three outputs become "0" and "1" at the falling edge of the timing pulse TP.
Output. And the output "1'" of two-man power is F-
Ii"60 and turn on the abnormality indicator light 22.

On the other hand, two-person OR? 2 output “1” is inverter 7
3 to input the three-person power N A N D 57 through 3, reset the ring counter 58, and also
The P-F 62 is reset via the terminal and the completion indicator light 21 is turned on.

In this case, the EPE erase OM is replaced without waiting for the completion of one cycle of the verify check mode, and the operations from the erase check are repeated again.

If the EPR, OM program is normal, the output of the comparator circuit 69 is °゛1'' and the output of the 3-man power NO'R77 is 0.
'', and the signal 22 does not light up. Then, when the binary counter 46 counts 100 clock pulses, the output II I II of the ring counter 58 is shifted to q, and the inverter 79.3 manual power N A N D
57, the ring counter 58 is self-reset and returned to the initial erase check position. At the same time, P-F62 is threaded through the inverter 61, and the end indicator light 2
1 lights up to indicate that the program is complete. Wait for this display and then remove the EP r (OM).

By attaching the programmed EPROM to a small read-only sequence controller, automation and labor saving of all types of equipment can be easily achieved.

It should be noted that the present invention is limited to the above-described embodiments, but it goes without saying that various modifications may be made.

Furthermore, although the present invention has been described with reference to an EPROM, it goes without saying that the present invention is not limited to an EPROM, and can be applied to PR, OM, EE PR, OM, and various other non-volatile memories.

[Brief explanation of drawings]

Figure 1 shows an example of a program sheet, Figure 2 shows a time chart created on a hub program notebook, Figure 3 is a perspective view of a photoelectric λEPR, OM programmer, and Figure 4 shows its 5 shows a circuit diagram of the photoelectric switch array, FIG. 6 shows an overall circuit diagram, and FIG. 7 shows a timing diagram. ■・・・・・・Film, Di・・・・・・・Timing clock mark for writing, 3・・・・・・・
・R, /W line. 4...Cheetah line, 7...
...Light-shielding adhesive tape, 10. II...Panel board, 13...Power switch, 14
・・・・・・Program sheet insertion slot. 17......EPROM, 20...Erase check switch, 21...End indicator light, 22...Error indicator light, 23... ...
/-T leader, 31...Crystal oscillator, 35
・・・・・・・・・A c/DC converter, 36...
...DC/DC converter, :38...First frequency dividing circuit, 39...Second frequency dividing circuit, 43.
...Initial reset circuit, 46...
...Binary counter, 58...
...Ring counter, 65...One-shot differentiator circuit including delay circuit, 66...
...Differentiating circuit including delay circuit, 68...Full three-state buffer, 69...Comparison + h path, 74...1 cycle completed circuit,
75... Differential pulse generation circuit, 76...
・・・・・・・・・RAM, 77・・・・・・・・・
Differential circuit including delay circuit. Applicant: Yoshi Kuze - Figure 3, Figure 11, Figure 4, Figure 5, Procedural Manual (Method) April 21, 1980 Director General of the Patent Office Kazuo Wakasugi 1, Indication of Case Patent Application No. 245072 of 1988 No. 2
, Title of the invention: EPROM programmer-3, Relationship with the person making the amendment Patent applicant address: 1-31-3-4 Higashimagome, Ota-ku, Tokyo Date of amendment order: March 7, 1980 (shipment date: March 27th) 5. Subject of correction Drawing (full drawing) 6. Contents of correction

Claims (1)

[Claims] 1 longitudinally arranged write clock marks;
a sheet reader that passes through the program sheet bearing R, W lines and multiple data lines to control read and write, and issues write clock pulses, R, /W line outputs and data outputs; W
A gate is actuated by the output from the write clock pulse, and R A, M for storing the data in synchronization with the write clock pulse, a read clock pulse generator for reading data, and a program sheet pass through R. a gate device which is actuated by the disappearance of the /W line output to generate the read clock pulse, and in synchronization with this, applies a program pulse to the EPR and OM to program the data written in the RAM into the EPROM; The ring signal is shifted by the one cycle end signal generated by the binary counter counting the clock pulses in the Ell, 0M programmer.
Each output of the counter is distributed to erase check mode, write mode, program mode, verify check mode, and reset mode, respectively, and the gate device of each mode is engaged with the gate device of the EPROM programmer. The gate automatically shifts each mode to the next mode in order, and resets the ring counter when the mode goes through one cycle, and generates a signal to reset the ring counter when an erase or verify error is detected. EPROM programmer consisting of equipment-0