JPS60140434A - Scheduler timer - Google Patents

Abstract

PURPOSE:To decrease the number of timers by outputting a reset signal with a microprocessor receiving an output of an FF latching the leading of a reference clock generating circuit so as to represent the count of the reference clock into plural registers. CONSTITUTION:The leading of a clock generated from a reference clock generating circuit 1 is latched by the FF2, an input/output port 3 to the FF2 and a count setting RAM11 are controlled by the microprocessor (MPU)4, for example exciting phase switching time setting registers 9, 10 are provided respectively to two step motors 7, 8 so as to control the MPU4. That is, the MPU4 detects the output 1 of the FF2 and also outputs a reset signal to the FF2, and when the content of the register 9 is not zero, ''1'' is decremented one after another, and when the content reaches zero, the exciting phase of the motor 7 is switched. Similarly, in controlling the motor 8, the registers 9, 10 are used in place of timers.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing generation method in a microprocessor system.

Conventionally, in a microprocessor system, in order to rotate a number of step motors or operate multiple magnets, a timer is used for each of the multiple motors and multiple magnets to control the excitation time. Was. Therefore, many timers were required.

According to the present invention, timer count registers are prepared as many as the number of timers conventionally required, and necessary counts are set in each of these registers. Every time a pulse is received from the basic clock generation circuit, this count is subtracted and repeated until the count is reached.

When the count reaches zero, it is assumed that the necessary time has elapsed, and the excitation phase of the step motor is switched, the magnet is excited, or held.

In this way, by using the timer count register, the number of timers can be kept to the minimum necessary number.

The present invention includes a circuit that generates a basic clock waveform, a flip-flop circuit with a reset input that latches the rising edge of the clock, and an input port that inputs the output signal of the flip-flop to a microprocessor system. It consists of an output port that outputs a reset signal to the 7 reset flop, multiple registers that set the count number, and a microprocessor that controls the input/output ports and registers.

The present invention provides a microprocessor system with a register that is subtracted at regular intervals, and uses this register instead of a timer to generate a large number of timers from a single oscillation source.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, the embodiment of the present invention has a basic clock generating circuit 1, a 7-lip/70-tub 2 with a reset input that latches the rising edge of the generated clock, and an output signal of a flip-flop 2. An input/output boat 3 for inputting and outputting (reset) No. 6, a random access memory 11 for setting a count for time setting, two step motors 7.8, and a driver circuit 6 for driving the step motors. and a register 9 for setting the excitation phase switching time of the stepping motor 7, a register 10 for the step motor 8, an input/output board 3, and a random access memory 1.
1, and a microprocessor 4 that controls the 1.

Next, FIG. 2 shows two step motors 7 according to this embodiment.
．． 8 is a flowchart showing a method for switching excitation phases when driving a motor. The program shown in this flowchart is included in the scheduler part of the program that controls the entire device. If the period of the scheduler is made shorter than the period of the basic clock, each time the output Q of the flip-flop 2 rises, the processor 4 can accurately count the time without dropping the signal. can be executed.

Further, FIG. 3 shows the basic clock generation circuit 1 shown in FIG.
2 is a time chart showing the output waveform of the flip-flop 2 with a reset input that latches the rising edge of the generated clock.

The operation of this embodiment will be congratulated in accordance with the flowchart shown in FIG. Processor 4 outputs W from flip-flop 2.
When it is detected that the value becomes 11, the flip-flop 2 outputs a heliset coefficient, and it is determined whether the contents of the timer count register 9 are zero. While the step motor 7 is stopped, this register 9 is set to zero, so control of the next step motor 8 is started. Since the register 9 is not set while the step motor 8 is rotating, 1 is subtracted from the register 9, and it is determined whether the result is zero. If it is not zero, the step motor 8 is controlled. After this operation consumes a time equal to the period of the basic clock multiplied by the value set in the timer count register 9, the timer count register 9 becomes empty. When the register 9 reaches zero, the processor 4 switches the excitation phase of the step motor 7, excites the next phase, and causes the step motor 7 to rotate once. Thereafter, the excitation time of the currently excited phase is set in the timer count register 9.

The step motor 8 is also controlled in the same manner as described above.

The present invention attempts to control a motor in this manner.

By simply assigning a timer count register to each magnet, etc., any number of control box timers can be added.

The present invention has the effect of reducing the number of timers by setting the basic clock and timer count register as described above.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram partially showing an embodiment of the present invention as a block diagram. FIG. 2 is an operation flowchart of the processor 4. FIG. 3 is a time chart showing the output waveforms of the basic clock generation circuit 1 and the flip-flop 2. ■・・・Basic clock generation route, 2. River: Clip flop, 3. Mountain, input/output boat, 4. Group.
Microprocessor, 5... Group flip-flop output signal, 6... Driver circuit, 7...
...Step motor, 8...Step motor,
9... Step motor 7 timer count register, 10... Timer count register for step motor 8, 11... Random access memory. 2nd leap

Claims (1)

[Claims] A basic clock generation circuit that generates a basic clock, a 7-lip-flop circuit with a reset input that latches the rising edge of the clock, an input port that inputs the output signal of the flip-flop circuit to the microprocessor system, and a flip-flop circuit that inputs the output signal of the flip-flop circuit to the microprocessor system. It has an output port that outputs a reset signal to the 70-tube, multiple registers that set the count number, and a microprocessor that controls the input/output boat register. Scheduler meeting timer as shown in .