JPS60137179A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To generate a field pulse in an element by integrating a voltage boosting circuit for the field pulse at a part of the circumference of an element chip. CONSTITUTION:The voltage boosting circuit 2-2 is provided to the output of a field pulse generator 1, and this circuit 2-2 consists of an insulating gate type field effect transistor Qc provided with capacity between the gate and source. When an output pulse f1 is applied to a terminal 4-1, a conductive MOSTQt turns on and off and the one-level voltage Vc developed at the source 7 is applied to a terminal 5-1 through capacity CB to raise the voltage by DELTAVF. The capacity CB is made much larger than parasitic capacity CC, and then the gate voltage of a charging MOSTQc rises above the drain voltage, thereby obtaining a high-voltage field.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a solid-state image sensor and an optical character reading device.

Alternatively, it relates to a photodetector element that sequentially scans a large number of photoelectric conversion elements in time and reads out a signal corresponding to an optical image of a subject.

[Background of the invention]

Solid-state image sensors require resolution comparable to that of image pickup tubes used in current television broadcasting, so
x'500 photoelectric conversion elements, switches for selecting the photoelectric conversion elements, and scanning circuits for opening and closing the switches are required. Therefore, MOS-LSI technology, which is relatively easy to integrate, is usually used. It is produced using The basic structure of an image sensor includes a horizontal scanning circuit, a vertical scanning circuit with an increment circuit, and a two-dimensional array area of photoelectric conversion elements including switches. Here, the scanning circuit differs depending on the type of image sensor.
type and CID type element (Charge Injecti
on Devices), both horizontal and vertical MOS
A shift register is used.

In addition, vertical is MOS shift register, horizontal is CCD
Alternatively, there is a type of element configured as a BBD shift register. Further, in the case of a MOS type element, examples of the photoelectric conversion element include a junction type photodiode and a commonly used amorphous photoconductive film.

Compared to the imaging electron tubes used in current television broadcasting, these solid-state image sensors are smaller, lighter, have lower power consumption, are maintenance-free, have no shape distortion, and are free from afterimages and
It has many advantages associated with solid-state technology, such as no burn-in, and is highly anticipated as a next-generation imaging device.

However, the solid-state image sensor described above requires a large number of clock pulses and field switching pulses (hereinafter abbreviated as field pulses) to drive the scanning circuit and the increment circuit, and the external circuit for driving is complicated. However, problems such as an increase in the number of pins of the package on which the device is mounted are occurring. C JP-A-56-119576). The increasing complexity of external circuits prevents solid-state cameras from becoming smaller and cheaper, and increasing the number of pins increases package prices, reduces reliability, and distorts video signals due to stray noise caused by stray capacitance between pins. This has led to factors such as making it difficult.

As a solution to these problems, it may be possible to integrate a field pulse or other generator of low frequency drive pulses with relatively low speed and power consumption on the image sensor chip, but it is difficult to obtain high voltage output. New problems will arise, such as:

[Purpose of the invention]

An object of the present invention is to obtain a high voltage output increment circuit 1 pivoting field pulse within an image sensor.

[Summary of the invention]

The present invention provides a voltage raising circuit at the output of a field pulse generator, and connects this raising circuit to an insulated gate field effect transistor (hereinafter referred to as
(abbreviated as MO8T).

[Embodiments of the invention]

The details of the present invention will be explained below using examples.

The configuration of the field pulse voltage increasing method of the present invention is shown in FIG. 1 is a field pulse generation circuit, 2-1 and 2
-2 is a voltage increase circuit, and 3 is a basic pulse input terminal that is the basis for producing field pulses.

4-1 and 4-2 are the output terminals of the field pulse produced by the field pulse generation circuit 1 (voltage increase circuit 2).
-1.2-2 input terminal) Also, 5-1.5=
2 is a high voltage field pulse output terminal. The illegal operation will be explained using the time chart shown in FIG. external circuit.

For example, the basic pulse ψ2 output from the synchronization signal generator.
is added to the field pulse generation circuit 1, and two-phase field pulses f, , F2 are produced within this circuit (here, the phase difference between the two-phase pulses is determined by the switch housed in the above-mentioned increment circuit). It is only necessary to be able to switch at 60 Hz, which is generally 180 degrees. However, the pulse duty ratio (the ratio of the 1" level period to the 10" level period) may generally be increased or decreased by a factor of 50 or slightly. .

The field pulse generation circuit 1 is MO8T like the image sensor.
Made with. Therefore, in the operation of MOST, the field pulse generated by the field pulse generation circuit 1,
That is, the pulses f, , f obtained at output 4-1.4-2
The "1" level voltage amplitude of 2 is lower than the voltage (DD) for driving the field pulse generating circuit 1. This voltage drop Δvf is given by the following equation.

Δ■, = N (VT + δ■T) ... (1) Here, ■
1 is the threshold voltage of MO8T, and δvT is the substrate effect voltage due to an increase in the MO8T teeth voltage. N depends on the configuration of the field pulse generation circuit 1, and N is an integer of 1 or more. For example, Vdd=9V, ■A=1■, δV, =I
(2) Even in the case of a one-step decrease (N,=1), which is the smallest decrease, only a decrease of ΔV=2V, that is, a voltage of 80 times Vdd, can be obtained. These pulses f,
, f2 are input to the voltage increase circuit 2-1.2-2, and its output 5-1.5-2 receives high voltage field pulses F1.
F2 is obtained (these pulses F, , F2 are applied to the aforementioned increment circuit). Here, pulse F
,・The “1°° level voltage vA of F2 is at least 766
In equation (2), the second term ΔV on the right side depends on the configuration of the voltage increase circuit 2-1.2-2, and Δ■ is a positive value of 0 or more. be. Therefore, T(''L pressure increasing circuit 2-1.2
−2, the voltage amplitude of the pulse f,, f2 is the voltage (Δ■
, +Δ■,).

Voltage increase circuits 2-1 and 2-2 may be the same circuit and 1
Various configurations are possible. An example of a specific configuration using MO8T is shown in FIG. In the same figure (a), Q
, is the transfer MO8T, Qc is the charge MO8T, Q, and Qdc are the discharge M, O3T. 4-1 is the input terminal of the above-mentioned pulse f, 6-1 is the discharge MO8T Q, , Qd
Input terminal for applying pulse f2 to open and close c, 5
-1 is the output terminal of the voltage increase circuit 2-1 mentioned above. Here, the explanation will be made with reference to the voltage increase circuit 2-1.

In the case of voltage increase circuit 2-2, connect 4-1 to 4-2, 5-1 to 5-2, and 6-1 to 6-2 (pulse f1 input terminal).
You can replace it with Furthermore, c.

is the capacitance (parasitic capacitance or additional manufacturing capacity) between the gate and source terminals of the charging MO8TQc. The operation of this circuit is shown in the same figure (bl
This will be explained using the time chart shown in . Terminal 4-1
When the output pulse f1 of t6. After (time 1,) terminal 5-1 has voltage ■□
is charged to the 1" level. Here, the voltage V, , is given by the following formula: O ■m = vdd - Δ■, - (vT + δ■T) (3) Here, the voltage V is at terminal 5. -1 is charged to the parasitic capacitance Cc (consisting of the source junction capacitance of the transmission MO8TQ, the drain junction capacitance of the discharge MO8TQd, and the gate capacitance of the charge MO8TQo).

At time t1, charging MO8TQc becomes conductive, and charging MO8TQ
The pulse f1 applied to the drain (4-1) of , after the delay time tdc due to charging IVLO8TQc (time t2
) appears in source 7. The -1'' level voltage ■ appearing at the source 7 is also transmitted to the terminal 5-1 through the capacitor CB, increasing the -voltage at the terminal 5-1 by ΔvF. Here, Δ■1 is given by the following equation.

As a result, at 9 hours t2, terminal 5-1 (i.e. charging M
The gate voltage of O8TQc) is the voltage given by the following formula, etc.
rise to

v : v + ΔV, (5) F m If the capacitance CB is designed to be sufficiently large with respect to the parasitic capacitance C6, the voltage ■ is equal to the 'IIW voltage ■4 of the pulse f1. −Δ■.

As a result, charging MO8TQ can be made higher.
Since the gate voltage of c is higher than the train voltage, charging MO8, TQ, , must operate in the non-saturation region.
Voltage obtained at terminal 7 ■. ■4. −Δ■, is equal to. Here, in order to increase the voltage amplitude of the field pulse F obtained at the output terminal 5-1 above Vdd, ld, (
31. The capacitances CB and C are set so that the equation (4) satisfies the following equation.
What is necessary is to determine the value of o.

〉■4. ... (6) From equation (6), here, Vdd = 9V, ■ = 1■, δ = 1■, Δv
, = 2v (in the case of N=1 in equation (1)), then from equation (7) it is sufficient that CB is 15 times or more as large as Cc. The value of parasitic capacitance Cc is transmission MO8TQ, .
Although it depends on the conductance of charging MO8TQ and discharging MO3TQd, it is generally from 0.1 pF to 19 F at most, so the capacitance CB (02 to 1.5 pF) can be easily manufactured on the substrate where the image sensor is integrated. can. time t
At 3, the pulse f decreases from -1'' to °0'' level, and the -1'' level of pulse F1 decreases from V to ■, and then the delay time t due to discharge MO3TQ, .
At time t4 after ddI, the voltage V, . . . decreases to the "0" level (eg, ground voltage) through the discharge MO8, TQ, . At this time, at the same time, the 1” level of terminal 7 (■.=:V
d, −, (V, ) time t, discharge M
It drops to the "0" level through O8TQdc. By a similar operation, a '1'' level pulse F is generated at time t5.

In the above embodiment, the gate of the transmission MO8TQ is opened and closed by the pulse f, but the start pulse ■, which has the same frequency as the field pulse and is applied to the first stage of the vertical scanning circuit,
(■) is a pulse that is the source of the scanning pulse output from each stage of the vertical scanning circuit. On the other hand, the discharge MO
8TQ, c.

The gate Qdl is opened and closed by the pulse f2 as in the previous embodiment. An operation time chart in this case is shown in FIG.

The high voltage output field pulses F, , F2 obtained by the voltage boosting circuit of FIG.
c. At the time of falling, the output becomes uneven for a period tddt.

Furthermore, in the case of FIG. 4, the output is uneven only at the falling edge.

Here, the period tdc ” dat is charging MO8TQc,
Although it depends on the value of the conductance of the discharge M O, S T Q, , it can be designed to be about 100 n5ec to 1 μsec at most, so this period is called the vertical retrace period (a period that is not related to the video signal and is generally 250μse
If it is within the range c), even if these irregularities exist, they will not interfere with the imaging signal at all.

In the embodiments shown in Figures 3 and 4, we considered generating two-phase field pulses within the image sensor, but it is also possible to supply one-phase field pulses from the outside and generate other-phase field pulses from this. The case is shown in FIG. 3/
is the input terminal of the field pulse (e.g. Fl),
Since this already has a high voltage, it is used as is as a pulse to drive the increase circuit. The output terminal of field pulse F1 is indicated by 5'-1. 8 is an inverting circuit (for example) that inverts the polarity of the pulse F1.

It is sufficient to use an l'tlLO8Ii inverting circuit configured by series connection of a load M, O8T and a drive M-08T). "1" of the inverted pulse obtained at the output 4' of this circuit
As mentioned above, since the level causes a voltage drop (Va + δVT) (however, when the polarity inverting circuit is one stage), a high voltage can be applied to the output 5-2 by passing it through the voltage increasing circuit 2-2. field pulse F2 can be obtained.

As mentioned above, the voltage increase circuit is a MOS that manufactures the image sensor.
-It can be manufactured using LSI technology and the circuit itself is simple, so the area occupied by this circuit when integrated is 500 x 500.
This is negligibly small compared to the array area of photoelectric conversion elements, and does not lead to an increase in chip size. Further, as the power supply (such as the above-mentioned Vdd) required to drive this circuit, the power supply added to drive the image sensor body can be used, and no special power supply is required. Furthermore, the frequency of the field pulse is 6.0 Hz, and the horizontal scanning circuit (5
In the case of 00 pixels, it is 1/1 compared to 10 ML(y, )
05, and even if the pulse rise and fall times are high speed, a few microseconds is sufficient (this is several hundred times longer than the rise and fall times of the horizontal clock pulse). Therefore, the configuration 1'vlO8TQF,Q. ,
Qd, , Q,. The conductance of the circuit can be designed to be extremely small, and the power consumed by this circuit is negligibly small compared to the power consumption of the image sensor itself.Although the above explanation has been based on the M'O8T, It is conceivable to use other junction field effect transistors or ordinary bipolar transistors without departing from the spirit of the present invention.

〔Effect of the invention〕

As described above in detail, in the image pickup device of the present invention, a field pulse with a high voltage imaging width can be obtained by integrating a field pulse voltage increase circuit in a part of the periphery of the device chip. As a result, it is now possible to apply a high voltage to the switch for selecting the photoelectric conversion element, expanding the dynamic range (range of incident light amount) of the photoelectric conversion element, reducing the conduction resistance of the switch, etc. It has become possible to provide the necessary performance as a field pulse for an image sensor. Therefore, it is now possible to generate field pulses inside the device, which were previously virtually impossible to generate within the device.
It has become possible to greatly improve the performance of image sensors, including improved reliability.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing an embodiment of a field pulse generation circuit constituting the solid-state image sensor of the present invention, FIG. 2 is a Quimchard diagram explaining the operation of the circuit in FIG. 1, and FIG. The figure shows the configuration and time chart of an embodiment of the voltage increase circuit required in the field pulse generation circuit of the present invention, and FIG. 4 shows the voltage increase circuit in FIG. 3 driven by a different type of pulse from the rough yield pulse. FIG. 5 is a time chart diagram illustrating the operation in this case, and FIG. 5 is a diagram showing an embodiment of a field pulse generation circuit different from that in FIG. 1. 1...Field pulse generation circuit, 2-1゜2-2・
...Voltage increase circuit, 3...Basic pulse input terminal. % 1 (2) Corpse Z[a ヂ2゜---t7ffi! 2------------
1－－－－－－－－－－－￥13 mouth

Claims (1)

[Claims] 1. In a solid-state image sensor equipped with a means for photoelectric conversion, a means for scanning or transferring signal charges generated by the photoelectric conversion, and a means for performing increment scanning on the same semiconductor substrate, driving the increment means 1. A solid-state image pickup device, characterized in that a pulse generation circuit including a voltage increase circuit is integrated on the same substrate as the solid-state image pickup device.