JPS60137111A - Amplitude limiting circuit - Google Patents

Abstract

PURPOSE:To enhance noise suppression effect by connecting the common emitter connection point of a pair of an NPN and a PNP transistor (TR) to the output load part of a differential amplifier circuit in common, and feeding its output back negatively. CONSTITUTION:A pair of emitters of NPNTRQ18 and PNPTRQ19 are connected to the high impedance point of the output of the negative feedback type differential amplifier consisting of TRs Q11-Q17 and resistances R11-R14, and R16, and the base of the TRQ11 as the in-phase input of the differential amplifier and the base of TRQ17 as the opposite-phase input are biased to V1. The collectors of the pair of TRQ18 and TRQ19 are both connected to the base of the TRQ17, and when the amplitude of the output attains to an amplitude limitation level and the pair of TRs Q18 and Q19 conduct, a feedback current flows to each collector.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an amplitude limiting circuit, and particularly to an amplitude limiting circuit that has high performance, excellent amplitude limiting properties, and is suitable for integration.

Conventional configurations and their problems For example, in video signal recording and reproducing devices that use recording media such as magnetic tape, the signal-to-noise ratio (hereinafter referred to as S/N ratio) of the reproduced signal is worse than that of the recorded signal. Therefore, it is necessary to suppress the noise and improve the S/N ratio before sending the reproduced signal to the television receiver. Such a noise suppression device employs a system as shown in FIG. In FIG. 1, 1 indicates a high-pass filter (H, P, F), 2 indicates an amplitude limiting circuit (LIM), and 3 indicates a low-pass filter (L, P, F). FIG. 2 shows waveforms at various parts of the block diagram shown in FIG. 1.

The FM demodulated playback video signal A shown in FIG.
As shown in the figure, the signal is supplied to H, P, and F1, and a signal containing a noise component and a high frequency component of the reproduced video signal as shown at the beginning of FIG. 2 is obtained. The signal port should further amplify only the energy of the noise component (L), which is supplied to IM2 to obtain the amplified inverted signal C. Signal C has its noise extraction band limited by LPF 3, and is mixed with signal A at an appropriate ratio. , 5 obtains a reproduced video signal 2 from which noise components have been removed.
The amplitude limiting circuit (LIv1) 1 at 1H'lB uses a circuit as shown in FIG. 3, and the operation of the amplitude limiting circuit in this case will be described in detail below with reference to FIG. Third
In the figure, Q1 to Q8 are transistors, R1 to R8 are resistors,
D1 to D4 are diodes, ■, ~. Current source, 1 to 01
-It is co7denza.

1, ]・Signal v input to transistor Q8 base
ln is the resistor R6 from the emitter and lid of the same transistor Q8.
The signal is input to a negative feedback differential amplifier formed by transistors 03 to Q6 and resistor R4. The output signal is output from the collector of transistor Q6 via the emitter follower of transistor Q7, and is also output from the collector of transistor Q6.
6 and is negatively fed back to the base of transistor Q6.

In this case, the input signal level is vln, and the output signal level is υ
. ut, and the gain of the differential amplifier composed of transistors Q3 to Q6 and resistor R4 is A. , the AC signal levels at the bases of transistors Q4 and Q6 are set to v4. If it is v6, Z'out ”
80 (Z'4 Z'6) -=--(2) holds true. Here, the diode D1, the resistors R1 to R2°R8, the transistors 01 to Q2. Q8 constitutes a bias circuit and a differential amplifier circuit cover sofa, and since the emitter of the transistor Q2 is a direct current, it becomes v4-Q. Also, considering that the gain of the differential amplifier is ideally infinite, (1)
Equations and (2) hold true. Therefore, a phase-inverted signal with a gain of R5/R6 is obtained at the output.

Also, the output signal is connected to the diode D3. Maximum V by D4
The amplitude is controlled to D (VD is the voltage between the anode and cathode when the diode is conductive). The operating point at the base of the transistor Q7 is "-Cc-2VD," and the anode of the diode D3 and the anode of the diode D4 are V. . Since it is biased at -2VD, the potential of the base of resistor Q7 is ■. o-V
D or above, and ■. If the voltage goes below 0-3VD, the diode D3 and the diode D4 become conductive and the potential becomes constant.

Furthermore, in this amplitude limiting circuit, For Rikijin-go, it operates as a simple differential amplifier circuit.

That is, by amplifying only the noise components contained in the reproduced video signal and applying it to the high frequency components of the reproduced video signal, the amplitude is limited and the efficiency of noise extraction is improved. In this case, after the high frequency components H, P, and Fl of the reproduced video signal have passed, a differential response as shown in the dotted line in Fig. 2E is shown, but during the period tLIM during which the differential response signal exceeds vD. The signal is clipped and the noise cannot be extracted. Therefore, when such a noise component and a clipped differential response signal are superimposed on the original reproduced video signal, the noise is not suppressed for a period of tLIlvi and the endogenous video signal is The loss of energy causes the dog to become angry. When such a reproduced video signal is displayed on a television receiver, there is a hazy residual noise at the edges of areas with strong contrast, and the ringing of the image becomes soft, making it visually unnatural. This will cause inconvenience.

OBJECTS OF THE INVENTION The present invention provides an amplitude limiting circuit that eliminates the problems that occurred when using the above-mentioned amplitude limiting circuit and has a large noise suppression effect.

Structure of the Invention To summarize, the present invention provides a common collector connection and a common emitter 1. to one signal input section of a differential amplifier circuit. connection,
The common collector connection point of NPN and P44P bare transistors each having their bases held at a predetermined reference voltage is connected to the common emitter connection point of the pair of transistors, and the common emitter connection point of the paired transistors is connected to the common emitter connection point of the differential amplifier circuit. This is an amplitude limiting circuit that is commonly connected to the output load section and has a configuration that provides negative feedback to the output from the differential amplifier circuit. When conductive, the conduction current is returned to the input, and the waveform of the differential response signal is amplitude limited without being distorted.

DESCRIPTION OF EMBODIMENTS FIG. 4 shows an embodiment of the present invention. In this embodiment, transistors Q11 to Q17. At the high impedance point of the output of the negative feedback differential amplifier constituted by the resistors R11 to R14 and Rle, that is, at the base of the transistor Q16, there is an N
PN) transistor Q18 and PNP transistor Q19
The Q11 base, which is a positive phase input, and the Q1□ base, which is a negative phase input, of the differential amplifier are biased to ■1 through R11 and R1□, respectively. Therefore, the DC level of the output is set to 1 in terms of the circuit format.The base potentials of the transistors 018 and Q19 are set to 20 VD>113-vD. Also, pair transistor Q18. Q
The collectors of transistors Q18+019 are both connected to the base of transistor Q1□, so that when the amplitude of the output reaches the amplitude limit level and the pair of transistors Q18 + 019 becomes conductive, a feedback current flows from the respective collectors to the input. The base of the twisted transistor Q16 and the transistor Q
A resistor R16 is inserted between the base of 1□ to stabilize the DC level of the output as a double feedback differential amplifier. Based on the present embodiment shown in FIG. 4, the operation will be described in detail below.

A negative feedback differential amplifier consisting of transistors Q11 to Q1□, resistors R11 to R15, and R1□ has a third
It is similar to the conventional negative feedback differential amplifier shown in the figure, but
Since the double feedback resistor R16 is inserted in this embodiment, the gain of the negative feedback differential amplifier shown in this embodiment is as follows, assuming that the gain without feedback is infinite.

(1Q Xiju Sanji+"16)-Hyakusun-"-R16R15 Under such gain settings, the input signal Z'in is υ.

= vlnG and the instantaneous value of the output signal 1v01ka v1+1vo1<■2+VD, v1-1001>■3-
When VD is satisfied, the paired transistor Q18. Q19 is a cutoff, and this embodiment shown in FIG.
If so, transistor Q19 turns on and ■1-1v
01〈■3-VD, the transistor Q18 turns on, and thus the paired transistor Q18. Q19
The output signal v0 is amplitude limited by the base-emitter voltage.

Now, as in the explanation of the conventional example of FIG. 3, a signal containing a noise component and a high frequency component of the reproduced video signal as shown enlarged in FIG. It is assumed that the signal is input to the base of the transistor Q1□ in this embodiment shown in the figure. To explain the output signal waveform in this case, as shown in Figure 5, for example, the differential response signal is
When the level of VD is reached, transistor 018 is turned on, and a conduction current flows from the collector of transistor Q19 to the input capacitor. The conduction current Ic18 in this case is expressed as: This current discharges the charge in the capacitor C1, and draws current from the voltage source 1 through the resistor R1□ to lower the input signal level. When the differential response signal reaches the level of 2+VD, the transistor Q19 is turned on, and a conduction current flows from the collector of the transistor Q19 to the input. The conduction current in this case is also expressed as in equation (6), and this current charges the capacitor C1, and causes the current to flow from ■1 through the resistor R1□ to raise the input signal level. Therefore, when the output signal level reaches the amplitude limit level, negative feedback is instantaneously applied to the input signal level, which continues only during the period when Q18 or Q19 is conductive, so that the output signal also attempts to return to its original level.

As a result, the amplitude of the differential response signal can be limited without clipping the tip of the waveform.

Therefore, as shown in Figure 5, it is possible to extract noise components from the reproduced video signal even during the transition period of the differential response, so the period tLIM during which noise extraction is impossible, as shown in Figure 2, It can be done without being present.

As described above, in this embodiment, in order to limit the amplitude without clipping the leading end of the differential response signal, when the signal shown in FIG. 5 oiC is superimposed on the reproduced video signal, Noise suppression becomes iJ function even in parts where signal level changes are large, and therefore,
As shown in FIG. 5C, the energy loss of the reproduced video signal is also reduced.

Effects of the Invention As described in detail above, if the amplitude limiting circuit of the present invention is used in a noise suppression device, for example, noise extraction can be effectively reduced by 1j, and the output of the noise suppression device can be Energy loss of the reproduced video signal can be reduced. As a result, the image displayed on the television receiver does not have hazy noise at the edges of areas with strong contrast, and the unnaturalness at the edges, as explained in the problem with the conventional example, is also eliminated. be able to.

[Brief explanation of the drawing]

Figure 1 shows an example of a noise suppression device. Figure 2 is a timing chart for explaining the operation of the noise suppression device, Figure 3 is a circuit diagram of a conventional amplitude limiting circuit, and Figure 4 is an amplitude limiting circuit of an embodiment of the present invention. The circuit diagrams of FIGS. 5A to 5C are diagrams showing the effects of the amplitude limiting circuit according to the embodiment of the present invention. 1... High pass filter (H, P, F), 2...
...Amplitude limiting circuit (LIM), 3...Low pass filter (L, P, F), Q11 to Q19...
...Transistor, R11-R18...Resistor, C1...Capacitor. Name of agent Patent attorney Toshi Nakao Male 11 or 1 Figure 1 Figure 2 No. / Figure 3 Figure 5 Figure 1 Display of the case 1982 Patent application No. 250426 Bow 2 Name of the invention Amplitude limiting circuit 3 Relationship with the case of the person making the amendment Patent application Person name Address 1006 Kadoma, Kadoma City, Osaka Prefecture Name (
582) Matsushita Electric Industrial Co., Ltd. Representative Toshihiko Yamashita 4 Agent 571 Address 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd., Yachi. Figure 2 Figure 5

Claims (2)

[Claims] (1) The common collector connection of a pair of NPN and PNP transistors, which have a common collector connection and a common emitter connection, and whose respective bases are held at a predetermined reference potential, is connected to one signal input section of the differential amplifier circuit. the common emitter and two-mega connection points of the paired transistors are commonly connected to the output load section of the differential amplifier circuit;
An amplitude limiting circuit that is configured to provide negative feedback to the output from the differential amplifier circuit. (2) The amplitude limiting circuit according to claim 1, wherein the negative feedback is directly coupled to the signal input section from a common emitter connection point of a pair of NPN and PNP transistors via a resistor.