JPS60136986A - Information storage circuit - Google Patents

Abstract

PURPOSE:To decrease the current consumption by constituting the titled circuit with a unit storage circuit group having plural input terminals, a selection circuit selecting a required signal out of the output signal and a control circuit section to control a write signal. CONSTITUTION:A storage circuit 21 makes read operation at the 1st half of a time slot TS and write operation at the latter half. A selection circuit 23 outputs selectively the input terminal 1, information of the time slot T9 of O4-O7 is obtained at the output and stored once in a storage circuit 24 at the falling of a write control signal WE. Moreover, the output of the storage circuit 24 is inputted to a selection circuit 25 and controlled by a decorder circuit 26. The information of the time slot T9 of the output signal O6 is replaced with input data information, and the information stored in the storage circuit 21 is obtained as it is as the information of the time slot T9 of other output signals O4, O5 and O7.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention is applied to, for example, a time division multiplex communication device,
The present invention relates to an information storage circuit for controlling a plurality of output alcoholic drinks consisting of a plurality of time slots using address information.

In the prior art, as shown in FIG.
Address information (Fig. 2(a) (5AD
)) and address information indicating the time slot position (
In the case of controlling according to FIG. 2 [b) (TAD)). A conventional information storage circuit has a configuration shown in FIG.

In FIG. 3, one unit storage circuit 11 is prepared corresponding to one output signal, and address information representing the time slot position (FIG. 2(b)) is given to the terminal 2, and the unit storage circuit 1. 1 address signal. On the other hand, based on the address information (FIG. 2(a)) for specifying the output signals that are input multiple times to the terminal l, the control circuit 12
A signal for information writing given to (Fig. 2 (dl(W
E) is distributed to the corresponding unit storage circuits 11. As a result, the information input to terminal 3 (Fig. 2(c) (D
ATA)) is stored in each corresponding unit memory circuit 11, and by reading these unit memory circuits 11 simultaneously, the desired output signal shown in FIG. 1 can be obtained.

Such a conventional configuration has the disadvantage that a unit storage circuit is required in proportion to the increase in the number of output signals t, resulting in an increase in the size of the p1 circuit and an increase in current consumption.

C.3 Objectives of the Invention An object of the present invention is to provide an information storage circuit in which the drawbacks of the conventional storage circuits described above are avoided by using a unit storage circuit having a plurality of input terminals.

D1 Configuration of the Invention The information storage circuit of the present invention includes a unit storage circuit group having a plurality of input terminals, a selection circuit for selecting a necessary signal from among the output signals thereof, and a holding circuit for holding the output of the selection circuit. an information storage circuit comprising: a selection circuit for selecting input data information and the holding circuit output; and a control circuit section for controlling a control signal of the selection circuit and a write signal of the unit storage circuit group. It is.

E, Example Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit block diagram showing an example in which the number of output signals is 16 (00 to 015). As individual memory circuits, four unit memory circuits 21 having four input/output common terminals are used, and a three-state buffer circuit 22 is provided to avoid signal collision during output operation. 1
The address information 0AD shown in FIG. 2 fal, which specifies six output signals, is a 4-bit binary signal "ooo
o~1111'', and input the upper two bits to terminal 5 and the lower two bits to terminal 6. On the other hand, the address information TAD representing the time slot position shown in FIG. It is input to the terminal 7 as address No. 16 of the memory circuit 21. Also, to the terminal 8, the address shown in FIG.
The write control signal WE shown in FIG. 2 fdl is input to the input data information terminal 9 shown in FIG. The operation in this case will be explained below with respect to the time slot TS in FIG.

The storage circuit 21 performs a read operation in the first half of the time slot TS, and performs a write operation in the second half. At this time, in the first half of the time slot T8, each memory circuit 21 outputs the information of the time slot T9 of each output signal (00 to 015). On the other hand, in Figure 2 (OAD of al represents 06
110", the top two bits) "01"' causes the selection circuit 23 to select and output all input terminals l. As a result, the selection circuit 23 outputs the time slots T9 from 64 to 67.
This information is temporarily held in the holding circuit 24 at the fall of the write control signal WE. Furthermore, this holding circuit 24
The output of is inputted to the 2-1 selection circuit 25 to which the input data information shown in FIG. 2 (cl) is connected to the other end. It is controlled by a decoder circuit 26. As a result, 2-
At the output of the 1 selection circuit 25, the information in the time slot T9 of the output signal O6 is replaced with the input data information, and the information in the time slot T9 of the other output signals 04, 05°07 is replaced with the input data information.
The information stored in the storage circuit 21 can be obtained as is. On the other hand, the WE signal shown in FIG. 2 +d+ is OA
It is applied to the corresponding storage circuit 21 by the distribution circuit 27 which receives the upper two bits "01" of D as input. time slot)
At T8, the write signal WE is applied to the memory circuit 21 that accommodates the output signals 04 to 07, and only the information in the time slot T9 of the output signal 06 is newly converted to input data information, and the output signals 04, 05, 07, As for the time slot T9 information, the information stored in the storage circuit 21 is written again.

0 Effects of the Invention As is clear from the above explanation, information stored in a memory circuit having a plurality of input terminals is read out in advance, one of the information is updated, and the other information is read again as it was. The writing method allows multiple output signals to be stored in one memory circuit. As a result, current consumption, which is a drawback of the conventional type, can be reduced, and the circuit scale can be dramatically improved even when the number of output signals is increased.

[Brief explanation of the drawing]

Fig. 1 is a timing diagram showing the output signal form, Fig. 2 is a timing diagram showing the input signal form, Fig. 3 is a circuit block diagram of a conventional information storage circuit, and Fig. 4 is a circuit according to an embodiment of the present invention. It is a block diagram. l~9...Input terminal, 11.21...Group/unit storage circuit, 12...Control circuit, 22/Old...
・3-state buffer circuit, 23.25...Selection circuit, 24...Holding circuit, 26...Decoder circuit, 27...Distribution circuit c>ts 't 1.1 (1, -11, 嘗 blind agony) \ L ', 1 C3 meat () li'+ li (name 3 figure

Claims (1)

[Claims] A unit storage circuit group having a plurality of input terminals, a selection circuit that selects a necessary signal from its output signals, a holding circuit that holds the output of the selection circuit, and a group of unit storage circuits that has a plurality of input terminals, a holding circuit that holds the output of the selection circuit, and a group of unit storage circuits that has a plurality of input terminals. An information storage circuit comprising: a selection circuit for selection; and a control circuit section for controlling a control signal of the selection circuit and a reading signal of the unit storage circuit group.