JPS60136831A - レシデユ−生成回路 - Google Patents

レシデユ−生成回路

Info

Publication number
JPS60136831A
JPS60136831A JP58247392A JP24739283A JPS60136831A JP S60136831 A JPS60136831 A JP S60136831A JP 58247392 A JP58247392 A JP 58247392A JP 24739283 A JP24739283 A JP 24739283A JP S60136831 A JPS60136831 A JP S60136831A
Authority
JP
Japan
Prior art keywords
residue
res
carry
generation circuit
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58247392A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0214727B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Hideo Miyanaga
宮永　秀雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58247392A priority Critical patent/JPS60136831A/ja
Priority to CA000469911A priority patent/CA1232072A/en
Priority to DE8484402615T priority patent/DE3485535D1/de
Priority to EP84402615A priority patent/EP0147296B1/en
Priority to AU36856/84A priority patent/AU550740B2/en
Priority to BR8406677A priority patent/BR8406677A/pt
Priority to US06/685,517 priority patent/US4727507A/en
Priority to KR8408288A priority patent/KR900000477B1/ko
Priority to ES539052A priority patent/ES8602271A1/es
Publication of JPS60136831A publication Critical patent/JPS60136831A/ja
Publication of JPH0214727B2 publication Critical patent/JPH0214727B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
    • G06F7/5275—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products using carry save adders
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
JP58247392A 1983-12-26 1983-12-26 レシデユ−生成回路 Granted JPS60136831A (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP58247392A JPS60136831A (ja) 1983-12-26 1983-12-26 レシデユ−生成回路
CA000469911A CA1232072A (en) 1983-12-26 1984-12-12 Multiplication circuit using a multiplier and a carry propagating adder
DE8484402615T DE3485535D1 (de) 1983-12-26 1984-12-17 Multiplizierschaltung.
EP84402615A EP0147296B1 (en) 1983-12-26 1984-12-17 Multiplication circuit
AU36856/84A AU550740B2 (en) 1983-12-26 1984-12-18 Multiplication circuit
BR8406677A BR8406677A (pt) 1983-12-26 1984-12-21 Circuito de multiplicacao
US06/685,517 US4727507A (en) 1983-12-26 1984-12-24 Multiplication circuit using a multiplier and a carry propagating adder
KR8408288A KR900000477B1 (en) 1983-12-26 1984-12-24 Multification circuits
ES539052A ES8602271A1 (es) 1983-12-26 1984-12-26 Circuito de multiplicacion para multiplicadores de gran velocidad en el sistema de un ordenador

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58247392A JPS60136831A (ja) 1983-12-26 1983-12-26 レシデユ−生成回路

Publications (2)

Publication Number Publication Date
JPS60136831A true JPS60136831A (ja) 1985-07-20
JPH0214727B2 JPH0214727B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-04-09

Family

ID=17162740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58247392A Granted JPS60136831A (ja) 1983-12-26 1983-12-26 レシデユ−生成回路

Country Status (1)

Country Link
JP (1) JPS60136831A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
JPH0214727B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-04-09

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