JPS60136551U - Channel selection device - Google Patents
Channel selection deviceInfo
- Publication number
- JPS60136551U JPS60136551U JP2315784U JP2315784U JPS60136551U JP S60136551 U JPS60136551 U JP S60136551U JP 2315784 U JP2315784 U JP 2315784U JP 2315784 U JP2315784 U JP 2315784U JP S60136551 U JPS60136551 U JP S60136551U
- Authority
- JP
- Japan
- Prior art keywords
- address signal
- section
- memory
- channel number
- signal output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Circuits Of Receivers In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は電子チューナに設けられたバラクタダイオード
の特性説明図、第２図はこの考案の選局装置の１実施例
のブロック図である。
１・・・電子チューナ、２・・・メモリ部、３・・・ア
ドレス信号出力部、４・・・増幅回路、５・・・比較回
路、６・・・チャ・ンネル番号表示部。FIG. 1 is a characteristic diagram of a varactor diode provided in an electronic tuner, and FIG. 2 is a block diagram of an embodiment of the channel selection device of this invention. DESCRIPTION OF SYMBOLS 1...Electronic tuner, 2...Memory section, 3...Address signal output section, 4...Amplification circuit, 5...Comparison circuit, 6...Channel number display section.
Claims (1)
備えた電子チューナと、全受信チャンネルのチャンネル
番号それぞれによりアドレス指定される複数のアナログ
メモリを備え、該各アナログメモリに前記全受信チャン
ネルのチューニング電圧またはチューニング電圧に比例
する電圧が書き込まれたメモリ部と、前記チューナから
チュー斗ング電圧が出力されたときに前記各アナログメ
モリを順次にくり返しアドレス指定するアドレス信号を
前記メモリ部に出力し、前記各アナログメモリの記憶電
圧を前記メモリ部から順次に読み出させるアドレス信号
出力部と、前記メモリ部から読み出された記憶電圧にも
とづ（読出しチューニング電圧が前記チューナから出力
されたチューニング電圧にほぼ一致したときに前記アド
レス信号出力部にアドレス信号の変更停止信号を出力す
る比較部と、前記アドレス信号出力部のアドレス信号の
デコードにより当該アドレス信号にもとづくチャンネル
番号を表示するチャンネル番号表示部とを設けた選局装
置。It comprises an electronic tuner with a presetting function for tuning voltages of receiving channels, and a plurality of analog memories each addressed by the channel number of all receiving channels, each analog memory having a tuning voltage or a tuning voltage for all said receiving channels. A memory section in which a proportional voltage is written, and an address signal for sequentially and repeatedly addressing each analog memory when a tuning voltage is output from the tuner are output to the memory section, and each of the analog memories is an address signal output section that sequentially reads storage voltages from the memory section; and an address signal output section that sequentially reads storage voltages from the memory section; and a comparison section that outputs an address signal change stop signal to the address signal output section, and a channel number display section that decodes the address signal of the address signal output section and displays a channel number based on the address signal. station equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2315784U JPS60136551U (en) | 1984-02-20 | 1984-02-20 | Channel selection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2315784U JPS60136551U (en) | 1984-02-20 | 1984-02-20 | Channel selection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60136551U true JPS60136551U (en) | 1985-09-10 |
Family
ID=30516137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2315784U Pending JPS60136551U (en) | 1984-02-20 | 1984-02-20 | Channel selection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136551U (en) |
-
1984
- 1984-02-20 JP JP2315784U patent/JPS60136551U/en active Pending
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