JPS5830328U

JPS5830328U - Receiving machine

Info

Publication number: JPS5830328U
Application number: JP12401681U
Authority: JP
Inventors: 誠山田; 沓山　弘
Original assignee: 三洋電機株式会社
Priority date: 1981-08-20
Filing date: 1981-08-20
Publication date: 1983-02-28

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の受信機の要部のブロック図、第２図は第
１図の同調指示信号電圧の経時変化説明図、第３図以下
の図面はこの考案の受信機の１実・流側を示し、第３図
は要部のブロック図、第４図は第３図の同調指示信号電
圧の説明図、第５図は第３図の要部の結線図、第６薗は
第５図のメモリ゛セルの動作説明図、第７図は同調指示
信号電圧の偏移による制御電圧の変化説明図、第８図ａ
、　　ｂ。Ｃはリフレッシュ動作説明用のタイミングチャートであ
る。１・・・ディジタルメモリ、２・・・アナログメモリ、
３ｂ・・・加算回路、４・・・リフレッシュメモリ、５
・・・リフレッシュ起動用スイッチ。Fig. 1 is a block diagram of the main parts of a conventional receiver, Fig. 2 is an explanatory diagram of changes over time in the tuning instruction signal voltage of Fig. 1, and Fig. 3 and the following drawings show the actual and flow diagram of the receiver of this invention. Fig. 3 is a block diagram of the main part, Fig. 4 is an explanatory diagram of the tuning instruction signal voltage of Fig. 3, Fig. 5 is a wiring diagram of the main part of Fig. 3, and Fig. 6 is a block diagram of the main part of Fig. 3. Fig. 7 is an explanatory diagram of the operation of the memory cell shown in Fig. 7. Fig. 7 is an explanatory diagram of the change in control voltage due to deviation of the tuning instruction signal voltage.
, b. C is a timing chart for explaining refresh operation. 1...Digital memory, 2...Analog memory,
3b...addition circuit, 4...refresh memory, 5
...Refresh activation switch.

Claims

[Scope of utility model registration request]

A tuning instruction signal is formed by adding a signal stored in a digital memory consisting of a non-volatile memory and a signal stored in an analog memory consisting of a non-volatile memory, and in a receiver that performs reception selection based on the tuning instruction signal, At the same time, a refresh memory stores a storage signal for compensation of variation in the storage signal of the analog memory by a refresh operation, a refresh activation switch of the refresh memory, a storage signal of the digital memory, a storage signal of the analog memory, and and an addition circuit that adds the storage signals of the refresh memory and outputs a tuning instruction signal.