JPS5850733U - Receiving channel selection device - Google Patents
Receiving channel selection deviceInfo
- Publication number
- JPS5850733U JPS5850733U JP13921981U JP13921981U JPS5850733U JP S5850733 U JPS5850733 U JP S5850733U JP 13921981 U JP13921981 U JP 13921981U JP 13921981 U JP13921981 U JP 13921981U JP S5850733 U JPS5850733 U JP S5850733U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- set output
- tuning
- output voltage
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の受信選局装置の一部のブロック図、第２
図はこの考案の受信選局装置の一部のブロック図である
。
１、・・・・・・記憶回路、２・・・・・・第１加算回
路、３ｂ・・・・・・可変抵抗、５・・・・・・検出回
路、６・・・・・・アナログスイッチ回路、７・・・・
・・第２加算回路、８・・・・・・発光ダイオード、Ｍ
５・・・・・・粗調用メモリ、Ｍピ・・・・・微調用メ
モリ。Figure 1 is a block diagram of a part of a conventional receiving channel selection device;
The figure is a block diagram of a part of the receiving channel selection device of this invention. 1... Memory circuit, 2... First addition circuit, 3b... Variable resistor, 5... Detection circuit, 6... Analog switch circuit, 7...
...Second addition circuit, 8...Light emitting diode, M
5...Memory for coarse adjustment, M pi...Memory for fine adjustment.
Claims (1)
調電圧それぞれを記憶する粗調用メモリおよび微調用メ
モリを備えた記憶回路と、前記両メモリの前記粗調電圧
と前記微調電圧とを加算しプリセット選局用同調電圧を
出力する第１加算回路と、手動操作により設定出力電圧
が変化する可変抵抗と、前記設定出力電圧を検出し切換
制御信号を出力するとともに前記設定出力電圧が前記微
調電圧範囲内のときに表示信号を出力する検出回路と、
前記切換制御信号によりスイッチング動作し前記設定出
力電圧が前記微調電圧範囲外のときに前記設定出力電圧
を出力するとともに前記設定出力電圧が前記微調電圧範
囲内のときに前記粗調用メモリの前記粗調電圧および前
記設定出力電圧を出力するアナログスイッチ回路と、該
アナログスイッチ回路を介した前記設定出力電圧および
前記粗調電圧が入力され前記設定出力電圧が前記微調電
圧範囲外のときに前記設定出力電圧にもとづくマニュア
ル選局用同調電圧を出力するとともに゛前記設定出力電
圧が前記微調電圧範囲内のときに前記粗調電圧および前
記設定出力電圧にもとづく手動微調選局用同調電圧を出
力する第２加算回路とを備えた受信選局装置。A storage circuit comprising a coarse adjustment memory and a fine adjustment memory that store a coarse adjustment voltage for each received tuning frequency and a fine adjustment voltage smaller than the coarse adjustment voltage, and a storage circuit that stores the coarse adjustment voltage and the fine adjustment voltage of both the memories. a first adding circuit that adds the preset tuning voltage and outputs a tuning voltage for preset tuning; a variable resistor that changes the set output voltage by manual operation; and a variable resistor that detects the set output voltage and outputs a switching control signal, a detection circuit that outputs a display signal when within the fine adjustment voltage range;
The switching operation is performed by the switching control signal to output the set output voltage when the set output voltage is outside the fine adjustment voltage range, and to output the coarse adjustment of the coarse adjustment memory when the set output voltage is within the fine adjustment voltage range. an analog switch circuit that outputs a voltage and the set output voltage, and an analog switch circuit that outputs the set output voltage and the rough adjustment voltage through the analog switch circuit, and when the set output voltage is outside the fine adjustment voltage range, the set output voltage a second addition that outputs a tuning voltage for manual tuning based on the coarse tuning voltage and the tuning voltage for manual fine tuning based on the set output voltage when the set output voltage is within the fine tuning voltage range; A receiving channel selection device comprising a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13921981U JPS5850733U (en) | 1981-09-19 | 1981-09-19 | Receiving channel selection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13921981U JPS5850733U (en) | 1981-09-19 | 1981-09-19 | Receiving channel selection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5850733U true JPS5850733U (en) | 1983-04-06 |
Family
ID=29932418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13921981U Pending JPS5850733U (en) | 1981-09-19 | 1981-09-19 | Receiving channel selection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850733U (en) |
-
1981
- 1981-09-19 JP JP13921981U patent/JPS5850733U/en active Pending
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