JPS647424U

JPS647424U -

Info

Publication number: JPS647424U
Application number: JP10147787U
Authority: JP
Priority date: 1987-07-01
Filing date: 1987-07-01
Publication date: 1989-01-17

Description

[Brief explanation of the drawing]

第１図は本考案装置の正面パネルの概略図、第
２図は本考案第１実施例を示す回路ブロツク図、
第３図は１実施例の動作フローチヤート、第４図
は従来例を示す回路ブロツク図である。１……制御回路、３……メモリ、４……プリセ
ツトキー、５……指定モードキー。 FIG. 1 is a schematic diagram of the front panel of the device of the present invention, and FIG. 2 is a circuit block diagram showing the first embodiment of the present invention.
FIG. 3 is an operational flowchart of one embodiment, and FIG. 4 is a circuit block diagram showing a conventional example. 1...Control circuit, 3...Memory, 4...Preset key, 5...Specified mode key.

Claims

[Claims for Utility Model Registration] a. A plurality of preset keys, b. A memory including a plurality of memory areas corresponding to each of the plurality of preset keys, and a last memory that does not correspond to any of the plurality of preset keys; c. The above-mentioned. a plurality of memory addresses included in each of the plurality of memory areas and whose storage contents are read/written by operations of the plurality of preset keys; d) a mode for specifying the plurality of memory areas by the plurality of preset keys; mode switching means for switching between a mode in which stored content is read from one of the plurality of memory addresses and a mode in which received data is written in one of the plurality of memory addresses; Last memory control means writes the number of the memory address where data is stored in the thrust memory, reads the data stored in the last memory when the power is turned on, and causes the broadcast station stored in the corresponding memory address to be received; An electronically tuned radio receiver comprising: