JPS6013557B2 - APC voltage and ACC voltage formation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for forming APC and ACC voltages of, for example, a color television receiver.

The APC circuit and ACC circuit shown in FIG. 1 have been considered as an APC circuit and an ACC circuit for a color television receiver.

That is, a color video signal is supplied to a bandpass amplifier 1, a carrier color signal is amplified and extracted, and this carrier color signal is supplied to a color demodulation circuit 2. Also, amplifier 1
The carrier color signal from VC0 is supplied to the burst gate circuit 3 to extract the burst signal Sb, and this signal Sb is supplied to the phase comparator circuit (multiplying circuit) 4.5.
(voltage controlled variable frequency oscillation circuit) 6 to the oscillation signal (continuous wave signal) whose free running frequency is the carrier frequency So is the comparison circuit 4
supplied to Further, the signal So from the VC06 is supplied to the phase shift circuit 7 to be converted into a signal Sp whose phase is shifted by 2, and this signal Sp is supplied to the comparator circuit 5. and,
The output voltages Ec and Ed of the comparison circuits 4 and 5 are supplied to the subtraction circuit 8 to take out the difference voltage Es=Ec-Ed, and this voltage Ec is supplied to the VC06 as its control signal (APC voltage), and the APC circuit 1 1 is constructed.

Further, the fin pressures Ec and Ed from the comparison circuits 4 and 5 are supplied to the adder circuit 9, and the Japanese crab pressure Ew=Ec+Ed is taken out, and this voltage insect w is sent to the amplifier 1 as a gain control signal (AC
C voltage), and the ACC circuit 12 is configured.

Then, the signal So from the VC06 is supplied to the color demodulation circuit 2, and red, green, and blue color difference signals are demodulated from the carrier color signal.

In this case, the phase of the oscillation signal So is 8o (burst signal Sb
(based on the phase of ), the voltage c is as shown in Figure 2A.
changes as shown by the solid line.

Since the signal Sp is phase-shifted by m/2 with respect to the signal So, the voltage d changes as shown by the solid line in FIG. 2A with respect to the phase oo of the signal So. The change characteristics are shifted by bamboo/2 with respect to the change in . Therefore, the differential voltage s
changes as shown by the broken line in FIG. 2A with respect to the phase 8o of the signal So. The phase or frequency of the oscillation signal So is controlled by this voltage Es, and since Es=0 in a steady state, at this time, the signal S
o is locked to the burst signal Sb in oo=3/4. Also, the sum voltage Ew' changes as shown by the pongee line in Figure 2 with respect to the phase oo of the signal So, and the level of the valley point corresponding to oo = 3/4 bamboo is taken out as the voltage Ew. . Then, when the level of the burst signal Sb changes, the levels of the voltages c and Ed change, and the level of the trough of the voltage w changes, so the gain of the amplifier 1 changes, and the output from the amplifier 1 changes. The level of the carrier color signal is kept constant.
On the other hand, if there is an error Δ0 in the phase shift amount of the phase shift circuit 7,
The signal Sp is different from the signal So as shown in FIG. 2B (
/20△0), but in this case as well, Es=
When it is 0, it is when the voltage Ew is at the valley point.

In the steady state, since Es=0 is locked, the voltage Ew' is at the trough level in this steady state. At the valley point of this voltage wave w, even if there is a variation in the phase 8o of the signal So, the level variation of the voltage Ew with respect to the phase variation is minimal.

Therefore, even if there is a phase shift error in the phase shift circuit 7, the phase variation of the signal So hardly appears as a level variation of the voltage Ew, so the phase shift variation does not cause a level variation in the carrier color signal. Thus, in the circuit of Figure 1,
Even if there is a phase shift error of the phase shift circuit 7 or a phase fluctuation of the signal So, it is possible to obtain a carrier color signal with stable bell and phase. This is an attempt to improve or simplify the configuration. An example of this will be explained below.

FIG. 3 shows the circuit of FIG. 1 excluding VC06.

That is, a first double-balanced multiplication circuit (phase comparison circuit) 4 is configured by the transistors Q4, to Q47, and burst signals Sb having opposite phases to each other are transmitted from the burst gate circuit 3 to the transistors Q44 and Q44. Q43
A signal So is supplied between the bases of transistors Q5 and Q. Further, a second double-balanced multiplication circuit 5 is configured by the transistors Q5, -Q7, and the burst signals Sb having mutually opposite phases are transmitted from the burst gate circuit 3 to the transistors Q5, Q54.
and the bases of transistors Q52 and Q53, and the signal Sp from the phase shift circuit 7 is supplied to the bases of transistors Q and Q$.
supplied between the two

An adder circuit 9 consisting of a current mirror circuit is configured by Q92 of the transistor Q.
&． Q44 and Q muscle, the collector of Q54 is resistor R4,
．． It is connected to the base and collector of transistor Q9 through R5.

Therefore, for each burst signal period, transistor Q2. Q
Voltages Ec and Ed are taken out to the collectors of 4, common 2, and common 4, and a sum voltage Ew is taken out from transistor Q92.

At this time, the sum voltage Ew is increased by the capacitor C9.
'The ripple component included in this is removed, and the voltage E
w is held for one horizontal period, and voltage w is a DC voltage (A) whose level changes in accordance with the level of burst signal Sb.
CC voltage).

Also, at this time, transistors Q42, Q44 and Q2
, Q54 are supplied to the bases of the transistors Q, , Q.

This transistor Q, Q82, is a transistor Q83.
The transistor Q3 and the transistors Q84 and Q85 together constitute a margin amplifier 82. And transistor Q2
A capacitor C8 is connected to the collector of
A current mirror circuit 83 consisting of transistors Q6 and Q7 and a resistor R82 is connected, and a transistor Q8
The collector of Q4 is connected to the emitter of transistor Q6. In this way, the subtraction circuit 8 is configured. Further, a switching circuit 1 is constituted by transistors Q, ~Q, and the collector of transistor Q is connected to resistor R,
The burst gate pulse Pf is connected to the base of the transistor Q4 through the terminal T, and the burst gate pulse Pf is supplied to the base of the transistor Q through the terminal T.

Therefore, during the burst signal period, the transistor Q is turned on by the pulse Pf, so the resistors R83 to R8
Transistor Q4 is turned off by the bias of 6,R,
Transistor Q3 is turned on (active region).

Since the transistor Q63 is on, the differential amplifier 81 amplifies the difference between the voltages Ec and Ed from the comparison circuits 4 and 5, and the differential voltage s is taken out to the collector of the transistor Q82. The ripple component is removed by the capacitor C8, held for one horizontal period, and further taken out through the current mirror circuit 83. On the other hand, during the non-burst signal period, the transistor Q is turned off by the pulse Pf, so the transistor Q
4 is on, transistor Q3 is off, and therefore transistors Q, , Q82, and Q86 are off. Therefore, voltage ES of capacitor Cm is taken out through transistor Q7. Then, this voltage Es is V in FIG.
It is supplied to C06 as its control voltage (APC voltage).

That is, a differential amplifier 61 is constituted by the transistors Q6, Q, and Q8, and a coil L6 for AC load and a capacitor C6 for phase shift and free-running frequency adjustment are connected to the collector of the transistor Q. be done. Further, a differential amplifier 62 is constituted by the transistors Q3, 4, and the resistor, and transistors Q5 and Q6 constituting a current mirror circuit 63 are connected to the outside of these transistors. Then, the collector of the transistor Q3 is connected to the base of the transistor Q mother, Q6, and
It is connected through a capacitor C62 to the collector of a transistor Q6, and this collector is connected through a crystal resonator to the bases of transistors Q64 and Q62. Furthermore, the collector of transistor Q5 is
It is connected to the emitter of the skin Q2, and the bases of the transistor Q62 and trench 4 are connected to the base of the emitter follower transistor Q7. Therefore, when an alternating current component is supplied to the base of the transistor Q2, it is differentially amplified by the amplifier 61, and is transmitted from the collector of the transistor Q to the resonator x 6.
, to the base of the transistor Q62, the amplifier 61 operates as an oscillation circuit, and the oscillation signal So is taken out by the transistor Q7.

In this case, if the current flowing to the side of the capacitor C is 12, the collector current of the transistor Q8 is L, and the current flowing to the resistor & is 1, then the collector of the transistor Q is 12 (1 + 13/1 , ) flows.

Therefore, the amplifiers 61 and 62 output the signal currents (118/
The current will be doubled by 1,), and equivalently the capacitance of capacitor C will be multiplied by (113/1,). and,
At this time, the electrical connection 08 is constant, and the collector current 18 is
Since it changes in response to the differential voltage Es, the amplifiers 61 and 62
The equivalent capacitance of will change in response to the voltage Es, and will act as a variable reactance.

Since this variable reactance is connected to the resonator, the oscillation signal So from the transistor Q67 is
The frequency of will change corresponding to the voltage Es.

That is, circuit 6 operates as a VCO. As described above, in the circuits of FIGS. 3 and 4, the APC voltage and A
CC voltages are available at the same time, in which case, according to the present invention, transistors Q82, Q
8 is turned off, the voltage Es charged on the capacitor C is not discharged, and the value of the resistor Ra is equivalently increased, so that the gain of the APC circuit can be increased.

Further, even if the value of the resistor R8 is made small, its equivalent resistance is large, which facilitates the distribution of the DC operating voltage and facilitates IC implementation.

Furthermore, the circuit configuration is simple and does not require any special configuration. In addition, since the voltages Ec and Ed are subtracted by the differential amplifier 81 and then held by the capacitor C, only one capacitor is required and the number of external pins for the capacitor is reduced. It becomes easier to

[Brief explanation of drawings]

FIG. 1 is a system diagram for explaining this invention, FIG. 2 is a diagram for explaining its operation, and FIGS. 3 and 4 are connection diagrams of an example of this invention. 1 is a bandpass amplifier, and 2 is a color demodulation circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. Each output terminal of the first and second multiplier circuits configured in a double-balanced type is connected to a common load through the first and second load resistors, and the first and second multiplier circuits are Each output terminal of is connected to each base of a pair of transistors constituting a differential amplifier, and a capacitor is connected to the collector of one of the pair of transistors.
A first switching element is connected in series with the power supply,
A second switching element is connected to the differential amplifier,
A burst signal is supplied to one input terminal of each of the first and second multiplication circuits, a continuous wave signal is supplied to the other input terminal of the first multiplication circuit, and a continuous wave signal is supplied to the other input terminal of the first multiplication circuit. A phase-shifted signal of the continuous wave signal is supplied to the other input terminal, a burst gate pulse is supplied to the first and second switching elements, and the first switching element is turned on during the burst signal period. At the same time, the pair of transistors is activated by the second switching element, and the first switching element is turned off during the non-burst signal period, and one of the pair of transistors is also turned off. An ACC voltage of a level corresponding to the level of the burst signal is extracted from the common load, and an ACC voltage of a level corresponding to the phase difference between the burst signal and the continuous wave signal is extracted from the capacitor.
APC voltage and AC from which PC voltage is extracted
C voltage formation circuit.