JPS6013556B2 - APC voltage and ACC voltage formation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for forming APC and ACC voltages of, for example, a color television receiver.

The APC circuit and ACC circuit shown in FIG. 1 have been considered as an APC circuit and an ACC circuit for a color television receiver.

That is, a color video signal is supplied to a bandpass assump 1, a carrier color signal is amplified and taken out, and this carrier color signal is supplied to a color demodulation circuit 2. Further, the carrier color signal from the amplifier 1 is supplied to the burst gate circuit 3 to extract the burst signal Sb, and this signal Sb is supplied to the phase comparator circuits (multiplying circuits) 4 and 5.
An oscillation signal (continuous wave signal) So whose free running frequency is a carrier frequency is supplied from a voltage controlled variable frequency oscillation circuit (voltage controlled variable frequency oscillation circuit) 6 to a comparator circuit 4 . Further, the signal So from the VC06 is supplied to the phase shift circuit 7 and is converted into a signal Sp whose phase is shifted by half.
This signal Sp is supplied to the comparator circuit 5. Then, the output voltages Ec and Ed of the comparison circuits 4 and 5 are supplied to the subtraction circuit 8, and the difference voltage Es=Ec-Ed is taken out, and this voltage E
s is supplied to VC06 as its control signal (APC voltage), and the APC circuit 11 is configured.

Further, the voltages Ec and Ed from the comparator circuits 4 and 5 are supplied to the adder circuit 9 and a sum voltage Ew=Ec+Ed is taken out, and this voltage Ew is sent to the amplifier 1 as a gain control signal (AC
C voltage), and the ACC circuit 12 is configured.

Then, the signal So from the VC06 is supplied to the color demodulation circuit 2, and red, green, and blue color difference signals are demodulated from the carrier color signal.

In this case, the phase of the oscillation signal So is 8o (burst signal Sb
(based on the phase of ), the voltage c is as shown in Figure 2A.
changes as shown by the solid line.

Since the signal Sp is phase-shifted by 1/2 with respect to the signal So, the voltage d changes as shown by the solid line in FIG. The change characteristic deviates by 0/2 with respect to the change in . Therefore, the differential voltage s
changes as shown by the broken line in FIG. 2A with respect to the phase oo of the signal So. The phase or frequency of the oscillation signal So is controlled by this voltage Es, and since Es=0 in a steady state, at this time, the signal S
o is locked to the burst signal Sb at oo=3/4. Further, the sum voltage Ew changes as shown by the line in FIG. 2 with respect to the phase oo of the signal So, and the level of the trough corresponding to oo=3'4m is taken out as the voltage Ew.
Then, when the level of the burst signal Sb changes, the levels of the voltages c and Ed change, and the level of the trough of the voltage Ew also changes, so the gain of the amplifier 1 changes,
The level of the carrier color signal from amplifier 1 is kept constant. On the other hand, if there is an error △8 in the phase shift amount of the phase shift circuit 7, the signal So will have a phase of (T/20△0) with respect to the signal So, as shown in FIG. 2B. , also in this case, Es=0
When , the voltage Ew is at the valley point.

In the steady state, the voltage Ew is locked at the state of Es=0, so in this steady state, the voltage Ew is at the trough level. At the valley point of this voltage 9W, the signal S
Even if there is a variation in the phase oo of o, the level variation of the voltage Ew with respect to the phase variation is minimal.

Therefore, even if there is a phase shift error in the phase shift circuit 7, the phase variation of the signal So hardly appears as a level variation of the voltage Ew, so that the phase shift variation does not cause a level variation in the carrier color signal. Thus, in the circuit of Figure 1,
Even if there is a phase shift error of the phase shift circuit 7 or a phase fluctuation of the signal So, it is possible to obtain a carrier color signal with stable bell and phase. This is an attempt to improve or simplify the configuration.An example of this will be explained below.

Figure 3 shows VC06 and subtraction circuit 8 of the circuit in Figure 1.
Shows the circuit excluding.

That is, a first double-balanced multiplier circuit (phase comparator circuit) 4 is configured by the transistors Q4, to Q47, and carrier color signals having mutually opposite phases are transmitted from the amplifier 1 to the transistors Q1, Q1 and Q43. At the same time, a signal So is supplied between the bases of transistors Q5 and Q. Further, a second double-balanced multiplier circuit 5 is configured by transistors Q5 and g7,
Carrier color signals having mutually opposite phases are supplied from the amplifier 1 to the bases of the transistors Q5, Q1 and Q53, and a signal Sp is supplied from the phase shift circuit 7 to the transistors Q5, Q53.
It is supplied between the bases of Buddha 8.

An adder circuit 9 consisting of a current mirror circuit is constituted by the transistors Q and Q92, and the transistor Q
The collectors of the peaks, Q43, Q5, and Q3 are transistors Q.
, is connected to the base and collector of the .

In addition, the collectors of transistors Q2 and Q44 are connected to the emitter of transistor Q of the emitter follower through resistor R4, and the collectors of transistors Q52 and Q44 are connected to the emitter of transistor Q of the emitter follower.
The collector of transistor Q4 is connected to the emitter of the emitter follower transistor Q through a resistor R5.

These transistors Q4 and Q35 are transistors Q~
This constitutes the burst gate circuit 3 together with Q3 and Q36, and the burst gate pulse M is supplied to the terminal T3. Therefore, when pulse M is supplied, transistor Q turns on, transistor Q33 turns off, transistors Q34 and Q5 turn on, and comparator circuits 4 and 5 connect to the power supply terminal through transistors Q4 and Q. T, is connected to.

Furthermore, since the transistor Q2 is turned off when the transistor Q3 is turned on, a constant base bias is supplied to the constant current source transistors Q47 and Q57 due to the transistor Q unevenness. On the other hand, when the pulse Pf is not applied, the transistor Q3 is turned off and the transistor Q3 is turned on, so the transistor Q
4, Q crab is turned off, and comparison circuits 4 and 5 are connected to power terminals T,
be cut off from.

Further, when the transistor Q is turned off, the transistor Q32 is turned on and the transistor Q36 is turned off, so that the transistors Q7- and Q7 are also turned off.
Therefore, since the operating voltage is supplied to the comparison circuits 4 and 5 only during the period of the pulse Pf, that is, during the burst signal period, the phase comparison output Ec between the burst signal Sb and the oscillation signal So is taken out from the comparison circuit 4. A phase comparison output Ed between the burst signal Sb and the phase shift signal Sp is taken out from the comparison circuit 5.

And transistors Q4,, Q43, Q, . Since the output voltages Ec and Ed obtained from the collector of the Q sphere are supplied to the collector of the transistor Q9, the transistor Q
The sum voltage Ew is taken out to the collector of 2. In addition,
At this time, the ripple component included in the sum voltage is removed by the capacitor C9, and the voltage Ew is held for one horizontal period, and the voltage Ew is a DC voltage whose level changes in accordance with the level of the burst signal Sb. (ACC voltage). Also, at this time, transistor Q group, Q
The voltages Ec and Ed obtained at the collectors of transistors Q2 and Q4 are made into similar DC voltages by capacitors C4, C5, and these voltages Ec and Ed are applied to the bases of transistors Q, Q2 shown in FIG. Supplied.

This transistor Q82 constitutes the subtraction circuit 8, and therefore constitutes a differential amplifier together with the constant current source transistor Q83.

Therefore, a differential voltage Es is taken out from the collector of the transistor Q82, and this is caused by the transistor Q which constitutes the current mirror circuit 81 together with the transistor Q85.
4. Further, VC06 is constituted by transistors Q and Q6.

That is, a differential amplifier 61 is constituted by transistors Q2 and Q68, and a coil L for AC load and a capacitor C6 for phase shift and free-running frequency adjustment are connected to the outside of the transistor Q. Ru. In addition, the differential amplifier 6 is connected to the transistors Q3 and Q84 and the resistor R.
2 are constructed, and transistors Q and Q6 constituting a current mirror circuit 63 are connected to their collectors. The collector of transistor Q3 is connected to the base of transistor Q6, and is also connected to the collector of transistor Q6 through a capacitor C62, and this collector is connected to the bases of transistors Q64 and Q62 through a crystal resonance. Ru.

Further, the collector of transistor Q5 is connected to the emitters of transistors Q6, Q2, and transistor Q6 is connected to the emitters of transistors Q6, Q2.
2, the base of Q4 is connected to the base of emitter follower transistor Q7. Therefore, transistor Q2
When the AC component is added to the base of the amplifier 6
Since the amplifier 61 operates as an oscillation circuit, the oscillation signal So is taken out by the transistor Q67.

In this case, the current flowing through the capacitor C62 is 12
, the collector current of the transistor Q is 18, and the resistor R6 is
, a signal current of 12 (118/1,) flows through the collector of the transistor Q.

Therefore, the amplifiers 61 and 62 transmit the signal current 12 (11
6/1,) will double the current, and equivalently the capacitor C
This means that the capacity of 62 is multiplied by (118/1,).
At this time, the current 1 is constant and the collector current 18 changes in response to the differential voltage Es, so the equivalent capacitance of the amplifiers 61 and 62 changes in response to the voltage Es. Acts as a variable IJ factor.

Since this variable reactance is connected to the resonator ~, the oscillation signal So from the transistor Q67
The frequency of will change corresponding to the voltage Es.

That is, circuit 6 operates as a VCO. As described above, in the circuits of FIGS. 3 and 4, the APC voltage and A
CC voltages are available at the same time, in which case, according to the present invention, transistors Q34 and Q
5 is turned off, the charge stored in the capacitor C4,, is not discharged, and therefore the resistor R4,,
Since the value of R5 becomes equivalently larger, the comparator circuits 4 and 5
The gain can be increased.

Furthermore, even if the values of the resistors R4, R5 are made small, their equivalent resistances are large, making it easy to distribute the DC operating voltage and also facilitate IC implementation.

Furthermore, the circuit configuration is simple and does not require any special configuration.

[Brief explanation of drawings]

FIG. 1 is a system diagram for explaining this invention, FIG. 2 is a diagram for explaining its operation, and FIGS. 3 and 4 are connection diagrams of an example of this invention. 11 is a bandpass amplifier, and 2 is a color demodulation circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. One output terminal of each of the first and second multiplier circuits configured in a double-balanced type is connected to a common load, and the other output terminal of each of the first and second multiplier circuits is connected to a common load. the first and second load resistors, and between the first and second load resistors and the power supply, respectively.
and a second switching element are connected in series, and the first
First and second capacitors are connected to the other output terminals of the first and second multiplier circuits, respectively, and a third switching element is connected to each constant current source transistor of the first and second multiplier circuits. A carrier color signal is supplied to one input terminal of each of the first and second multiplier circuits, a continuous wave signal is supplied to the other input terminal of the first multiplier circuit, and a continuous wave signal is supplied to the other input terminal of the first multiplier circuit. A phase-shifted signal of the continuous wave signal is supplied to the other input terminal of the multiplier circuit, and a burst gate pulse is supplied to the first to third switching elements so that the first and second switching elements are switched during the burst signal period. The switching element is turned on, the third switching element is turned off, phase comparison is performed in the first and second multiplier circuits, and the level of the burst signal in the carrier color signal is determined from the load. The ACC voltage at a level corresponding to the burst signal is extracted, and the voltage difference between the voltages obtained at the first and second load resistors changes in level in response to the phase difference between the burst signal and the continuous wave signal. A circuit for forming an APC voltage and an ACC voltage, which are output as an APC voltage.