JPS6013536B2 - Clock pulse synchronization method in triple system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for synchronizing the clock pulses of each system in a triplex system, and in particular, a system that includes an original clock pulse generator having a higher frequency than the basic clock pulse, and turbidizes the original clock pulse. is used as a clock pulse for intersystem synchronization, and by controlling the frequency dividing circuit, a clock pulse (hereinafter simply referred to as a clock) is generated.

) is related to a synchronization method that synchronizes. There are various units of triple system synchronization, from precise ones to rough ones, but the most precise unit is the basic clock unit for the operation pace of each system.

In order to synchronize the triple system in units of basic clocks, the basic clocks themselves must be synchronized. To synchronize the basic clocks, it is necessary to detect synchronization deviations in the basic clocks and to correct them to eliminate the deviations. One method is to have a clock faster than the basic clock (hereinafter referred to as the original clock), and use a frequency-divided version of the original clock as a synchronization clock between systems. By controlling the frequency dividing circuit to synchronize the divided clocks and using the majority vote result of the divided clocks as the basic clock of each system, the basic clock of the triple system can be realized. There is a way to synchronize. In this method, the length of the original clock is equal to the length obtained by dividing one period of the divided clock by the number of frequency divisions, and correction after synchronization deviation is detected can be performed in units of the original clock, so the frequency division ratio is large. This allows for more detailed corrections.

In the conventional triple system clock synchronization method, each system is equipped with a counter to divide the original clock generated by itself.
The frequency-divided clock of each eye system is compared with the majority decision result of the frequency-divided clocks of the three systems, and according to the result, the count value of each counter is controlled so that it is always equal, and the majority decision result is directly used for the operation pace of each part. It is used as the basic clock.

In order to supply a high-frequency basic clock using this method, the original clock of each system must have a high frequency. Therefore, the length of wiring and logic elements that make up the clock synchronization circuit of each system must be adjusted. The problem is the operating speed. That is, in a system in which the majority decision division clock is used as the basic clock, if the frequency of the basic clock is to be set to, for example, MHz, the frequency of the original clock must be set to 24 MHz if the frequency is divided by 8, for example. Therefore, the unit time for correction after the synchronization shift is detected (ie, one cycle of the original clock) is 41.7 m. On the other hand, if there is a difference in wiring length between systems, for example, two systems, the difference in signal propagation delay will be about one plate s, which is a value on the same order as the unit time of correction after synchronization deviation detection. Therefore, even if a synchronization difference between the divided clocks of one system and the other two systems occurs at the same time, the system with the longer interconnection length will detect the synchronization difference sooner, and the shorter system will Detection would be slow between the two, and synchronization could not be achieved properly. It is difficult to supply a stable basic clock with commonly used logic elements, and in order to supply a basic clock with stability that meets the requirements, special logic elements are required, and the wiring length of the majority synchronous circuit is A circuit is required to adjust the propagation delay of the pulse due to the difference between the two clocks, which makes the clock synchronization circuit expensive and has the disadvantage of requiring fine adjustment.

Japanese Patent Application Laid-Open No. 13420/1989 discloses that each system is provided with a counter that divides the frequency of the source clock, and the basic clock is synchronized by controlling the source clock generator based on the phase comparison result of the divided clock pulses. The synchronization method adopted is described, but firstly, the synchronization deviation is gradually adjusted by analog control such as voltage control of the original clock generator, so the response speed to the synchronization deviation is slow, and secondly, Since the basic clock is adjusted by changing the frequency of the original clock generator, devices to which this synchronization method can be applied are:
Processing speeds are limited to those within the possible range of frequency variations of the original clock generator.

In this way, in a synchronization method in which a frequency-divided original clock is used as an inter-system synchronization clock, the present invention performs division based on the result of a comparison between the divided clock of its own system and the divided clock of the third system. By digitally controlling the frequency counter and multiplying the frequency of the majority decision result and using the doubled frequency clock as the basic clock for each system, the response speed to synchronization deviations can be increased and the processing speed can be applied to devices with widely different processing speeds. The purpose is to make it applicable.

Next, embodiments of the present invention will be described with reference to the drawings, together with examples of circuits used to use the method of the present invention.

Each of the systems A, B, and C constituting the triple system has clock synchronization circuits a, b, and c of the same configuration as described later, and each circuit has a clock pulse generation circuit (not shown) provided for each system. The original clock o, which is required to have the same frequency from
Applying cp,, ocp2, ocp3, the clock pulses are synchronized by the same effect, and double frequency clock pulses mCPI'mCP2, mCp of the same frequency are applied.
Outputs 3.

Therefore, here, the clock synchronization circuit a of the first system A will be representatively explained. As shown in FIG. 2, the clock synchronization circuit a has a branch synchronization section a. The frequency division synchronization section includes a presettable frequency division counter 1 that is incremented by applying the original clock ocp of its own system, and a frequency division clock dcp from this counter, etc. Divided clocks dcp2, dcp from similar counters of two systems
The majority circuit 2 which receives 3 and its own frequency divided clock d
cp. The majority clock mtp from the majority circuit 2 is compared with respect to the precedence relationship of the output, and the own system advances, the intermediate system,
It is comprised of a counter control circuit 3 which determines which one is the delay type and controls the counter 1 according to the comparison result.

Further, the doubling cup 22 is formed of one or several chips,
For example, a PLL (Phase Locked Loop) frequency doubler circuit or other publicly available information circuits may be used. In the above structure,
When the frequency division counter 1 is incremented by the application of the original clock ocp and outputs the frequency division clock dcp, and the majority circuit 2 does not output the majority clock mjcp,
In other words, the frequency division of the second and third systems. Tsuku dcp2, dcp3
is not output (the first system in this case is referred to as the leading system), the majority clock mt
The enable signals s,
is erased, and the increment of counter 1 is stopped. On the other hand, if the majority circuit 2 outputs the majority clock mtp at the same time as the divided clock dcp,
If either the second or third system outputs a frequency-divided clock before the first system outputs a frequency-divided clock (the first system in this case is referred to as an intermediate system).

), the input of the enable signal s, is maintained, so the counter 1 continues counting. Also, if the divided clocks of the second and third systems are output and the majority clock mtp is output before the divided clock dcp of the first system is output (in this case, the first system is That's what it means.

), when the AND gate 6 constituting the counter control circuit 3 satisfies the ASOD condition, it outputs the load signal s2, which is applied to the counter 1, and this load signal sets the preset data s3 in the counter. A frequency-divided clock dcp is output from the counter. The clock synchronization circuits b and c of the second and third systems also operate in the same manner as described above.

Therefore, when each frequency division counter is set to be a 16 frequency division counter, the first system is a leading system, the second system is an intermediate system, and the third system is a lag system, the operation of the frequency division synchronization section of each system When shown in a time chart, it becomes as shown in Fig. 3. In the first system frequency division counter, the enable signal s, falls due to the rise of the minute clock dcp, so the next step after the count value "8" is It is stopped until the majority clock 2 is output by the output of the second system's division clock dcp2, and the frequency division clock dcp of the first and second systems has already been output until the majority clock 2 is output.
,, Since the load signal s2 is output by the output of dcp3, the preset data is set, and if the clock continues to step forward, the frequency-divided clock dcp3 should be output at the position indicated by the chain line, but when the load signal s2 falls, the preset data is set. The branch clock dcp3 is forced to be output. The division counter 1 of the first system continues to increment again by the source clock after the enable signal s rises again due to the output of the frequency division clock of the second system. In this way, the frequency divided clocks dcp, , dcp2, dcp3 of the triple system are synchronized, and the majority clock obtained in each system always has a constant period. The majority clock micp obtained as described above in the frequency dividing synchronization section a is input to the frequency doubling section a2 as shown in FIG. 2, and as shown in FIG. As shown in the example in which it is used, the frequency is doubled and supplied as the basic clock to this triple system device.

In this way, in the method of creating a basic clock by multiplying the frequency of the majority clock mtp, which is the majority decision result of the frequency-divided clock, for each system, when obtaining basic clocks with the same frequency, if the frequency ratio is set to 8, for example, Since the frequency of the original clock is one-eighth of that of a method that does not double the frequency, the unit time for correction after synchronization deviation is detected (one period of the original clock, for example, 41.
7m) becomes eight times (for example, $333).

Compared to this value, the difference in pulse propagation delay due to the difference in wire length between systems (for example, if the difference in wire length is 2 skins, about 1 skin s) is a negligible value, so the difference in wire length This eliminates the need for a circuit to adjust the pulse propagation delay due to Also, the relationship between a synchronized divided clock (i.e. majority clock) and the basic clock obtained by multiplying it is 8
In the case of rented space, as shown in Figure 4, the basic clock is included in 8 periods within one period of the divided clock, but since one period of the divided clock is a short period, the basic clock that occurs during this period is The discrepancy between systems is within a very small range,
If this deviation is acceptable for the triplex system, it can be said that the basic clocks of each system are synchronized. In the above-described embodiment, the frequency division synchronizer 2 controls each frequency division counter by stopping the frequency division counter increments for the leading system using the enable signal, and presetting the frequency division counter for the lag system using the load signal. Although we have explained an example in which a method is adopted to control the value, the value of the valley frequency division counter can be changed by presetting both the lead system and the lag system using a load signal at the rising edge of the frequency division clock of the intermediate system. The frequency-divided clocks may be synchronized using a method of controlling the frequency division clocks.

In addition, any frequency circuit that can supply the basic clock required according to the processing speed of the device can be used for the frequency doubler a2, and in that case, the frequency of the basic clock supplied is There is no restriction on the operating speed of the logic element in the frequency division synchronization section.

As described above, according to the present invention, firstly, the original clock is frequency-divided by a digital frequency division counter to create a frequency-divided clock, and the frequency-divided clock of the own system is divided by the majority vote of the frequency-divided clocks of the three systems. The division counter is digitally controlled according to the comparison result so that the values are equal in the system, and the division counter is immediately controlled by the original clock input immediately after the majority result is output, so synchronization is achieved. The response speed to misalignment is extremely fast.

Second, the frequency of the majority clock obtained after synchronizing the frequency-divided clocks of each system is doubled, and the frequency-multiplied clock is used as the basic clock of the device, so even when supplying a high-frequency basic clock, There is no need to use a particularly high-frequency one for the original clock generation circuit, and therefore there is no need to use a special and expensive logic element with a particularly high operating speed in the frequency division synchronization section, and there is no need to use a special and expensive logic element with a particularly high operating speed. A clock synchronization scheme can be provided. In addition, since the majority clock is frequency-multiplied and used as the basic clock of the device, by setting the multiplication rate arbitrarily, the frequency of the basic clock can be easily and widely changed.
The synchronization method of the present invention can be easily applied to devices having widely different processing speeds.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a triple clock system;
FIG. 3 is a clock synchronization circuit diagram of the first system, FIG. 3 is a time chart showing one aspect of triple system synchronization, and FIG. 4 is a time chart showing an example in which the frequency of the majority clock is multiplied by eight. A, B, C... system, a, b, c... clock synchronous circuit,
a. ...Frequency division synchronization section, a2... Frequency doubling section, 1
・・・・・・Divide counter, 2・・・・Majority circuit,
3... Counter control circuit, s. ...Enable signal, s...Load signal, s3...
・Preset data. Figure 1 Figure 2 Figure 3 Figure 4 total

Claims (1)

[Claims] 1 In each system, the original clock pulse is divided by a digital frequency division counter to create a frequency-divided clock pulse,
The frequency divided clock pulse of the own system is compared with the majority decision result of the frequency divided clock pulse of the three systems, and according to the comparison result, the frequency division counter is controlled so that its value is equal between the systems, and the frequency of the majority decision result is doubled. A clock pulse synchronization method in a triple system, characterized in that the frequency-multiplied clock pulse is used as a basic clock pulse of a processing device.