JPS60134359A - Parallel memory system for three-dimensional address space - Google Patents

Abstract

PURPOSE:To shorten equivalently an access time per one word even if a memory element whose access time is slow is used, by reading out in parallel continuous 2K words along each axis shown by a three-dimensional logical address space. CONSTITUTION:Each line shows banks 0-3 of a memory bank, and each row is a physical address of a 4-bit portion in the bank. A number within in its drawing corresponds to a logical address. When each lower side 2-bit of logical addresses (p, y and x) is denoted as p1, p0, y1, y0, x1 and x0, respectively, the address assignment rule is bn={(a/4)+a}//4,ba=a/4, (a//4 is a surplus of the time when (a) has been divided by 4) when a bank number and a physical address of each bank are denoted as bn and ba, respectively, with respect to a=p1.2<5>+ p02<4>+y1.2<3>+y1.2<2>+x1.21+x02<0>, and as a result, as for four words continued in the three axes direction of the three-dimensional space, their bank numbers are different from each other, therefore, the access can be executed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory system in an information processing device.

In image processing and the like, when accessing image information to be processed stored in a memory, a two-dimensional logical address space is generally used to indicate the position of a target area within the image. In addition, there are three-dimensional images with spatial distances in the depth direction, three-dimensional images that express dynamic changes by arranging images at different times along the time axis, and three-dimensional images that express spectral decomposition along the wavelength axis. There is processing for accessing data with a three-dimensional structure, such as images, and in this case it is convenient to use three-dimensional logical addresses.

The three-dimensional structured data is generally a three-dimensional array A (engineering,
JSK) - (I and J% each correspond to the coordinate value in each coordinate axis direction). As for the data access order, there are many processes that require continuous access in each coordinate axis direction.For example, J and K are fixed in the above array, and only
A typical example is when the information is accessed sequentially by updating the information while adding the information. By the way, regarding the arithmetic processing section,
Speed-up is achieved through pipeline processing technology, parallel processing technology, etc., but when it comes to memory access, highly integrated but low-speed memory elements are often used in order to make large-sized memory smaller and cheaper. Therefore, it is necessary to speed up the access time of the memory system by some method.

Conventional methods for speeding up access to memory banks with consecutive addresses include accessing in block units, where n consecutive words constitute one block, and reducing the access time per word to l/n, or An interleaving method (Information Processing Handbook (Ohmsha), p. 817) in which N banks are divided into N banks that can be accessed independently and operated in parallel is known.

When sequentially accessing a one-dimensional array, it is possible to speed up the process using the two methods described above, but in order to enable continuous access in each three-dimensional direction, some further measures are required.

When dealing with two-dimensional logical address space, “Memor”
y Systems for Image Process
ssing''.

(IEEE TRANSAOTIONS ON OOM
PIJTBR8゜VOL, 0-27, Ya2, F'EB
, 1978, PP113-125)
2-dimensional 1 cp x q words in row direction or p x q words in column direction
A memory system has been proposed in which memory systems can be accessed in parallel in one of two modes: words, or pXq words in a rectangular area of nine words in the row direction and nine words in the column direction. However, in the above-mentioned paper, the treatment of three-dimensional structures (/sign) cannot be simply extended, since only memories up to the second-order 'jr:s' are considered.

An object of the present invention is to provide a memory system t having a three-dimensional logical address space for processing data having a three-dimensional structure.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory system in which the access time per word is substantially shortened with respect to consecutive accesses in three-dimensional axis directions in order to speed up memory access.

The structure of the present invention is a memory module that operates by independent addressing in a word-organized random access memory and reads and writes data of two words in parallel in each bank of two memory banks. A mode parameter for selecting one of P mode, X mode, and X mode as a memory access mode for the three-dimensional address space (P, Y,
X)
, pl, po), y-(Ym-1+”””・Y +
+”””, yl +Y o), X = (xl 1
r"-"' + X + + """ + X t +
X0), p, +Y11X, represents 1 bit in binary representation), and according to the mode parameters,
In P mode, pk-□+ p y-2+...-,
po, in X mode, Yk-1"Yk-2"4', in y0°X mode, X k-r r X h-21...
・Address generation means for generating an address that exclusively associates one word corresponding to an access address other than one of , xo with the one memory bank t;
WE! 2. A three-dimensional address space 1H characterized by comprising a word order conversion means for inputting and outputting data by making a correspondence between the word order according to the addresses of 2k words and the bank number order of 2k memory banks. is a parallel memory system for

A specific embodiment Q will be explained below with reference to the drawings. In the embodiment, for the sake of simplicity, a case will be described in which the hardware parameter k that defines the number of memory banks is equal to 2.

FIG. 1 is a block diagram showing the configuration of a specific embodiment of the present invention. 103.104.105.106 are 4 (2 = 2) memory units that can operate independently.
'lltζ These are memory bank 0, memory bank 1, memory bank 2, and memory bank 3. Signal line 1000 is 3
A signal for selecting one of P mode, The signal line 1001 is a three-dimensional address signal line, and is a three-dimensional address signal line (
psyxx), (here p=pn-1,...+
p, 1rp0)y = (ym-1゜-...,y,,y,
)', X =, (x7' 1 r """, X 1
．． X, )) is input to the address generation circuit 100. Also, during a write operation, the signal lines 1002.10o3.
1004 and 1005, 4 (2, -=z) words of write data are input to the write data word order conversion circuit 101.

The address generation circuit 100 generates an address for memory access in the mode selected by the mode parameter to each memory bank on signal lines 1o13.1014.10.
15. Output to 1016. Also, the address generation circuit 10
0 is the write data word order conversion circuit 1014 and the signal line 1
002.1O03, 101) 4. Write data signal iIM101 to each memory bank with 4 words input from 1005
7.1018.1019.1o2o When the word order conversion signal is output to the signal line 1012#, the read data word order conversion circuit 102I is simultaneously outputted to the read data signal line 1o21.1022 of each memory bank.
．． A word order conversion signal is output to the signal line 1011 for converting the four-word data input from 1023, 1024 into the word order according to the address values of the signal lines 1006, 1007, and 008, 1009, and outputting the converted word order.

A signal indicating that memory access is a write is input from the signal line 1010; however, if this signal is not active, the state is set to read.

Next, the operations of the address generation circuit 100, write data word order conversion circuit 1011, and read data word order conversion circuit 102 will be described in detail.

FIG. 2 is a schematic diagram showing the data structure of a three-dimensional array.

The X axis is horizontal to the paper, and the vertical direction? The P-axis is taken in the depth direction. An element of this array is one word of data, and has a coordinate value (p=y.

X) specifies one word. In Fig. 2, the entire space is divided into small areas of 4 x 4 x 4 words with each side consisting of 4 consecutive words in the three axis directions, but in the present invention, the 4 x 4 x 4 M small Treat the area as a unit. This invention ζ
Accordingly, it is possible to obtain a memory system that accesses four consecutive words in three axial directions in parallel in the small area.

FIG. 3 shows numbers assigned to the six words of the small area, using hexadecimal representation. In the figure f) 0+
p 1 + p 2 r p 3 shows a cross section in the P-axis direction in FIG. 2, and it is assumed that 4×4 word branes are lined up in the depth direction ζ. The said number is hexadecimal 2
Although it is expressed in digits, it is essentially 6 bits of information, starting from the lowest two bits in order: X, , the lowest two bits of the YSP address. Using the above numbers, the four words that can be accessed sequentially according to the present invention are as follows. In the following, numbers are 1 unless otherwise specified.
Use hexadecimal number.

(1) X mode; IxlO+Jx4, lX10+
JX4+l.

IxlO+Jx4+2, lX10+JX4+3.

(However, I=0.1, 2, 3. J=0.1, 2.3
) (1) Formula 4 formula % (where I=O, 1, 2, 3, J=O, 1, 2, 3) (
2) Formula (3) P mode; 4xI+J, 10+4xI
+J.

20+4xIxJ, 30+4Xl+J.

(However, I=0.1,2,3., T-0,1,2,3
) (3) In order to access 4 (2=2) words, it is conceivable to use four memory banks that can be independently addressed. However, the above 3
In any of the two modes, the specified (p.

In order to make the address words (y,

FIG. 4 is a diagram showing the assignment of addresses to each memory bank employed in the present invention. Each row is bank 0 of the memory bank. Bank 1, Bank 2. Bank 3 is shown, and each column represents a 4-bit physical address (1
(0 to F in hexadecimal). The numbers written in the figure correspond to the numbers in FIG. 3, that is, the logical addresses. The address assignment rule in FIG. 4 can be expressed mathematically as follows. Logical address (p, y,
x), pl, po+Y1+Vo+X
1+χ0, a=p, ・25+p024+y1・23+y1◆22+
x1-210Xo2 For equation (4), let the bank number be, l, and the physical address of each bank, then b - ((a/4)+a)/4 (5) equation b = a/ 4
Equation (6) (here, a/4 + a// 4 indicates the quotient and remainder when a is divided by 4.) According to the above assignment rule, four consecutive words in the three axes of the three-dimensional space Since they have different bank numbers, they can be accessed in parallel.

FIG. 5 is a block diagram showing the specific configuration of an embodiment suitable for the address generation circuit. Since we are dealing here with only four consecutive words in the 4X4X4 word small area mentioned in the explanation of Figure 2, we will use the 6-bit value consisting of the lower 2 bits corresponding to each axis of the logical address, that is, the 6-bit value in equation (4) above. Enter the value and move it to the memory bank with the bank number obtained by formula (5) (6
) only the function that outputs the physical address value given by the formula is extracted. In Figure 5, the signal line 2003.20
04 and 2005 are address signal inputs of the lower two bits in the P, Y, and X directions, respectively, and the zero-successless circuit 20
0.201.202 respectively. signal a 2
006.2001.2002 is a mode parameter for selecting the mode of P, Y, and X, and only one of the three trees becomes active. The mode parameter signal is 'f! rlIllc is input to corresponding zero suppress circuits 200, 201, and 202, and the 2-bit address value for the active mode is zero suppressed. For example, in X mode, signal line 2005
The lower 2-bit address in the X direction from 1 is zeroed by the zero-the-breath circuit 202 by the signal on the X mode signal line 2002 and output to the signal line 2008. Similarly X
In the mode, the lower two bits of the address in the Y direction are suppressed with zeros and outputted from the signal line 2007f, and in the P mode, the lower two bits of the address in the P direction are suppressed with zeros and outputted to the signal i* 2006. Note that zero suppression [g circuits 200, 201, and 202, in modes that do not support the input 2-bit address value or 0
．． r R is output. 7JLI'lI-dg203
．． 204 is a 2-bit adder. KA'J#, vessel 20
3 outputs the addition result of the 62-bit address input through the signal lines 2007 and 2008 to the signal line 2009, and the adder 204 adds the 2-bit address of the signal 12006 to the addition result and outputs it to the signal line 2010. For convenience, this value will be referred to as ``one number'' hereinafter. The signal line 201
The 0 signal is input to the table memo IJ (ROM) 205 and routed to line 46 2011.2O12, 2013, 2014
Read out each signal. Chiful Memo J Bar R, OM) 20
The contents of 5 are as shown in Figure 6. , R□.

Each output of R2, I (3 becomes -t11S of the physical address for the four memory banks.Here, we will focus on the memory bank puncture & number 01 and explain the generation of the physical address.) The table memory 205 The address value derived from fg line 20141 is multiplexer l!-
Multiplexer 21 for bank number 0 of 1 path 206
0.211. -10,000 Multibrexa 2
The lower 2 bits of the P address are also input by the signal &2003, and the multiplexer 211ζ
Here, the lower two hits of the Y address are also input manually via the signal line 2004. The select signal of said multiplexer 210.211 is the mode parameter signal of signal arm 2000.2001. In P mode, the signal line 2000 becomes active, and the output signal line 20 of the multiplexer 210
21, the input value on the signal line 2014 side is output, and in other modes, the signal line 2003 side is selected. Similarly, in the multiplexer 211, signal line 2 is used only in the X mode.
The 014 side is selected and output to the signal line 2022. Similar processing is performed on physical addresses for other banks and output to signal lines 2015-2020. signal line 200
3. The lower 2-bit address in each axis direction of 2004 and 2005 is p/.

y/, x/, and if the table memory output for bank number i is r, then the 4 bits of the physical address for the memory bank of bank number i are the following combinations.

In X mode p / y / In YX mode p/r In P mode r, y/ This satisfies equations (1), (2), and (3).

FIG. 7 is a block diagram showing a specific example of the configuration of a word order converting circuit for making correspondence between the memory bank scan code order and the logical address order of input 4-order data. Four words of input data are input from signal lines 3000.3001.3002.3003. The radix used for referencing the table memory 205 in FIG. 5 is input to the signal line 3004 as a word-by-word shift signal.

The multiplexer 300 is for one word shift, and its output is connected to signal lines 3005.3006.3007.
．． 30081 is output and input to the multiplexer 301 for two-word shift, and the result is sent to the signal line 3009.3.
Output to 010.3011.3012.

The relationship between the base number and the shift number will be explained using FIGS. 3 and 4. If, among the four words to be accessed in parallel, a word ζ in the P-brane in FIG. 3 is located in M row and N column, then the base number is CM+N)/4. For example, in P mode, 05, p of the P0 plane in Figure 3, 15, p2 of the brane
When accessing four words, 25 in the plane and 35 in the p3 plane, the base number is 05 in the p0 plane, in the first row,
Since it is a column, it is 2. At this time, in FIG. 4, the memory having the logical address is set as a pair (bn, ba) of bank number bn1 physical address b11 in order (2, 1).
.

(3,5), (0,9), (1,b). In other words, for the cycle number of O, 1.2.3, where the bank number starts from the radix, word order correspondence can be achieved by performing a rotation shift on a word-by-word basis by the amount of the radix. However, in the above word order conversion, the direction of rotation shift is reversed between writing and reading, but the signal line 3000.30 in FIG.
01.3O02, 3003 and signal line 3009.3010
．． By inverting the order of 3011.3012,
Both a write data word order conversion circuit and a read data word order conversion circuit can be configured.

According to the present invention, one continuous word along each axis shown in a three-dimensional logical address space can be read out in parallel.

Therefore, even if a memory element with a slow access time is used, the access time per word is isometrically shortened, so that a memory system suitable for a high-speed processing system can be configured.

This is also effective in speeding up memory access time when a long arithmetic processing unit is sped up.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing a specific embodiment of the present invention;
Figure 2 is a diagram for explaining the three-dimensional logical address space handled by the present invention, Figure 3 is a diagram showing a 4X4X4 word small area handled in a specific embodiment, and Figure 4 is a diagram for explaining the 6 words in the small area. FIG. 5 is a block diagram showing a specific embodiment of the address generation circuit. FIG. 6 is a diagram showing the contents of the table memory used in the address generation circuit. FIG. 7 is a block diagram showing a specific embodiment of a write data word order conversion circuit and a read data word order conversion circuit. In the figure, 100 is an address generation circuit, 101.10
2 is a write data word order conversion circuit and a read data word order conversion circuit, 103.104.1()5.106 is a memory bank, 200.201.202 is a zero suppression circuit, 20
3. 204 is an adder, 205 is a table memory, 210
．． 211 is a multiplexer, 206 is a multiplexer prepared for each memory bank, 300.301 is a multiplexer for 4 words, 1000 to 1024. 2000 to 20
22. 3000 to 3012 indicate signal lines. Figure 1 Figure 2 Rain 3 Figure 1% $4 Figure 5 Ward 4 Figure 7

Claims (1)

[Claims] A word-organized random access memory module which operates by independent addressing and reads two words of data in parallel in each bank of two memory banks. with a three-dimensional address space (P, Y,
P mode as the memory access mode for X),
Set the mode parameter for selecting one of the current mode and X mode to the access address (1), y,
=(px-1,,-1,,pi,==-2pl,
I) 0), y=(yIT, -0゜°°゛°°“+y,,
-+y 1. yo), x-(xJ 1 r'°"",
x. ""+X1.
...+1) o. In Y mode, y, -1, Yk-2, ..., y,
X mode 0))'MoIJ Address generation means that generates an address that is exclusively associated with a bank, and data that corresponds to the word order according to the word address in 2. and the bank number order of the memory banks in 2. 1. A parallel memory system for a three-dimensional address space, comprising: word order conversion means for performing input/output.