JPS5899835A - Picture processor - Google Patents

Abstract

PURPOSE:To simplify the constitution of a picture memory, and to execute parallel access of a square window of prescribed size, at an optional position on a two-dimensional picture element array, at a high speed, by providing a window access memory for executing a direct data transfer, between the picture memory and a parallel operating circuit. CONSTITUTION:Picture data of a two-dimensional picture element array is stored in each memory chip SOO-SRR, upper address lines 10PO-10PR, and lower address lines 10QO-10PR are connected to an address comparator 12P and an address converter 12Q, respectively. These lines 10PO-10PR and 10QO-10PR are made to a multiple system of nP lines and nQ lines, and each chip SOO-SRR is accessed to the picture data by an upper address P and a lower address Q whose in-reference window relative position U and V are same. Also, on each chip SOO-SRR, data lines DOO-DRR for executing write and readout are provided, these lines DOO-DRR are connected to a data selector 16, and the picture data is outputted from the data lines dOO-dRR of the data selector 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing apparatus, and particularly to a high-speed parallel access image processing apparatus using a window access memory.

Image processing, for example, processing of an image consisting of a two-dimensional pixel array, requires handling a large amount of image data of many pixels at high speed. This requires a large amount of processing time in a sequential processing computer, so an image processing processor placed at the bottom of the memory hierarchy performs parallel operations to process the image data while preserving the two-dimensional array data structure. It is.

Conventionally, a locally parallel image processing device (LPIP), which performs locally parallel operations using the locality of image processing such as facsimile or television images, processes local images using the number of processor elements that can be realized due to the locality. It performs parallel operations on data and scans the processing on the screen. However, parallel operation in data transfer between the image memory and the parallel processing circuit is performed through a buffer interposed between the two, and it cannot necessarily be said that sufficient high-speed parallel access is performed. In addition, in order to accommodate high-speed parallel processing of such a large amount of image data, it is necessary to use a storage device as image memory that satisfies the two incompatible requirements of large storage capacity and high-speed access, which is not practical. Not. Therefore, high-speed parallel access of arbitrary windows in a two-dimensional pixel array has been extremely difficult.

The present invention solves the drawbacks of the prior art and provides an image processing device that allows parallel access of rectangular windows of a predetermined size at arbitrary positions on a two-dimensional pixel array in a multilayered manner. purpose.

This purpose, according to the present invention, is a window access memory IJ (WAM) that performs direct data transfer between an image memory and a parallel processing circuit for all pixels included in a window at an arbitrary position on a two-dimensional pixel array. This is achieved by configuring.

An image processing device according to the present invention includes a plurality of memories that can be read and written independently from each other and store image data in each reference window obtained by equally dividing a two-dimensional pixel array, and each memory stores image data in each reference window obtained by equally dividing a two-dimensional pixel array. Image data of a pixel at a relative position within the window is stored in a storage location specified by an address corresponding to the coordinates of the reference window, and furthermore, when the coordinates of the window in the two-dimensional pixel array are given, the coordinates of this window are used as the reference window. An addressing circuit generates the address of the storage location of the image data of the pixel in each memory from the coordinates of the window depending on the degree of deviation from the coordinates of the window, and specifies the address of each memory. When the image data of each pixel included in the memory is read out in parallel, the degree of deviation corresponds to the image data read out in each memory.
The read image data is organized into image data corresponding to the relative position within the window of the window according to the relative position of the pixel in the window, and the image data is stored in each memory. When writing, the image data given corresponding to the relative position within the window in the window is written according to the degree of the shift and the relative position within the window of the pixel corresponding to the image data to be written into each memory. It includes a data organization circuit that organizes image data corresponding to relative positions within the reference window and writes the data in parallel to each memory.

Next, embodiments of an image processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a rectangular coordinate system (j%j) (i%j is an integer) representing a two-dimensional pixel array of an image to be processed. Generally, in this pixel array (i, j), a square area with one side of size R+1 (R is a natural number), or a "window", contains (R+1)" pixels, but this window is defined as W (i, j) 4 ((i+I, j+J) I L J=
Os 1, ..., R). This is, for example, the square area surrounded by the dotted line in Figure 1, w (i
, j). expressed. In Fig. 1, the windows arranged adjacent to each other without overlapping each other with respect to the coordinate axes, that is, the j-axis and the j-axis, are referred to as "reference windows JW, , Q.
It is called WP%. = W (P (P+1), Q(P+1))
It is defined as However, P and Q are non-negative integers. The reference window is a square area surrounded by a solid line in FIG.

As will become clear from the following description, it is advantageous for R, P, and Q to be powers of 2 in order to effectively utilize the hardware as a memory for storing pixel data. Therefore, R+ 1 = 2 r(2) pg(o, 1,..., 2nP-1) (3) Qg(0, 1,..., 2nQ-1) (4)
shall be. However, r%np and n are positive integers.

Therefore, the two-dimensional pixel arrangement in Figure 1 P + n Q The total number of reference windows W in the column is 2 P% Q It is.

In the image processing bag device according to the present invention, reference window WP1. Data d of each pixel included in (P2r+U, Q2r+V) :U%Vj (O
ll,...,R) (5) is (P+1) two physically independent memory chips S
It is stored at the location specified by the address AP, , corresponding to P and Q of U, , that is, the storage location. In other words, it is included in a certain reference window WP, , and the relative position in the reference window, that is, the relative position within the reference window is (U,
The image data of the pixel V) is the address Us' ps corresponding to the address A of the memory chip S.
For example, it is stored in the Q application as one memory word.

Therefore, if we look at one memory chip ``U, V, this chip has pixel data d (P2
+U, Q2 +V) to address AP1. It is remembered, that is, "handled" in correspondence with. As a result, a window access memory whose position on the screen can be specified arbitrarily can be configured with a minimum number of chips.

Here, for convenience of explanation, it is assumed that F, Q give an address A such that P is the upper bit of the address line of the memory chips SU, V and Q is the lower pit. That is, Q AP, ,=P2 +Q (6).

In addition, in these descriptions, reference window WP1. Although the size of the window (i, j) including The two-dimensional pixel array (i, j) may be divided into rectangles with different lengths.

By the way, the general window W (i% j) is 1=P2r+M
: M! (0,1,...,R) (7)j=Q
2r+N; N1 (0%1%-..., R) (8
), the reference window WP1 . otherwise, reference window 2, Q P+1, Q
Pl, +1 and (also W , W
, W is) WP+11. +, including a part of -. therefore,
As mentioned above, in the memory chip S, 2 which stores the pixel data at the location specified by the address A corresponding to the reference window W, the pixel corresponding to the window W(t, j) In order to access the data, at most four of the above-mentioned reference windows included in the window W(i%j) must be used. Q or Q+1) will be used.

This address A, -%, - is the reference window WP1. of the window W (i%j). According to the degree of deviation from B, that is, the values of M and N, corresponding locations in different memory chips SUV are specified. Focusing on a certain memory chip defect 2, in that chip defect 2, image data of relative positions (U, V) within the reference window in each reference window WP, , are stored corresponding to address A, P, Q. However, as can be seen from Fig. 1, these data are the pixel data d(i+I,
j+J) depends on M and N. However, it is Jt(o, 1, . . ., R). To briefly illustrate this situation, for example, for a one-dimensional pixel array in the j direction, the relative position J in the window of pixel j and its corresponding position on the pixel array, that is, the position Q on the screen.
2 The relationship with +V is listed in Table 1.

Table 1 According to this table, Q and V determine the position Q"2r+v on the screen corresponding to the relative position J in the window according to the value of N.
The value of changes. In other words, when N+J≦R, Q -Q%V=N+J
(9) When N+J≧R+1, Q = Q+1, V-N
+J − (R+1)1, and the larger N is, the more memory chips are accessed at the address Q+1.

Tables 2 and 3 summarize this situation by focusing on individual memory chips.

Table 2 Table 3 Table 2 shows the lower address Q supplied to each memory chip in the j direction. For example, the memory chip corresponding to the relative position V within the reference window in the j direction is accessed with Q as the lower address Q'' when the value of N is less than or equal to v,
If it is larger than (2), it is accessed with Q+l.

Table 3 shows the correspondence between the relative position J of a pixel within the window and the memory chip in the j direction. According to this table, each memory chip stores accessed pixel data at a different relative position within the window according to the value of N. Treated as data corresponding to J. Therefore, in the j direction, when accessing pixel data of a general window, each memory chip accesses the pixel data at the lower address Q"(<2 Q-1) shown in Table 2, and the accessed pixel The data is processed as corresponding to the relative position J within the window shown in Table 3.

Similarly, for the pixel arrangement in the i direction, when M+I≦R, P −P, U=M+I
C+1) When M+I≧R+1, P article=P+1, U=
M+I-(R+1)(2).

Therefore, a window access memory consisting of memory chips SU, V has the upper and lower addresses P of each memory chip SU, V from i and j specifying the window W (iX j).
and Q, and these addresses P'' and Q
The pixel data words of each memory chip SU, V specified by are accessed in parallel. These data words accessed in each memory chip SU, V are stored in M of the window W(i,j)
and its relative position within the window depending on the value of N (Eng., J
) is handled, that is, read or written, by the corresponding data line.

An example of an image processing device that realizes this function is shown in FIG. In the same figure, the image processing device includes a memory chip S that stores image data of the two-dimensional pixel array shown in FIG.
. It has 0-8RR. Each memory chip S. Q””””
It is desirable that the RRs be independently accessible from each other and typically physically separated from each other.

Memory chip S. 0"'=SRR is the relative position 41 (within the corresponding reference window) in each reference window shown in FIG.
The image data of U, V) is stored at the location specified by the address AP, Q.

Each memory step S. Upper address 51 of 0"""'RR
opo to IQPR are connected to the upper address converter 12P, and lower address lines 10QO to 10QIlj are connected to the lower address converter Q. The upper address lines 10PO to 10PR have the number of bits nP, and the n upper address lines of the memory block 5UO=SUR, in which the relative position U in the reference window in the i direction in each reference window is the same, are duplicated and the upper address converter 2P connected to the address output of Therefore, each memory chip S00''SRR is accessed to image data at the same upper address P for each group of chips having the same relative position U within the reference window.Similarly, the lower address lines 10QO~
IQQR is the number of bits n, and the memory chip S has the same relative position V in the reference window in the j direction in each reference window.
-8 n3 lower address lines are double OV
RV type and connected to the address output of lower address converter 2Q. Therefore each memory step S. 0
``''''''''The RR accesses the image data at the same lower address Q for each group of steps having the same relative position within the reference window fz.

Lower address converter 12Q has inputs 14Q and 14
N, thereby inputting Q and N to the lower address converter 12Q as the lower address j of window (i, j). Therefore, input 14Q is n, bits, 14
N has r pits. Lower address output node (-ta 12
Q is the window W (1% j) input from input 14Q
The lower address Q in the j direction of
Convert the address (” to memory chip “-8oo-8-
The corresponding Q is set according to the V of address lines 10QO to 1O.
This is an address conversion circuit that outputs parallel to QR. This conversion is performed according to Table 2, for example, if N is 2, the -lower address line 10QO of chip SU0 and
and 10Q1 has Q+l as Q, and lower address lines 10Q2 to 10Q of other chips 5tr2 to SUR.
Q is output as "Q" to R. Similarly, the upper address converter 12P has inputs 14P and 14M,
The upper address P is converted into an actual upper address P7 according to M and U, and the memory chip S is converted. This is an address conversion circuit that outputs a corresponding P'' to address lines 10PO to 10PR according to U of 0 to SRR.These address converters 12P and 12Q are simple combinations that perform address conversion according to Table 2 and the table. The memory chip S.o-8RR can be realized by a logic circuit, and is preferably realized by a read-only memory (ROM), and has data lines DOO to DRR for reading and writing pixel data words.
These are connected to the data selector 16. The data selector 16 has other data lines d00 to dRR and is connected to the memory chip S. , ~So to the data lines DOO~DRR using the reference window, and the pixel data read out corresponding to the pair of QQ positions (U, V) are transferred to the data lines d00~dRR corresponding to the relative positions within the window (■, J). Convert the position to and output it, and also
The pixel data given to the data lines doO to dRR corresponding to the relative positions within the window (■, J) are transferred to the relative positions within the reference window (U,
The memory step S converts the position and outputs the data lines DOO to DRH corresponding to V). 0" is a conversion circuit that supplies write data to SRH. For this conversion, M and N are input from leads 14M and 14N to data selector 16. Note that window access memory S.0 to
Read R) and write (W) of SRR are controlled by read R/W. Such data conversion in the data selector 16 is performed according to Table 3 mentioned above. For example, looking at the j direction, if the addressed window W (i%j)c7)N is 1, the relative position J within the window is R,Oll from the memory chips sUo to sUR to the data line 000-DRH. ,..., are read out as pixel data corresponding to R-2 and R-1, but
The data selector 16 sets this as 0.1, . . . , R-1,
The position is converted to pixel data in the order R and the data line doO
~ Output to dRR. In addition, in the case of writing, the pixel data given to the data lines doO to dRR are position-transformed so that the relative position J within the window corresponds to R10, 1, ..., R-2, and R-1. Output to lines D00 to DRR and memory chip S. 0""'Write to SRR.

Since the data selector 16 is a simple combinational logic circuit that performs such position conversion, the address converter 1
It can be configured with a read-only memory like 2P or 12Q, but since the data transfer direction is the opposite for reading and writing, it is better to implement it with a bidirectional multiplexer, which reduces the hardware size. can be made smaller.

To explain the operation, address P of window w (1% J)
, M%Q and N are address manual 14P.

14M, 14Q and 14N, address converters 12P and 12Q convert this to addresses P and Q. Therefore each chip S. 0”””
"RR's address human power 10P1~10PR and 1
Addresses P" and Q" converted according to M and N are given to oQo to 10QR as described above. When a read designation is given to the read R/W, each memory chip S. 0"SRR reads pixel data in parallel from locations specified by addresses P" and Q to data lines DOO-DRH. Data selector 16 is data line D
The position of the pixel data read out from OO to DRR is converted according to the values of M and N, and the pixel data d (i, j
), ..., d (i+Rs j +R) and output in parallel. Furthermore, when a write designation is given to the read R/W, the data selector 16 selects the data lines d00 to dRR.
The position of the pixel data given to is converted according to the values of M and N, and the relative position t within the reference window is set to the data lines DOO to DRR.
Output as pixel data corresponding to (U, V). Each memory chip S-8RR writes pixel data of data lines DOO to DRRO in parallel to locations designated by addresses P and Q, which are the outputs of address converters 12P and 12Q.

By having the image processing apparatus according to the present invention configured as described above, it is possible to perform high-speed parallel access to the window access memory with the minimum hardware scale without intervening a buffer memory or the like. The access time of this window access memory is the memory chip S. This is the sum of the access time of 0 to SRR and the propagation delay time of address converter 12P or 12Q and data selector 16, which is much smaller than when a buffer memory is interposed. In terms of hardware scale, n p + as image data memory
n Q 2 x 1 bit r read/write memory per pit plane, upper address n p +
2 Xn p-bit ROM as a converter
n + r 2 (2 The 256 x 256 pixel bit plane window access memory, which can perform window access, has 16 4 x 1 pit read/write memories (
For example, 2141), 6 256 x 6 bit R
OM (such as TBP28L22), and 16
16-channel bidirectional multiplexer (for example, 40
67B, etc.).

Therefore, as long as the size of the window is not too large, high-speed parallel access of image data can be performed using an easily realizable hardware-scale window access memory.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an orthogonal coordinate system (i, j) representing a two-dimensional pixel array for detailed explanation of the present invention, and FIG. 2 is a block diagram showing an embodiment of an image processing device according to the present invention. . 12P, 12Q...Address converter 16
...Data selector So, ~SRR mountain...Memory chip WP1.・・・・・・Reference window

Claims (1)

[Scope of Claims] Includes a plurality of memories that can be read and written independently from each other and store image data in each reference window obtained by equally dividing a 12-dimensional pixel array, and each of the plurality of memories stores image data in a different reference window. The image data of a pixel at a relative position within a reference window is stored in a storage location specified by an address corresponding to the coordinates of the reference window, and when the coordinates of the window in the two-dimensional pixel array are given, the coordinates of the window are an addressing circuit that specifies the address of each memory by generating the address of the storage location of the image data of the pixel in each memory from the coordinates of the window according to the degree of deviation from the coordinates of the reference window; When the image data of each pixel included in the window is read out in parallel, the readout is performed according to the degree of the shift and the relative position within the window of the pixel corresponding to the image data read out in each memory. The output image data is organized into image data corresponding to the relative position within the window in the window and output, and when writing the image data to each memory, the image data is organized into image data corresponding to the relative position within the window in the window. The image data is organized into image data corresponding to the relative position within the reference window according to the degree of deviation and the relative position within the window of the pixel corresponding to the image data to be written into each memory. An image processing device comprising: a data organization circuit that writes data in parallel to a memory. 2. The device according to claim 1, wherein the addressing circuit comprises a combinational logic circuit including a read-only memory, and the data organization circuit outputs data read from the memory and outputs the data to the memory. An image processing device comprising a bidirectional multiplexer in which data to be written is input in both directions using the same data line.