JPS6367655A - Memory system for processing two-dimensional information - Google Patents

Abstract

PURPOSE:To increase possibility of parallel accesses by using designing parameters (p) and (q) to calculate the data on a lattice point shown by the position coordinates (i, j) by means of a specific function. CONSTITUTION:An address evolving part 20 decides a gathering of lattice point data actually required form coordinates (i, j) and a block form (t) and calculates concretely the coordinates of each lattice point. In such a case, a single block includes 8 lattice points and therefore 8 different coordinates (i0, j0)-(i7j7) are outputted in parallel. These different coordinates are sent to 8 module control units M030-M737 via signal lines 200-207 respectively. Each of these control units uses the coordinates (ik, jk) to calculate the number mk showing a specific memory module that contains the data on the relevant lattice point based on a formula. The double oblique lines in the equation show the operators that show the quotient and the residue obtained through divisions using integers.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a memory method that can efficiently access a data subarray having a specific shape in a data set arranged in a two-dimensional orthogonal grid. It is something to do.

[Conventional technology]

In data processing by a computer, data to be processed is sometimes arranged in a two-dimensional orthogonal grid. A typical example of such processing is image data processing.

In addition, even with data other than images, there are many situations in which two-dimensional array data is handled, such as when data is arranged two-dimensionally for statistical processing, or when data is displayed two-dimensionally to make it easier for humans to understand. It will be done.

In data having such a structure, it is frequently necessary to access a portion of the data that has a predetermined shape. For example, in image processing, data of a square (rectangular) area in the vicinity of a suitable point of interest is used at once. Also, statistical processing often requires an entire row or column at the same time.

To efficiently access data with the above shape,
One possible method is to divide the storage device into several modules that can be accessed in parallel, distribute data appropriately to each module, and parallelize access. An invention for this purpose was published in Japanese Patent Publication No. 56-44449, in which data within the area can be accessed in parallel for three parties: ■ IXP (horizontal area of I; ■ vertical area of pqX1; and ■ PX (rectangular area of I). However, regarding (2), there are restrictions on the arrangement of areas that can be accessed in parallel, and speeding up of access is not necessarily achieved.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the following measures are specifically used for image data.

The target data is a screen in which pixels are arranged in a square grid, and can be schematically shown as shown in FIG.

In image processing, some of these pixel data are used simultaneously. Pixels that are used simultaneously are arranged in a specific shape, and specifically, the shapes shown in 21 to 23 in FIG. 2 are typical.

In the figure, pp q is a design parameter, and in the figure, p=4,
An example of q=2 is shown.

These pixel data are stored in a memory device 10 of the type shown in FIG. The device includes several memory modules 50 that can be accessed in parallel, 21 to 21 in FIG.
Pixel data included in each shape shown at 23 is distributed and stored in each module according to an appropriate rule. It is clear that in order to access these simultaneously, the number of memory modules must be pq or more. Here, we consider the case where the number of modules is exactly pq, and each module has O
It is assumed that the numbers from Pq-1 to Pq-1 are attached.

In such a device, the problem of access parallelization can be reduced to the following problem. In other words, the problem is which module number should the data of the pixel in the i-th row and j-th column be stored in? Mathematically speaking, the function M (i, j) that calculates the module number with jv i as input is It is nothing but a matter of determination.

In the conventional technology, M(i, j) is M(ITJ).
=(i×q+(i/p)//q+j)//(p×q)
The formula was used. However, / and // are operators indicating the quotient and remainder, respectively, when divided by an integer.

As in FIG. 2, p=4. If this pattern is shown as q"2, it will look like Figure 4. In the figure, the number written at the position of each pixel indicates the number of the memory module in which that pixel data is stored. The arrangement is repeated on the right and bottom of the screen, but is omitted in Figure 1.

With this method, parallel access to data having the shape shown at 21.22 in FIG. 2 is possible.

However, parallel access is not possible for 23-shaped blocks unless the block position satisfies a certain condition. Specifically, parallel access is possible only when the row coordinate of the topmost pixel of the block is a multiple of p.

In the present invention, the function M(IIJ) is improved to expand the possibility of parallel access. The points to note here are 2.
The point is that it is impossible to enable parallel access at arbitrary block positions for all shapes No. 1 to No. 23. However, M(i.

j) It is possible to expand the possibility of access, and the function can be defined as follows.

[Means for solving problems]

The above purpose is to set M(1+j) as M(it j)=((i+j/q)Xq-1-(, j+
This is achieved by using the function i/p)//q)//(p×q).

FIG. 1 shows the correspondence between pixels and modules based on this function. The figure shows an example of P''4+q=2.

[Effect]

The main point of modifying the function in this way is to make changes in module numbers within the same line non-monotonous. In the conventional method, the column position j in the formula for M(i, j) is simply added (excluding the outermost //pq), and this causes the rectangular block shown by 23 in FIG. Parallel accessibility was reduced. In the present invention, by restricting carry in the addition of j, changes in module numbers within the same row are given locality, and duplication of module numbers that becomes an obstacle to parallel access is reduced.
Regarding the shape shown in Figure 21.22, parallel access was possible at any block position using the conventional method, but
The present invention also retains the same possible properties.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 5 to 9.

In the following explanation, design parameters p and q are expressed as p=4=
22. The case where q=2, therefore the number of modules pq=8 is shown. By taking p and q to powers of 2 in this manner, the circuit configuration of a computer based on the binary system is simplified. Of course, the present invention is effective even when p and q are not powers of 2.

FIG. 5 shows an outline of the memory circuit 10 according to the method of the present invention and a data processing device 100 connected thereto.

Data processing device 100 is not part of the invention, but is illustrated to clarify the functionality of the invention. 'First, let me explain this part.

The data processing device 100 reads and writes data to and from the memory circuit 1 through the signal line 110 depending on the processing content.

At this time, relative to 1, the ordinate is 1120°, the abscissa is j130,
Block shape t140 and reading/writing distinction R/W15
Supply 0. All data accesses are done in parallel. i and j indicate the coordinates of the reference point of the data block that is accessed simultaneously, and t indicates the shape of the block as a 2-bit binary number, where t=00 indicates a horizontally long block, 01 indicates a vertically long block, and 10 indicates a rectangular block. do.

° Using the above signals, the memory circuit 1 operates as follows. First, the address expansion unit 20 calculates the coordinates 1s j
From the block shape and block shape t, a set of actually required grid point data is determined, and the coordinates of each grid point are specifically calculated.

In this example, since there are eight grid points in one block, there are eight types of coordinates (xot jO) to (17157
) are output in parallel. Two nine signal lines 200 to 207
through eight module control units Mo30~M7
37 respectively. Each module control unit uses the coordinates (ih, jh) to determine the number mk indicating in which memory module the data of the grid point is stored using the rule mh = ((i, +jk/q) x q + (jk + ih /p
)//q)//(p×q). The above calculation formula is the same as the formula described in the claims except for the subscript k.

The module control units 30 to 37 calculate m+t as well as the address ah of the data in the memory module. Each of mk and ah is combined with the data transfer line 110 to the processing device 100 and sent to the digital bidirectional crossbar switch 40 as signal lines 300 to 307.

The crossbar switch 40 connects a data line Dk and an intra-module address ak to the corresponding memory module using the module number mk. Thereby, the connection between the memory modules 50 to 57 and the processing device 100 is completed, and data can be transmitted and received between them.

Each of the memory modules 50-57 actually reads and writes data using data lines from the crossbar switch, address lines, and a read/write signal 150 directly applied from the processing device 100.

The details of each element will be explained below using FIGS. 6 to 9.

Address expansion part.

FIG. 6 shows the address expansion section 2o. In this part, 8 (=p
q) It has a function of creating a set of coordinates (101jo) to (17°j7) according to the designation of the block shape t.

The 2-bit signal t is converted into four control signals α231 . β232. It is converted into γ233° δ234.

OR gate 235 and NOR gate 236 are used for this purpose. These signals i is the coordinate addend determination unit 210
and used in the two-coordinate addend determination unit 220.

The coordinate signal (i, j) is branched into eight parts, (lo+jo)
It becomes the standard for calculating ~ (Sat 7. J7). These coordinates are added to the addends produced by 210 and 220 in the adder 250.
It is calculated by adding (x+j)L using 260 and 260. For (i 0t j o), (i,
The value of j) may be used as is. ・210.220 are respectively i addend determination unit 2] 1 or j addend determination unit 2
21 are arranged side by side. Figures 6(b) and (Q) are
This shows the details of each unit. 2 to these
By giving the output of 30 as shown, -(ihy
The value obtained for jh) is the value shown in FIG. 6(d).

These values correspond to the block shape defined in FIG.

Module Control Unit FIG. 7 shows details of the module control units 30-37. In this unit, (lk+Jk) indicating the coordinates of a grid point is input, and the memory module number mb to which the grid point data belongs is calculated. At the same time, a data address ah within the module is created.

The calculation of mk is mh=(
(ib+jk/q)×q+(jh+L/p)//q)/
/(p×q). The above formula is mad p
It calculates q = mod 8, and this calculation does not require the lower 3 bits of ik, j and h.
The operations for division, multiplication, and remainder in the formula are based on p and q being powers of 2, so it may be necessary to shift the wiring or do it as appropriate.
This can be done by selecting . As a result, what needs to be explicitly calculated in the above equation is the addition part of (jk+ik/p)//q and the addition part of (i h+j k/q ) X q. These can be calculated by using two adders 311 and 312 as shown. The third addition in the formula can be obtained by simply arranging the above two addition results.

8 is a value giving the address of the data in the memory module, and is given to each memory module together with the input or output data Dk.

In this embodiment, it is assumed that the data arrangement within each memory module is as shown in FIG. That is, the screen is 1X
Divide into pq horizontally long blocks (corresponding to block shape t=θ). Due to the nature of module distribution, each block contains one of all P q==3 modules. Therefore, in each memory module, considering X shown in FIG. 8 as a new abscissa, the data of its own module contained in the R block is determined by coordinates (i, x) as determined by (i, x). store in memory.

According to this rule, as the intra-module address ak, iR is given to the module as is, and for jk, P
Just divide by q=3 and give it to the module. This division can be done by simply ignoring the lower 3 bits of jk.

Digital bidirectional crossbar switch FIG. 9 shows the function of the digital bidirectional crossbar switch. In this part, a set of data dht module internal address ak and module number mk (dh+
akt mk) 81'L, and connects dh and ah to the corresponding memory module according to the value of each ma+. An example of this is shown in FIG.

Since the method for implementing this function is well known, it will not be described in detail here.

The memory module is a part that stores actual data, and receives an internal module address ak from the crossbar switch and reads or writes data dk.

The address in the module ah and the entire screen! ff,?
The relationship between the marks (it J) is as shown in FIG.

The method for implementing this part is well known and will not be described in detail here.

As described above, in this embodiment, the method of the present invention is used for the address expansion section 2o and the module control units 30 to 37, and the bidirectional digital crossbar switch 40 and the memory module 50 are constructed using known techniques. Furthermore, by setting the parameters p and q to powers of 2, the effects of the present invention can be realized with a simple circuit.6 [Effects of the Invention] According to the present invention, (i) horizontally long area (11) on the screen Simultaneous access to vertically elongated areas (iii) regularly arranged rectangular areas is possible. Of these (i) (ii)
), it is possible to achieve the same function as the present invention with the conventional technology, but in (■), the present invention has a function that exceeds the conventional technology. Figure 10(a) shows the features of the present invention in (tit).
) to (c).

FIG. 10(a) shows one of the conventional techniques, JP56-
In 44449, the meaning of diagram 0, which shows the arrangement of rectangular areas that can be accessed in parallel, is that when the reference point of the rectangular area is one of the points marked with black circles in the diagram, parallel access is possible. show something

The reference point of the rectangular area is the upper left point of the area, specifically the point 1030 indicated by a black circle in FIG. 10(Q). However, an example where p=q=4 is shown here.

In contrast, in the present invention, the parallel accessible area is
The meaning of figure 0 arranged like figure 0 (b) is shown in figure 10 (
Same as a). As can be seen by comparing FIGS. 10(a) and 10(b), the present invention has the following effects.

That is, ■The number of areas that can be accessed in parallel is increasing.

(2) The areas that can be accessed in parallel are arranged symmetrically with respect to the ordinate i and the abscissa j.

A new effect arises. Among these, the effect (2) produces a property that the horizontal coordinate and the vertical coordinate can be treated equally when performing operations such as transposing and rotating the screen, and realizes a new function not found in the prior art.

[Brief explanation of drawings]

Figure 1 shows the pixel distribution rule of the present invention with design parameters p=
4, q=2 is shown as an example. FIG. 2 shows the shape of an area that can be accessed in parallel. FIG. 3 shows a schematic configuration of a memory for parallel access, and FIG. 4 shows a conventional system in comparison with FIG. 1. 5 to 9 show the configuration necessary for implementing the present invention, and FIG. 10 shows the differences between the present invention and the conventional system. DESCRIPTION OF SYMBOLS 1... Pixel, 3... Screen, 20... Address development part, 30-37... Module control unit, 311
~312...Adder. Figure 1 J - Z Figure 3 Log 4 Figure 5 L
J Fig. 6 (Figure (b) showing ＾jiτ %)
ν β Be 箭 Otsu z(t) Tree L (~Otsu+l shown in 832. 1 color die) Tsukasa C9f book Empty jWlxρΣshow T・ 100 7 Figure B q Unillustrated/ρ m(c Ji

Claims (1)

[Scope of Claims] A memory system that stores data arranged in a one- and two-dimensional orthogonal grid, the memory system consisting of p×q memory modules with p and q as design parameters, and each module can be accessed in parallel, the data of the grid point indicated by the position coordinates (i, j) is expressed as M (i, j) = ((i + j / q) × q + (j + i / p)
//q) //(p×q) However, / and // indicate the quotient and remainder when divided by an integer, respectively. A memory system for two-dimensional information processing characterized by storing data in the M(i, j)th memory module given by .