JPS60132A - Data transmission circuit - Google Patents

Abstract

PURPOSE:To transmit data with high efficiency by synthesizing selectively the data and clock signals with a time division mutiple access signal to transmit then, and reproducing the signal at the reception side to divide it into a data signal and a time division multiple access switch control signal for outputting. CONSTITUTION:The data signal, the time division multiple access TDMA signal and the clock signal are supplied to terminals 1, 2 and 3 respectively of the transmission part. The data and clock signals extracted selectively at the output sides of gate circuits G1 and G2 and added together by a synthesizing circuit A. Then the data signal is correctly inserted to the part where no clock signal is contained. While the signal received from a terminal 5 of the reception part and supplied to signal reproducing circuits F1 and F2 and the signal shifted by half are reproduced and applied to a data reproducing circuit G3 and a TDMA switch control signal generating circuit G4. Then the data signal and the TDMA switch control signal are extracted out of terminals 7 and 8 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data transmission circuit, and in particular to a time division multiple access (time division multiple access) circuit.
This relates to a data transmission circuit in a TDMA (abbreviated as TDMA) communication system.

fbl Conventional technology and problems In TDMA communication, multiple stations use repeaters in a time-sharing manner, so the signals transmitted from each station are bursts and 11=J''
Although the signal is periodically intermittent, the transmitting position must always maintain a constant time relationship with respect to some time reference so that it does not intersect with burst signals transmitted from other stations on the repeater. It is controlled by a TDMA switch control signal.

The TDMA communication method has been used in the field of satellite communication for some time. - For example, a small wireless device and an antenna are installed on the roof of a building, and a TDMA control device is installed indoors, and a track connects the two. Then, three signals must be sent to the wireless device: a data signal, a clock signal, and a TDMA switch control signal corresponding to the burst signal.
There are different types of lines, and the length of the line that transmits these signals depends on the installation location of this TDMA control device, but if it is installed on the first floor of a building, it will be approximately the same length as the height of the building, for example several The line is 100 meters long, and requires three lines for each of the three types of signals and, depending on the case, metal pipes to accommodate them. Furthermore, when the line becomes long, matching circuits, line equalizers, etc. are required between the line and on-line equipment, which complicates the system configuration, which raises the cost and reduces reliability. .

fC) Purpose of the Invention The present invention has been made in view of the problems of the prior art described above, and provides a data system that improves the reliability of the system, reduces the cost of the system, and allows efficient data transmission. The purpose is to provide transmission circuits.

(d) Structure of the Invention The object of the invention is to provide means for selectively extracting a data signal in response to a TDMA switch control signal, means for selectively blocking a clock signal in accordance with the TDMA switch control signal; a data transmission circuit transmitter comprising means for synthesizing a single data signal obtained from the signal blocking means and a clock signal obtained from the signal blocking means; a means for dividing the received baseband signal into two; and a means for dividing the received baseband signal into two; a first signal reproducing means for reproducing the first baseband signal obtained from the means; a second signal reproducing means for reproducing the second baseband signal after delaying the second baseband signal by half a bit; first and second means for extracting a data signal and a TDMA switch control signal from signals obtained from the first and second signal reproducing means;
a data transmission circuit receiving section comprising a signal extracting means, and a reproducing means for reproducing a clock signal extracted from the baseband signal and supplying the clock signal to the first and second signal reproducing means. This is achieved by providing a data transmission circuit characterized by the following configuration.

(0) Embodiment of the invention Figure 1 is a block connection diagram of an embodiment of the invention.
al indicates a data transmission circuit transmitting section, and (in Fig. 1) indicates a data transmission circuit receiving section.

In the same figure, c, G2. are each gate circuit G
, is a data recovery circuit, G is a TDMA switch control signal recovery circuit, A is a synthesis circuit, S is a half bit shifter,
1 and 2 are signal reproducing circuits, C is a black reproducing circuit, and 1 to 8 are terminals, respectively.

Each of these blocks is connected as follows.

Regarding the data transmission circuit transmitting section shown in FIG.
The output terminal to the 1 synthesis circuit is connected to the input terminals 1) and (2) to the terminal 4, and the terminal 2 is connected to the input terminal (2) of the gate circuits Gl and G2, respectively.

Regarding the data transmission circuit receiving section shown in FIG.
They are respectively connected to the (1) input terminals of the TDMA switch control signal reproducing circuit q. In addition, the input terminal of the signal reproduction amount IIF is terminal 5, and the output terminal is the data reproduction "1 path G3.
and the input terminal (2) of the TDMA switch control signal reproducing circuit G. The output terminals of the data reproducing circuit G3 and the TDMA switch control signal reproducing circuit C11 are connected to terminals 7 and 8, respectively. On the other hand, the terminal 6 is connected to the signal reproducing circuit via the clock reproducing circuit C and to the two input terminals, respectively.

FIG. 2 is a diagram for explaining the operation of the data transmission circuit transmitting section and the data transmission circuit receiving section shown in FIG. 1. ■, ■, etc. shown on the left side of FIG. The operation of the part with the same symbol as shown in is shown. Now, the operation of the first [ffl] will be explained with reference to FIG.

First, the operation of the data transmission circuit transmitting section shown in FIG. 1 (al) is as follows.

A data signal is applied to terminal l, a TONA switch control signal is applied to @child 2, and a clock signal is applied to terminal 3.
(See ■, ■ in Figure 2).

Then °ζTDM^ Switch control signal to gate circuit [2&G
,.

G2 operates as follows. That is, when gate circuit G1 is ON, gate circuit G2 is OFF, and when G1 is OFF, G2 is ON. Therefore, the data signal applied to terminal 1 is applied to gate circuit G while gate circuit G1 is 0.11.
Since the data signal is taken out to the output terminal 1 and not taken out while the gate circuit G is OFF, a burst data signal is obtained (see FIG. 2).

On the other hand, since the clock signal applied to the terminal 3 causes the gate circuits G1 and 02 to operate alternately as described above, the clock signal is not taken out at the time when the data signal is taken out from the gate (Fig. reference).

Therefore, the data signal and clock signal taken out to the output side of the two gate circuits G and Gi are added to the synthesis circuit, and the data signal is inserted into the part G where the clock signal is not included. (See Figure 2 ■).

In this way, three types of signals, the clock signal, the TDMA switch control signal, and the data signal, are converted into serial signals.

Next, such a signal is sent to the other station, but the receiving station receives data 4. The original signal must be extracted from the received signal in the faulty circuit receiver.

The data transmission circuit receiving section shown in FIG. 1(b) is a circuit for extracting the original signal, and the operation of this circuit will be explained with reference to FIG. 2 and subsequent figures.

The received signal taken out at terminal 5 is the same as the signal sent from terminal 4 of the data transmission circuit transmitting section. This received signal is then divided into two parts, one of which is applied to a half-bit shifter 81, and the other part of which is applied to a signal reproducing circuit consisting of a flip-flop circuit (see FIG. 2).

The received signal applied to the one-and-a-half bit shifter S is delayed by half a bit by the delay circuit included therein, and then sent to the output terminal Y-
After being taken out to the signal reproducing circuit etc. (second
(See figure ■).

On the other hand, a clock signal extracted by passing the received signal through, for example, a PLL (Phase Lock Loop) circuit is applied to the two signal reproducing circuits and h from a terminal 6 via a clock quaternary circuit C (second (See figure ■)
.

Therefore, in order to separate the data signal and TDMA switch control signal from the received signal, the half-focus-shifted received signal, and the clock signal, the following method is used.

That is, as shown in the time chart of FIG. 2, the received signal shown in FIG. 2 (■) and the half-focus-shifted received signal shown in FIG. Judgment is made as follows from the level values of the two signals obtained by sampling at the rising point.

Signal combination judgment ■Value ■Value ■Data signal Control signal 1 0 0 1 o 1 0 1 1 1 1 0 o o o o.

That is, when the combination of ■ and ■ is 10 or 010, the data signal is assumed to be 0 and the TDMA switch control signal is assumed to be 1. When the combination is 11 or 000, the data signal is 1 or 0, TDM
The A switch control signal is assumed to be 0.

Signal regeneration circuit F3. shown in FIG. 1tb+. & and data P raw circuit G, TDM eight stitch control signal regeneration circuit G is a circuit for implementing the above method, and the signal regeneration circuit and the received signal added to 1%, half bit. After each shifted received 4R signal is reproduced, the data reproduction amount VF
r G, and T[1M/l switch control signal control body circuit G
, where the data signal and TDMA switch control signal are separated, and the data signal is sent to terminal 7 and the TI signal is sent to terminal 8.
IMA switch control signals are respectively taken out (second
(See Figure ■, [Phase]). FIG. 3 shows another practical example of the present invention.
Instead of shifting the received signal by half pino 1-, shift the clock signal by half pino while leaving the received signal as is.

Half-bit shifter S is shown in FIG. 1 (from the block diagram of BL).

is removed, and a half-pin S2 is inserted between the terminal 6 and the signal reproducing circuit F2. However, it goes without saying that the operation of the receiving section is exactly the same as that shown in FIG. 1 fbl.

ffl Effects of the Invention As explained in 2, according to the present invention, three types of digital signals can be arranged and transmitted in chronological order, so data transmission can be carried out efficiently, and The system configuration is easy and the price can be kept low.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of FIG. 1, and FIG. 3 shows another embodiment of the present invention. In the figure, G, G2. are respectively gate circuits, G3 is a data regeneration circuit, G and F are TDMA switch control signal regeneration circuits, A is a synthesis circuit, S, s are half-bit thick"-, F, , F2 are the signal regeneration times 1/i't, C is the clock regeneration circuit, and 1 to 18 are each 1 degree rotation: 1 child.

Claims (1)

[Claims] means for selectively extracting a data signal to T[1M in response to a switch control signal; means for selectively blocking a clock signal in accordance with the TDM switch control signal; a data transmission circuit transmitter comprising a means for combining the clock signal obtained from the signal blocking means, a means for dividing the received baseband signal into two, and a first baseband signal obtained from the two-half dividing means. a first signal reproducing means for reproducing a second baseband signal after delaying the second baseband signal by half a focus; first and second signal extracting means for extracting a data signal and a TD old switch control signal from the signal; 1. A data transmission circuit comprising: a data transmission circuit receiving section comprising clock regeneration means for supplying a signal;