JPS60132363A - Ccd linear sensor - Google Patents

Abstract

PURPOSE:To reduce the number of output circuits, the power consumption and the area of a chip in a CCD linear sensor by producing a compensation signal from the output circuits not used as the normal output of separating and combining output circuits. CONSTITUTION:When a CCD linear sensor is used in a separation output system, photoelectric conversion signal components S from odd and even number picture element groups are contained in addition to DC offset components and reset noise components in the output signals of output circuits 40, 50 for CH1, CH2. On the other hand, only the DC offset components and the reset noise components are contained in the output signals of a composite output circuit 30. Accordingly, it is constructed that the both components become equal to one another, thereby using the output signal of the circuit 30 as a compensating signal.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a COD imaging device using a COD (charge coupling-i8 device). The present invention relates to a CCD linear sensor in which transferred charges are taken out from two formed COD registers by combining or separating charges.

[Technical background of the invention]

Recently, the number of pixels has been increased to increase the reading density of CCD linear sensors, and the number of pixels is increasing to about 5,000 pixels. With the increase in the number of pixels, there is a need to increase the rate of single-pixel scanning.For example, in order to read out 2,500 pixels and read out 5,000 pixels in the same main interpolation period, it is necessary to read out 5,000 pixels. You have to double your payout rate. So, fast! 7. As a means of achieving t right breast, COD registers are placed along both sides of the pixel rows arranged in a transverse manner, respectively. The signals of the odd-numbered pixels and the even-numbered iJ! of the pixel rows are formed in advance. l! Tochizo's has a separate output method in which the signals of the I ligation group are sent to the above-mentioned CCI registers on both sides separately, and all the signals of these two COD registers are taken out separately from each other. An addendum to the separation/synthesis switching method has been proposed that can switch to a composite output method in which the signals of the two COD registers are combined to output jt/p and bt.

The basic configuration of this separation/synthesis switching type CCD IJ near sensor is shown in Figure 1, where 1 is a pixel column in which photodiodes (pixels) are arranged linearly, and 2l is a pixel column on one side of the pixel column 1. A first channel CM provided adjacent to each odd-numbered pixel.

22 is a charge storage section for the younger 2-channel CH provided adjacent to each even'th pixel on the other side of the pixel row 1; 31 and 32 are charge storage sections on the upper side; C for discharging 22 charges at the same time.
Shift gate for H, and shift gate for CH, 4□
and 4 are the above shift games }J, , ? From 2' charges are transferred in parallel, and the C for CH1 transfers them in series.
CD register and CCD register for CI{,.

These two COD registers 4I, 4□ transfer charges in the same direction, and separate output gates 51e52 are formed adjacent to each other at the tips in the charge transfer direction, as well as synthesis input gates 61, 4□. 6□ is formed in contact with W4. Then, the separation output gate 51
, 5.

An output output circuit 7□ for CH1 and CH converts the amount of charge transferred into a voltage signal adjacent to the output circuit 7□ and CH.

A charge synthesis section 8 is formed adjacent to the synthesis input gates 6□ and 62, and a synthesis output gate 9 is formed adjacent to the charge synthesis section 8.
is formed, and the charge /
A composite output circuit 10 for voltage conversion is formed.

CCD using the above separation/melon printing method! 7CCD linear sensor is ti! The charges photoelectrically converted in the first pixel group in the odd column of iI series 1 are stored in the charge storage unit 2 for the corresponding CH. By opening the CH1 shift gate sXt, 1L of the accumulated charge r, (1L is transferred to the CH1 CCD register 41. At the same time, by opening the CH2 shift gate 32, the CH1 charge storage unit 22 The charge obtained by photoelectric conversion of the even-numbered j[IIl group stored in
H, read to the CCD register 42. When reading by the separate output method, a separate output gate 5,
.

5. Open the meeting and drive the CCD registers 48, 4□ at high speed with the synthesis input gate 61 t62 closed. On the other hand, when reading by the composite output method, the composite input gate 6! , open 6°, separate output gate 5□
, CCD shift register'! with 52 closed. t'
tk Drive at low speed.

Incidentally, the output signal of a CCD linear sensor is generally an analog signal with a waveform as shown in FIG.
In addition to the conversion signal Danger S, it also includes a DC offset signal (JIE).

Therefore, when processing the output of the CCD linear sensor (a"yk), in order to improve the S/N of this output signal, the upstream offset component DC and reset noise component Np are added to the output signal shown in Figure 2. It is a good idea to remove it.

That is, for example, DC offset component DC-5V, reset noise component N R = 0.57. Regarding the output signal of photoelectric conversion signal component S -0.5V, the signal fraction 5y5
If you simply use an amplifier with a gain of 10 times, the output amplitude will be DC offset component 50V + reset noise 1 minute 5V + signal fraction 5V -
The voltage is 60V, and as a power source for the amplifier, a voltage higher than the output amplitude is required as a matter of course.

In this way, 60V is required to obtain an output signal of signal component 5■.
A larger power supply is required, resulting in poor efficiency. To avoid such a situation, it is desirable to remove the direct current offset component DC and the reset noise component NRk from the input signal of the amplifier. For that purpose, the above DC
・A l1ij rectifier signal output circuit is provided on the same tick as the CCD linear sensor to output the output signal d (compensation signal) for the gods and Buddha, which consists of the offset portion DC and the reset noise component NR and the same amount. , jifJ, a normal output signal consisting of a direct current offset portion DC, a reset noise component NR signal portion S, and the above compensation signal are differentially amplified by a fully differential amplifier. That is, the first
In the CCD linear sensor shown in the figure, 11.12 and 1
3 correspond to the output circuits 71 and 7 for separate output.
．． and a compensation signal output circuit provided for compensating the output signal of the composite output circuit 1O.

[Problems with background technology]

However, in the CCD linear sensor of FIG. 1, there are three output paths 7! for normal output signals. .

7! ,,10 and three compensation signal output circuits 11, 12゜1
3, a total of six output circuits must be formed on the same chip, resulting in disadvantages such as an increase in power consumption, an increase in the tip area, and an increase in the number of output terminals. Moreover, even though such a large number of output circuits are provided, it is not possible to simultaneously select a combined output method and a separate output method, and it is not possible to select one output method or the other at the same time. It is designed by
There is a waste of unused circuits existing among the output circuits of 1.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and has a small number of output circuits, low power consumption, and a large chip surface.

It is possible to reduce the number of output terminals, reduce the number of unused and wasted output circuits, and simplify the number of beats.
CD! jCCD linear sensor.

[Summary of the invention]

That is, in the CCD linear sensor of the present invention, separation output circuits are provided corresponding to the first channel and the second channel, and a comparison output circuit is also provided at the bottom of the stack. Of each output circuit, the output (i12
The circuit (1' corresponds to a composite output circuit when a separation output method is adopted, and 2A corresponds to at least the output of the 1 separation output circuit when a composite output method is adopted.

), a signal for Shintoism and Buddhism including an iFi-style offset of 7 minutes is extracted from k th m.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Compared to the CCD linear sensor described above with reference to FIG. 1, the CCD linear sensor shown in FIG. 3 omits three compensation signal output circuits (11° 12.1 s in FIG. 1),
An output circuit that is not used for normal output (this example assumes use in a separate output method, so it corresponds to the composite output circuit 3O for composite output)' is used as a compensation signal output circuit. They are different in that they are different, but the rest are the same, so the same reference numerals are given and the explanation will be omitted.

The composite output circuit 3O includes a charge detection section (for example, a floating diffusion region) 31 formed adjacent to the composite output gate 9, and a reset circuit formed near the center direction detection section 3. The drain region 32, the reset gate 33 formed between the charge detection section 3 and the reset drain head mount 32, and the voltage output section (for example, a MOS FET ID source follower circuit) 34. Also, CH.

The output circuit 40 includes a charge storage section 4 formed adjacent to the CH and separation output gate 5□, a charge detection section 42 formed near the charge storage section 4, and the above-mentioned charge storage section 4. : a pariah gate 43 formed between the charge accumulation section 41 and the charge detection section 42; a reset drain region 44 formed near the self-charge detection section 42; It consists of a reset gate 45 formed between the region 44 and a voltage output section 46 that detects the potential of the front charge detection section 42. Similarly, output circuit Ik for CH,
Reference numeral 650 includes a gun cargo horizontal portion 5 formed in contact with the CHt separation output gate 52, and a charge detection portion 52;
It consists of a pariah gate 53, a reset drain fi11'1 region 54, a reset gate 55, and a voltage output section 56.

FIG. 4 shows a part of the voltage applied to the above-mentioned on-state CCU') near sensor, and shows the driving shaft pulses φ1 and φ2 for starting the COD register 41+'2 by, for example, a two-phase drive system, and The reset pulse R8 applied to the reset gates 33, 45.55, the gate operation signal G1 applied to the gate 5□ for CH and separation output, and the gate 5. Gate switching signal G2 applied to
Signal G. says the grape. Note that since this embodiment shows use in a separate output method, the separate output gate 5I
Gate switching signal G1FG to alternately open p52
2 are alternately set to high level (for example, 12), and gate switching signal +5GO is constantly set to low level (Ov) in order to keep the synthesis input gate 6116* closed. Furthermore, the pariah gates 43, 53 in the output circuits 40, 50 for isolation have their respective gate electrodes supplied with a constant DC potential, and provide a predetermined potential barrier to the voltage transfer path under the gate electrodes. In addition, each output circuit 30, 40, 5
0. The reset drain regions 32, 44, and 54 are each given a constant flux (M).

Next, the operation of the CCD linear sensor will be explained. Each time the reset pulse R8 becomes high level, the reset gate 33°45.55 opens in each output circuit, so the charge detection parts 31, 42°52 are connected to the reset drain regions 32, 4.
It is reset to the same potential as 4.54. Note that this reset potential corresponds to the DC offset (DC offset) in the output signal, and the potential change due to the amplitude induced component of the reset pulse R8 leaking into the charge detection section via the parasitic capacitance causes the reset potential in the output signal. This corresponds to the noise component NR. Then, each time the reset pulse R8 becomes low level and the reset gates 33, 45, 55 are closed, the gate switching signal G□ or G sets the separation output gate 51 or 52, so that the CCD register 4. Or, the charge from 42 is injected into the charge detection section 42 or 52 via the charge storage section i1 or 5 and the pariah gate 43 or 53, and the charge detection section 42, 52 is injected according to the amount of the injected charge.
The potential of changes. Therefore, the output signal of the output circuit 40 for CHI includes the photoelectric conversion signal component S from the odd-numbered pixel group in addition to the DC offset component DC and reset noise component NR, and the output signal of the output circuit 5O for CH includes photoelectric conversion signal components S from even-numbered pixel groups in addition to the DC offset component DC and reset noise fraction NR. On the other hand, the gate switching signal G. gate 6 for synthetic input.

Since No. 6 is closed, only the output of the composite output circuit 30 (No. N includes the DC offset of the previous b pin), the H portion DC, and the reset noise portion NR are included.

Once, the DC offset component DC and the reset noise component NR included in the output signal of the composite output circuit 3O were respectively added to the DC offset component DC and the reset noise component NR included in the output signal of the separation output circuit 40゜5Q. By multiplying the number of wheels so that they are equal, the output signal of the composite output circuit 30 can be used as a signal for compensating the spirit. Alternatively, the composite output circuit 30 can be used as a compensation signal output circuit.

In addition, when using the above CCD linear sensor in a composite output method, a part of the applied pressure caused by the fourth factor is changed to separate output gate 5. and 52 are closed, and the synthesis input game F6. It is only necessary to open r6t'l', and for this purpose, the gate switching signals Gl, G are always kept at low level, and the gate switching signal G. ? ! - Always keep it at a high level.

In this case, the separation output circuits 40 and 50 can each be used as compensation signal output circuits, but it is sufficient to use only some of them.

In addition, in all of the above embodiments, a DC offset component and a reset noise component are obtained as compensation signals, but for formulations where the reset noise fraction is small, it is possible to obtain a certain degree of compensation effect by obtaining only the blood flow offset component. For this purpose, it is sufficient to apply the same DC potential as the high level of the reset pulse to the reset gate electrode of the output circuit for i-1: compensation signal output.

〔Effect of the invention〕

As described above, according to the CCD linear sensor of the present invention,
Since the number of output circuits (3 Ihr) is small and the capture is simple, it is possible to reduce power consumption, chip area, and number of output terminals. Moreover, in the case of the separate output method, all three output circuits are used, and in the case of the combined output method, at least two output circuits are used, so some of the three output circuits are not used and are wasted. Only one or zero circuits are required, which is wasteful or less than the conventional three circuits.

[Brief explanation of drawings]

Stripe 1 is the conventional COD! 2 is a waveform diagram showing an example of the output signal of the sensor shown in FIG. FIG. 4 is a waveform diagram showing a part of the applied voltage when the sensor shown in FIG. 3 is used in a separate output method. 1... Pixel column y41t'□... CCD register, 5
1. 5m...1 separate output gate, 6I, 62...
・Synthesis input gate, 8...5 pieces of storage, 9...
Synthesis output gate, 3O...Synthesis output circuit, 40.5
0... Separation output circuit, 31, 42. 52... Charge detection section, 32, 44, 54... Reset drain region,
34.46.56...Pa city pressure output section.

Claims (3)

[Claims] (1) Two CCD registers, which are provided along both sides of a linearly arranged pixel column, each read out signal charges of a predetermined pixel group in the pixel column in parallel and transfer them to the pixel column; 11! corresponding to the leading edge of the CCD register in the charge transfer direction. A separation output gate for the first channel and a separation output gate for the second channel are provided adjacent to each other, and a charge voltage conversion gate is provided adjacent to the separation output gate for each channel. an output circuit for the first channel and an output circuit for the second channel, a synthesis input gate provided adjacent to the tip end portions of the two CCD registers in the charge transfer direction, and a synthesis input gate adjacent to the synthesis input gate. A charge combining section provided in the charge combining section, a combining output gate provided adjacent to the charge combining section, and a combining output circuit provided adjacent to the combining output gate for performing charge-voltage conversion. ,
Each of the above outputs 1f! A CCD linear sensor characterized in that the entire compensation f6 including a direct current offset signal is taken out from an output circuit which is not used for generating a normal output signal among the circuits. (2) Each of the output circuits includes a charge detection section into which input charges are injected, a reset gate provided at this charge detection section, and a reset drain region provided adjacent to the reset gate. , and a voltage output section that generates an output voltage according to the potential of the charge detection section. (3) A constant reset level is applied to the reset drain region, and a reset pulse is applied to the reset gate electrode of the output circuit for each channel before charge is injected into the mJ charge detection section; A single voltage potential or the above-mentioned reset pulse is applied to the reset gate electrode of the composite output circuit, the two separation output gates are controlled to open alternately at a constant cycle, and the composite output gate is always closed. A CCD linear sensor as set forth in Section Illg of the patent, characterized in that the CCD linear sensor is controlled by: 6) A constant reset potential is applied to the reset drain region of the composite output circuit and the output circuit for at least one channel, and a reset potential of the reset gate of the composite output circuit is applied to the reset drain region of the composite output circuit and the output circuit for at least one channel. A reset pulse is applied before, a constant potential or the above-mentioned reset pulse is applied to the reset gate electrode of the output circuit for one channel, and the two synthesis input gates and the synthesis output gate are connected to the output circuit. The CCD linear sensor according to the above-mentioned % tolerance request range item 2 d, characterized in that the two separation output gates are controlled to be opened and the two separation output gates are always closed.