JPS60130917A - Mos semiconductor delay circuit - Google Patents

Abstract

PURPOSE:To make the leading and trailing time of an output signal coincident with each other accurately by forming depletion transistors (TRs) with the same channel length and channel width. CONSTITUTION:An input terminal 21 is connected to a gate of an enhancement MOSTR22. A drain of the enhancement MOSTR22 is connected to a source of a depletion MOSTR23. The source and gate of the TR23 are connected in common to the source and gate of a depletion MOSTR24. The depletion MOSTRs 23, 24 have the same channel length L and channel width and the identical characteristic.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an MO8 type semiconductor delay circuit, which is a circuit that delays a signal without changing the duty ratio of an input signal, and which is suitable for use in edge detection circuits, triangular wave generation circuits, etc. Used for etc.

[Technical background of the invention]

As shown in FIG. 1, the delay circuit includes an inverter 12,
There is one using a resistor 13 and a capacitor 14. The delay time of this circuit is determined by a time constant determined by the resistor 13 and capacitor 14.

The input signal given to the input terminal 11 is sent to the inverter 12
The signal is inverted at , delayed and applied to the output terminal 15 . FIG. 2 shows an example of such a delay circuit constructed from an MO8 type semiconductor. The input signal is input to the enhancement type MO8) transistor 17 as a drive transistor. As a load for this transistor 17, a deresolution type MO8) lunge or star 16 is used. A capacitor 18 is provided between the source electrode of this transistor 16 and the ground potential. In this semiconductor circuit, the effect corresponding to the resistor 13 can be obtained by selecting the channel width and channel length of the transistors 16 and 17.

[Problems with background technology]

In the semiconductor delay circuit described above, even if a rectangular wave signal with zero rise and fall times is input, it is difficult to match the rise and fall times of the output signals. This is due to the following reason.

Since the transistors 16 and 17 are different types of transistors, there are variations in the manufacturing process between them. Therefore, the on-resistance ratio of the transistor 16.11, the resistance of the transistor 16 when the transistor 16 is on, the transistor 17 is off and the capacitor 18 is charged, and the resistance of the transistor 16 when the transistor 16, 17 is on and the capacitor ' It is difficult to make the ratio between the resistance of the transistor 17 and the resistance of the transistor 17 when the discharge of the transistor 18 is performed to a desired ratio.

Further, since the transistors 16 and 17 have different temperature values, there is also a problem that they lack reliability against temperature changes.

As mentioned above, in conventional semiconductor delay circuits, it is difficult to precisely match the rise and fall times of signals, and it is required to accurately transmit the duty ratio. It is desired that such problems be solved in circuits such as these.

In addition, as a semiconductor delay circuit, Japanese Patent Application Laid-Open No. 50-142128
There is a technology described in the publication. This technology is
The focus is only on connecting a capacitive element to the output electrode of a John-type field effect element.

In other words, a degradation type field effect element is provided as a control element for charging and discharging charge to a capacitive element, and the difference in conductance during charging and discharging of this depletion type field effect element is used to control the rise of the output signal. , the difference in the falling time is made larger.

To explain further, a. This technology is desolation type 1! This circuit includes a field effect element as a control element for charging and discharging charge to a capacitive element.

b. The purpose is to use the difference in conductance during charging and discharging of this depletion type field effect element to increase the difference in the rise time and fall time of the output signal, and the purpose is different from the present invention. It is something that

c. The technology described in Sho 50-142128 does not consider the shape of the inverter connected to the control circuit to be a problem, but the present invention concerns the shape of the inverter and the shape of the control element. becomes important.

That is, the purpose is to make use of the difference in conductance in the charging time of the delusion transistor to increase the difference between 9 hours for the rise and 9 hours for the fall of the output signal.

[Purpose of the invention]

The present invention provides an MO8 type semiconductor delay circuit that can accurately match the rise and fall times of delayed output signals and can delay the input signal without changing its duty ratio. purpose.

[Summary of the invention]

In this invention, when the transistor 22 is turned on and the capacitor 25 is viewed from the transistor 22 side, the discharge charge of the capacitor 25 per unit time is calculated, and when the transistor 22 is turned off and the capacitor 25 is viewed from the side of the transistor 25, The depletion type transistors 23 and 24 are formed with the same channel length and channel width so that the charge amount per unit time for the capacitor 25 is equal, and the rising edge of the output signal and the channel width are the same.
The above object is achieved by precisely matching the falling and falling times.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, and the input terminal 2 is
Enhancement fiMO8) Connected to the dart electrode of the transistor 22. In this enhancement type MO8) transistor 22, the source electrode is connected to the ground potential, and the drain electrode is connected to the depletion type MO8) transistor 23.
connected to the source electrode of This depletion type transistor 23 has its drain electrode connected to the power supply.
Acts as a second load. Furthermore, depression type MO
8) The source electrode and dart electrode of transistor 23 are commonly connected to the source electrode and f-) electrode of depression type MO8) transistor 24. The drain electrode of this depletion g'ytoS) transistor 24 is connected to the ground potential terminal via a capacitor 25. Capacitor 25 is constructed by polysilicon diffusion or a polysilicon-polysilicon combination.

Enhancement fiMO8) Lannostar 2 mentioned above
2. Depression type MO8) transistors 23 and 24
, and the capacitor 25 forms a basic delay circuit.

Here, in the present invention, the depletion type MOS transistors 23 and 24 have the same channel length (L) and channel width (W), and have the same characteristics.

Next, the operation will be explained as follows.

That is, when the input terminal 21 becomes high level, the transistor 22 is turned on. The charge in the capacitor 25 is then discharged through the transistors 24 and 22. At this time,
The current 11 flowing through the transistor 24 is: lJ=β1(v081-vth)2 vGll,=0, so +1=β1v,h2. However, μm is the current amplification factor vG81 of the transistor 24, and vth is the threshold value of the transistor 24. In other words, in this case, the transistor 24 operates as a current source.

Next, when the input terminal 22 becomes low level, the transistor 22 is turned off. Therefore, the capacitor 25 is charged via the transistors 23 and 24. At this time, the current 12 flowing through the transistor 23 is 12=β2 (VG112 =vth) 2■. 82
-〇, so i2=β2vth2. However, β2 is the current amplification factor ■ of the transistor 23. 8□ is the dirt-source potential vth of the transistor 23.
Threshold W of the transistor 23 In this case, the transistor 23 operates as a current source, and the current flowing through the transistor 24 is controlled by the transistor 23.

Here, depression type MO8) transistor 23.2
4 satisfies the conditions that the channel length and channel width are the same and that they are the same type, so the capacity is 25
On the other hand, the charge i discharged per unit time during discharging is equal to the amount of charge charged per unit time during charging. This means that the rise time υ and the fall time υ of the output signal applied to the output terminal 26 are equal.

Fig. 4 shows two stages of the basic delay circuits as described above connected in series, transistors 31.35 are enhancers) WMO8)7 and transistors 32, 33.3.
Reference numerals 6 and 37 are depletion type MO8) transistors, and each stage has a capacitance of 34.38. The output is then led out to an output terminal 41 via an output circuit constituted by an enhancement type MOS transistor 39 and a depletion type transistor 40.

FIG. 5 shows the input signal (A) at the input terminal 30 of the circuit described above, the signals (B) and (C) at the nodes (mode) 42 and 43, and the output signal ((C) at the output terminal 41).
D) is shown.

Transistors 32, 33, 36, 37 of the above delay circuit
．． 40 are formed to have the same channel length and channel width, and the capacitances 34 and 38 are also formed to be the same.

Further, the transistors 31, 35, and 39 are also formed to have the same channel length and channel width.

Therefore, for a noculus-like input signal (A), the node 4
The signals (B) and (C) in 2.43 have equal rising and falling times (TW1='rW2). Furthermore, the inverter circuit made up of transistors 31 and 32, the inverter circuit made up of transistors J5 and 36, and the inverter circuit made up of transistor 39.4o have the same circuit threshold values (v, II, =vTII
2) Do.

As a result, when comparing the input signal (A) and the output signal (D), the time (tl) from the rising edge of the input signal (A) to the falling edge of the output signal (D) (tl) and the input signal The time (t2) from the falling edge of signal (A) to the rising edge of output signal (D) coincides, and the delay times of the leading and trailing edges of the tab coincide.

(tz=t2) Also, this does not matter if the threshold value of the inverter circuit changes, and when looking at the output signal (b), the overall delay time will change, but the input signal (A)
The duty ratio of is outputted as an output signal (D) without changing.

〔Effect of the invention〕

As described above, according to the present invention, the rise time and fall time of the delayed signal can be made the same υ time, and the MO8 type semiconductor delay can be delayed without changing the duty ratio of the input signal. The circuit can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional delay circuit, Fig. 2 is a circuit diagram showing a conventional semiconductor delay circuit, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a circuit diagram showing a conventional semiconductor delay circuit. A circuit diagram showing another embodiment of the invention, FIG. 5 is a signal waveform diagram of each part of the circuit of FIG. 4. 22.31, 35.39...Enannouncement type M
O8) Transistor, 23, 24, 32.3B. 36.31,40...Desolet; John type MO8) transistor, 2B, 34.38...Capacity.

Claims (3)

[Claims] (1) The dirt and source electrodes of the first depression type transistor are connected to the dirt and source electrodes of a second depression transistor having the same channel length and channel width as the depression type transistor, and the dirt and source electrodes of the first depression type transistor are A driving transistor having as a load and having an input signal applied to a dart electrode is connected between an inverter circuit formed as an enhancement transistor and a drain electrode of the second depletion transistor and a ground potential terminal. MO8 whose percentage is that it has at least the capacity
type semiconductor delay circuit. (2) A MO8 type semiconductor delay according to claim 1, characterized in that a plurality of circuits constituted by the first and M2 depletion type transistors, the enhancement type transistor, and the capacitor are connected in cascade. circuit. (3) A dirt electrode of an enhancement type transistor is further connected to the drain of the second depletion type transistor, and a third depletion type transistor having the same channel length and channel width as the second depletion type transistor serves as a load to this transistor. 2. The MO8 type semiconductor delay circuit according to claim 1, wherein the r-) and source electrodes of the transistor are connected, and the dart and source electrodes are connected to an output port.