JPS60130846A - Manufacture of bump electrode type semiconductor device - Google Patents

Manufacture of bump electrode type semiconductor device

Info

Publication number
JPS60130846A
JPS60130846A JP58239383A JP23938383A JPS60130846A JP S60130846 A JPS60130846 A JP S60130846A JP 58239383 A JP58239383 A JP 58239383A JP 23938383 A JP23938383 A JP 23938383A JP S60130846 A JPS60130846 A JP S60130846A
Authority
JP
Japan
Prior art keywords
layers
film
laminated
bump electrode
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58239383A
Other languages
Japanese (ja)
Inventor
Shoichi Inoue
正一 井上
Susumu Kimijima
君島 進
Mitsue Kikuchi
菊池 光江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58239383A priority Critical patent/JPS60130846A/en
Publication of JPS60130846A publication Critical patent/JPS60130846A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To form a bump electrode having high reliability by forming the pump electrode consisting of a low melting-point metal on laminated metallic films composed of Ti/Al/Ti while using the laminated metallic films as foundation metallic films and removing the laminated metallic films through etching by using an alkali group etchant. CONSTITUTION:An insulating film 23 with openings is formed on input sections 22 consisting of Al electrodes on a CCD substrate 21. A laminated film 24 in which a Ti film 241, an Al film 242 and a Ti film 243 are evaporated on the whole surface in succession is shaped. Cu films 25 as plating layers are formed at positions where bump electrodes are shaped through evaporation and patterning. A photo-resist 26 is formed according to a pattern, and Cu layers 27 and In layers 28 are shaped. The photo-resist 26 is removed, only foundation metallic layers just under laminated electrodes consisting of the Cu layers 27 and the In layers 28 are left while using the laminated electrodes as masks, and the laminated metallic films 24 except these layers 27, layers 28 and foundation metallic layers are removed gradually through etching by an alkali group etchant in succession.

Description

【発明の詳細な説明】 [花明の技11j分野] 本光明は、半導体基板上にオーミック接触された少数の
金属電極層の上にさらに低融点金属からなるハンプ電極
を形成してなる半導体装置の!Fl造方法に関する。
[Detailed description of the invention] [Field of technology 11j of Hanamei] This Komei is a semiconductor device in which a hump electrode made of a low melting point metal is further formed on a small number of metal electrode layers in ohmic contact on a semiconductor substrate. of! This invention relates to a Fl manufacturing method.

[発明の技術的背廚とその問題点] CODセンサは、像の明暗を2次元的に多数配列した光
検知素子で受け、これを時系列の電気信号に変換して取
り出す機能を備えた集積化センサとしてよく知られてい
る。従来は2次元の物理量を取り出すセンサは、このよ
うな光検知素子に限られていた。最近、メカ1〜ロニク
ス技術の発達により、光以外の物理量、例えば圧覚、触
覚等の信号を2次元的に検知する要求が増えはじめた。
[Technical backstory of the invention and its problems] A COD sensor is an integrated sensor that has the function of receiving the brightness and darkness of an image using a large number of two-dimensionally arranged photodetecting elements, converting this into a time-series electrical signal, and extracting it. It is well known as a sensor. Conventionally, sensors that extract two-dimensional physical quantities have been limited to such photodetecting elements. Recently, with the development of mechanical technology, the demand for two-dimensional detection of physical quantities other than light, such as pressure and tactile signals, has begun to increase.

これらの物理量を検出する素子としては、−例どして半
導体のピエゾ抵抗素子が利用される。例えば81基板に
拡散抵抗素子を2次元的に配列形成し、これに外部から
の応力が加わればその点°の抵抗値が変化して信号を得
ることができる。そしてこのような検知素子をCC,D
と一体化すれば、応力分布を検知してその電気信号処理
まで行う集積形センサが得られる。この場合、検知素子
基板とCOD基板を一体化するには、対応する複数の端
子電極を直接突き合わせて接続する、いわゆるバンプ電
(6偶j4か用りられる。
As an element for detecting these physical quantities, a semiconductor piezoresistive element is used, for example. For example, if diffused resistance elements are formed in a two-dimensional array on an 81 substrate and an external stress is applied to them, the resistance value at that point changes and a signal can be obtained. And such detection elements are CC, D
When integrated with the sensor, an integrated sensor can be obtained that detects stress distribution and processes its electrical signals. In this case, in order to integrate the sensing element substrate and the COD substrate, a so-called bump electrode (6/j4) is used in which a plurality of corresponding terminal electrodes are directly butted and connected.

第1図は従来のハンプ電極形CCDの製造工程例である
。まず(a’)に示すように、cc’om板11の板面
1は、バンブ電極を形成すべき入力部12(12a、1
21+、・・・)上に開口部を有する絶縁膜13を形成
する。図では省略したが、CCD暴(ff111には多
数の呵送ゲ−1・電極が配列形成されており、入力部1
2はA−C電極により形成され−(いる。この後(1+
 )に示すように、バリヤメタルとなるCr膜14を蒸
着し、更にメッキ用電(勇どなるC11躾15を蒸着づ
る。次に(C,)に示すJ、うにノア1 hレジスト1
6のパターンを形成し、選択メッキ法にJ:ツて00層
17(17a、17b。
FIG. 1 shows an example of the manufacturing process of a conventional hump electrode type CCD. First, as shown in (a'), the board surface 1 of the cc'om board 11 is connected to the input section 12 (12a, 1
21+, . . . ), an insulating film 13 having an opening is formed. Although not shown in the figure, a large number of feed gates 1 and electrodes are arranged in the CCD sensor (ff111), and the input section 1
2 is formed by the A-C electrodes. After this, (1+
As shown in ), a Cr film 14 serving as a barrier metal is deposited, and a plating resist (C11 resist 15) is deposited.Next, as shown in (C,), a Cr film 14 is deposited.
A pattern of 6 was formed, and J:Tsu00 layer 17 (17a, 17b) was formed using the selective plating method.

−) 、 HA イテI n層18 (18a 、18
b 、−>を形成4る。次に((1)に示すように、フ
第1−レジスト16を除去し、しかる後にCIJ膜15
とCr膜14を順次1ツヂングで除去して7 nバンブ
電極を形成覆る。
-), HA ite I n layer 18 (18a, 18
b , −> is formed 4. Next, as shown in (1), the first resist 16 is removed, and then the CIJ film 15 is removed.
Then, the Cr film 14 is removed one by one in order to form a 7n bump electrode.

このような従来法tこおいては、メッキ用電極であるC
1l膜15およびその下のバリヤメタルであるCr膜1
4を除去するエツチング;jlは、配糸のものが用いら
れるため、I n G 18がエツチング液によって侵
される。このため111層18が薄くなり、最悪の場合
はCLI層17が露出し、目的とするl nバンブ電極
の形成がなされない欠点がある。
In such a conventional method, the plating electrode C
1L film 15 and the Cr film 1 which is a barrier metal thereunder.
Etching to remove 4: Since jl is used with yarn, I n G 18 is attacked by the etching solution. As a result, the 111 layer 18 becomes thinner, and in the worst case, the CLI layer 17 is exposed, resulting in the disadvantage that the desired ln bump electrode cannot be formed.

[発明の目的] 本発明は、このような欠点を解消し、信頼性の高いバン
ブ電極の形成を可能とした半導体装置の製造方法を提供
するものである。
[Object of the Invention] The present invention provides a method for manufacturing a semiconductor device that eliminates these drawbacks and makes it possible to form highly reliable bump electrodes.

[発明の概要] 本発明は、バリヤメタルとしてTi、メッキ電−極用金
属としてA1を用いたTi/A1.’T−iの積層金属
膜を下地金属層として、この上に選択メッキ法により低
融点金属からなるバンブ電極を形成した後、アルカリ系
エッヂヤントを用いて上記積層金属膜をエツヂンク除去
するJ:うにしたことを特徴とする。
[Summary of the Invention] The present invention provides a Ti/A1. Using the laminated metal film of 'T-i as a base metal layer, a bump electrode made of a low melting point metal is formed on this by selective plating, and then the laminated metal film is removed by etching using an alkaline edger. It is characterized by what it did.

[発明の効果] 本発明によれば、バンブ電極がエッヂヤントにJこり浸
されることがなく、目的とするバンブ電極をもった4−
11,頼性の高い半導体装Iを19ることができる。
[Effects of the Invention] According to the present invention, the bump electrode is not immersed in the edgeant, and the 4-
11. A highly reliable semiconductor device I can be produced.

[発明の実1JI!例] 以F第2図を用いて本発明の一実施例を説明する。第2
図(a)は第1図(a )と同じであり、CCD基板2
1上のA、C電極からなる入力部22(22a 、22
b 、・・・)上に間口をもつ絶縁膜23を形成した状
態である。このII(b)に示すように、全面に7i膜
24t 、Af膜242、Ti膜243を順次蒸着した
積層膜24を形成する。
[Fruit of invention 1JI! Example] An example of the present invention will be described below using FIG. 2. Second
Figure (a) is the same as Figure 1 (a), and the CCD substrate 2
Input section 22 (22a, 22
b, . As shown in II(b), a laminated film 24 is formed by sequentially depositing a 7i film 24t, an Af film 242, and a Ti film 243 on the entire surface.

Ti llA241.243はバリヤメタルであり、Δ
、、e Ill 242はメッキ用電極である。次に(
C)に示乃ように、バンブ電極を立てる位置にメッキ下
地層どなるCIJ IFJ25 (25a 、 25b
 、−>を蒸着、パターニングにより形成する。この後
、((1)に示J−ようにフt l・レジスト26をパ
ターン形成し、選択メッキ法によりCl1127 (2
7a 。
TillA241.243 is a barrier metal, Δ
,,e Ill 242 is a plating electrode. next(
As shown in C), the plating base layer is placed at the position where the bump electrode is placed (25a, 25b).
, -> are formed by vapor deposition and patterning. After this, a pattern of the resist 26 is formed as shown in (1), and Cl1127 (2
7a.

271+ 、 ・) 、次いで[n lii!28 (
28a 、 281+ 。
271+, ・), then [n lii! 28 (
28a, 281+.

・・・)を形成する。011層27の形成は、基板を例
えば硫酸銅浴のCLIメッキ液中に浸しl°温にて、上
記AJl膜242を電極として、最初に逆メッキを数秒
間行なって清浄化し、しかる後に正常なCuメッキを所
定電流値で数十分間通電することにより行う。これによ
り数μIllの厚さの011層27が形成される。また
In1ffi28は、この半導体基板を例えばホウフッ
化浴のInメッキ液に浸し、所定の電流値で数十分間電
気メッキを行なうことによって数μmの厚さに形成され
る。次に(C)に示すように、フォトレジスト26を除
去し、Cu層27とln層28の積層電極をマスクとし
て直下の下地金属層のみを残して、それ以外の積層金属
膜24を順次アルカリ系エッヂトン1−ににリエッチン
グ除去していく。まずTi膜24:+(、j、例えばA
液どじて水1−eにエチレンジアミン四酢酸24g、ア
ンモニア水180ccからなるp)litの液と、B液
として過酸化水素とを用いて、A:r2:B液=2:1
の混合比のエツチング液で室温にて約1分前後エツチン
グして除去覆る。次にAffi膜242は、例えば水5
00CCに水酸化カリウム75gを充分解かしたpH1
1の液で約2分前後エッヂングして除去する。その際に
発熱するために流水で冷やり“。次のTi膜241は上
記Ti膜243ど同じエツチング液を用゛いて同じ要領
でエツチングし除去づる。
...) is formed. To form the 011 layer 27, the substrate is immersed in a CLI plating solution such as a copper sulfate bath at a temperature of 1°, and the AJL film 242 is used as an electrode to first perform reverse plating for several seconds to clean it, and then perform normal plating. Cu plating is performed by applying current at a predetermined current value for several tens of minutes. As a result, an 011 layer 27 having a thickness of several μIll is formed. The In1ffi 28 is formed to a thickness of several μm by immersing this semiconductor substrate in an In plating solution such as a borofluoride bath and performing electroplating at a predetermined current value for several tens of minutes. Next, as shown in (C), the photoresist 26 is removed, the laminated electrode of the Cu layer 27 and the ln layer 28 is used as a mask, and only the base metal layer immediately below is left, and the rest of the laminated metal film 24 is sequentially coated with alkali. The system edge 1- is etched and removed. First, the Ti film 24: +(, j, for example A
Using a p) lit solution consisting of water 1-e, 24 g of ethylenediaminetetraacetic acid, and 180 cc of ammonia water, and hydrogen peroxide as the B solution, A: r2: B solution = 2:1.
Remove and cover by etching for about 1 minute at room temperature with an etching solution with a mixing ratio of . Next, the Affi membrane 242 is coated with, for example, water 5
pH 1 obtained by thoroughly decomposing 75g of potassium hydroxide in 00CC
Remove by edging with solution 1 for about 2 minutes. At that time, it is cooled with running water to generate heat.The next Ti film 241 is etched and removed in the same manner as the above Ti film 243 using the same etching solution.

このように本実施例によれば、l nバンプ電極形成後
、下地積層金B膜をアルカリ系エッチャントて順次エツ
チングJることにより、バンブ電極を12Jことなくジ
Vストエツチングが可能となる。
As described above, according to this embodiment, after forming the ln bump electrode, the underlying laminated gold B film is sequentially etched using an alkaline etchant, thereby making it possible to perform di-V strip etching without removing the bump electrode by 12J.

J、た、上記の如くジITストエツチングが確実に可能
となることで、例えば、COD転送部の多数のポンディ
ングパッドにA!金属膜を用いてマスク設工1ち簡素化
できる利点が得られる。
In addition, by making it possible to reliably perform di-IT stretching as described above, for example, A! The advantage of using a metal film is that mask construction can be simplified.

本発明は上記実施例に限られない。例えばC,11層2
7はl nバンプ電極の補助金属層であり、これを省略
して直接l n層28をメッキして■ロ□バンプ電極を
形成することも可能である。またバンブ電極全屈層とし
ては、l nの他に、Sb、Bf。
The present invention is not limited to the above embodiments. For example, C, 11 layer 2
Reference numeral 7 denotes an auxiliary metal layer of the ln bump electrode, and it is also possible to omit this and directly plate the ln layer 28 to form the bump electrode. In addition to ln, Sb and Bf can be used as the bump electrode total bending layer.

pl+、Δu 、 3n 、 Zll等の低融点金属を
用いることができる。
Low melting point metals such as pl+, Δu, 3n, Zll can be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a )〜((1)は従来のCODのバンブ電極
形成方法の工程を示す断面図、第2図(a)〜(e)は
本発明の一実施例に係るCODバンプ電極形成方法の工
程を示す断面図である。 21 ・COD基板、22a 、22b 、22c −
・・入力部、23川絶縁膜、24・・・積層金属膜、2
41・・・Ti膜、242・・・A −e 1!、24
3・・・Ti膜、25a 、 25+) 、 ’;! 
5cmQu膜、26−・・フッ11−レジスト、27a
 、 27b 、 27cmC;u層、28a 、28
b 、2’8cmIn層。 出願人代理人 弁理士 鈴江武尽
FIGS. 1(a) to ((1) are cross-sectional views showing the steps of a conventional COD bump electrode formation method, and FIGS. 2(a) to (e) are COD bump electrode formation according to an embodiment of the present invention. It is a sectional view showing steps of the method. 21 COD substrates, 22a, 22b, 22c -
...Input section, 23 River insulating film, 24... Laminated metal film, 2
41...Ti film, 242...A-e 1! , 24
3...Ti film, 25a, 25+),';!
5cm Qu film, 26-...Flu 11-resist, 27a
, 27b, 27cmC; u layer, 28a, 28
b, 2′8 cmIn layer. Applicant's agent Patent attorney Takejin Suzue

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に、複数のバンブ電極形成領域でA−ミン
ク接触する下地金属膜を全面形成し、この下地金属膜上
に選択メッキ法により低融点金属からなる複数のバンブ
電極を形成した後、このハンプ電極をマスクどして前記
下地金属膜の不要部分を1ツヂング除去で−る半導体装
置の製造方法にJ3いて、前記下地金属膜としてT i
 /’A−(1/’ T iの積石金属膜を用い、この
積層金属膜のエツチングをアルカリ系エッチt・ントに
より行うようにしl3口とを特徴とJ−るバンブ電極形
半辱体装置の製jろ 方 )人 。
A base metal film is formed on the entire surface of the semiconductor substrate to make A-mink contact in a plurality of bump electrode formation regions, and a plurality of bump electrodes made of a low melting point metal are formed on this base metal film by selective plating. J3 is a method for manufacturing a semiconductor device in which an unnecessary portion of the base metal film is removed by removing a hump electrode as a mask, and Ti is used as the base metal film.
/'A-(1/' Ti stacked metal film is used, and this laminated metal film is etched with an alkaline etchant. The person who manufactured the device.
JP58239383A 1983-12-19 1983-12-19 Manufacture of bump electrode type semiconductor device Pending JPS60130846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58239383A JPS60130846A (en) 1983-12-19 1983-12-19 Manufacture of bump electrode type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58239383A JPS60130846A (en) 1983-12-19 1983-12-19 Manufacture of bump electrode type semiconductor device

Publications (1)

Publication Number Publication Date
JPS60130846A true JPS60130846A (en) 1985-07-12

Family

ID=17043965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58239383A Pending JPS60130846A (en) 1983-12-19 1983-12-19 Manufacture of bump electrode type semiconductor device

Country Status (1)

Country Link
JP (1) JPS60130846A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270253A (en) * 1986-01-27 1993-12-14 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device
US5608991A (en) * 1993-05-18 1997-03-11 Yamashita; Senji Flexible form member and method of forming through hole by means of the form member

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460557A (en) * 1977-10-24 1979-05-16 Hitachi Ltd Solder electrode forming method
JPS54160166A (en) * 1978-06-09 1979-12-18 Hitachi Ltd Electrode forming method for semiconductor device
JPS5524414A (en) * 1978-08-09 1980-02-21 Hitachi Ltd Electrode forming process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460557A (en) * 1977-10-24 1979-05-16 Hitachi Ltd Solder electrode forming method
JPS54160166A (en) * 1978-06-09 1979-12-18 Hitachi Ltd Electrode forming method for semiconductor device
JPS5524414A (en) * 1978-08-09 1980-02-21 Hitachi Ltd Electrode forming process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270253A (en) * 1986-01-27 1993-12-14 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device
US5608991A (en) * 1993-05-18 1997-03-11 Yamashita; Senji Flexible form member and method of forming through hole by means of the form member

Similar Documents

Publication Publication Date Title
KR940010510B1 (en) Fabricating method of semiconductor device
EP0405585B1 (en) A method of manufacturing a semiconductor device
US4040891A (en) Etching process utilizing the same positive photoresist layer for two etching steps
KR920009716B1 (en) Semiconductor device preparing for bump structue
JPH0415938A (en) Formation of contact hole
JPS60217646A (en) Manufacture of bump electrode type semiconductor device
US4362598A (en) Method of patterning a thick resist layer of polymeric plastic
JPS60130846A (en) Manufacture of bump electrode type semiconductor device
GB2059679A (en) Method of making composite bodies
US3783056A (en) Technique for the fabrication of an air isolated crossover
JPH0227711A (en) Manufacture of semiconductor device
JP2672557B2 (en) Method for manufacturing semiconductor device
JPH0789553B2 (en) Method for manufacturing bump electrode type semiconductor device
JPH01179345A (en) Manufacture of semiconductor device
JPH01122141A (en) Manufacture of bump electrode type substrate device
JPS59110169A (en) Manufacture of semiconductor device
JPH04102341A (en) Manufacture of tab tape
JPH0917679A (en) Manufacture of laminated coil
KR0147485B1 (en) Method of making a gate electrode for rom
JPS6028237A (en) Manufacture of semiconductor device
JPS6072249A (en) Manufacture of integrated circuit
JPH0494544A (en) Manufacture of integrated circuit
JPH02139934A (en) Manufacture of integrated circuit
JPS5933850A (en) Manufacture of semiconductor device
JPS605543A (en) Manufacture of semiconductor device