JPS60130218A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To decrease the frequency response time and also to make the titled synthesizer suitable for circuit integration by applying an output of a voltage controlled oscillator (VCO) to a low frequency to decrease the overall frequency division after the output is frequency-divided by a pre-stage frequency divider. CONSTITUTION:An output of the VCO11 is outputted to an output terminal 12 as a synthesizer output and also and frequency-divided into several MHz by a pre-stage frequency divider 22a at first in a variable frequency divider section 22. The frequency dividing output is subjected to frequency division by a mixer 22b using an output of a reference oscillator 16 as a local oscillation signal next to a frequency of several hundred kHz. After the signal is subject to M frequency-division by a main frequency divier 22c, the result is fed to a phase comparator 15, an error signal is fed back to the VCO11 via a loop filter 18 and a signal having a frequency equivalent to L times a radio frequency interval fch is obtained at the output terminal 12.

Description

[Detailed Description of the Invention] The present invention relates to a frequency synthesizer using a phase-locked loop (PLL), and in particular, in a frequency synthesizer using a direct frequency division method that is suitable for IC implementation, the present invention relates to a frequency synthesizer that uses a phase-locked loop (PLL). The purpose of this invention is to significantly shorten the response time compared to the conventional method.

<Prior art> Wireless communication, especially mobile communication (bow, 11
4. In order to make effective use of certain frequencies, multiple radios share a number of radio frequencies, and each radio selects one of these radio frequencies when necessary to send a radio signal. Multi-channel access methods are becoming more widespread. In this method, in order to provide each radio image with the function of cutting a large number of radio frequencies, from tens to thousands of channels, a frequency synthesizer is required to
There are various types of frequency synthesizers, but what is the difference between them?
The conditions are that it operates at a high 1^1 wave number of about GH2, has good frequency stability, and is easy to miniaturize, integrate into ICs, and simplify. In consideration of this, a direct frequency division type frequency synthesizer has been used in the past.The configuration of a pulse swallow type frequency synthesizer, which is a type of surface frequency division type, is shown in FIG.

In FIG. 1, the output from the voltage controlled oscillator (VCO) 11 is output to the output terminal 12 as a 7-noiseizer output, and at the same time is input to the variable frequency divider 13.
A signal is obtained by dividing the frequency of the synthesizer output by N using an integer ratio according to the 151 wave number set from the setting terminal 14. This N-divided output signal is the output signal of the phase comparator 15.
is applied to the input terminal of On the other hand, the second
The input of *11.1 is the base value obtained by dividing the output of the d standard profit and loss 16 by the fixed frequency divider 17. The frequency of this basic thread signal (phase comparison frequency) is selected to match the hot wire frequency interval fch of the wireless channel. Phase ratio iI5! The device 15 compares the phases of the two input signals and outputs the result as an error signal. This error signal is passed through the loop filter 18 to the VCOII as necessary.
is given as a control signal. As a result, V C011
-t1] A phase-locked loop (PLL loop) consisting of variational frequency divider 13 - phase comparator 15 - loop filter 18 - VCOII is constructed, and a signal with a frequency N times the frequency interval fch is output to the output terminal 12. can get. The total frequency division number N of the variable frequency division section 13 is set by the code band symbol inputted from the frequency setting terminal 14, and the configuration shown in FIG. 1 operates as a frequency synthesizer.

The variable branching section 13 will be explained using and X. vIIF band~
The synthesizer output of IG+(2 is 25 K t(z f
In order to divide the frequency with i8 degrees of phase comparison frequency agility, the frequency division number Nil''1 of the variable frequency dividing section 1513 is approximately tens of thousands.In order to obtain such a large frequency division number, the variable Branch part 1
3.

Preliminary input signal count M 1-17. A high-speed 1111 frequency divider that divides the frequency by degrees], 3a, and a prescaler 1.3
The output of a is further divided into a low power consumption main frequency divider 13b which divides the frequency by phase comparison frequency agility, and a counter 13c for use in the pre-frequency divider section j. Positional frequency divider 1
3a has two branch modes, and a control counter 13c.
When the output of the counter 13C for l1lr+lI is 0, the mode is ÷P mode, and when the output of the l1lr+lI counter 13C is 0, the mode is +(P+1). Furthermore, a programmable counter is used for the main frequency divider] and 3b, the frequency division number iVI of which can be arbitrarily set. The output of the control counter 13c is set to 1 when the output of the first 16th frequency divider is divided by A cycles, and is reset to O every time a division pulse is output from the main frequency divider 131. shall be carried out. 3. Make it ARM. At this time, the total frequency division number N of variable frequency division section] 3
is, N=A(P+1)+(M-A)・P=M-P0A (
It becomes 1,1. If the control counter 13c is also configured as a programmable counter so that A can take all values from 0 to °(P-1)t, then N can take the value of any natural number. However, by using the configuration of the pulse swirl system shown in FIG. 1, it is possible to perform a frequency division operation equivalent to a single p] variable frequency divider.

As mentioned above, all circuits other than the VCO and loop filter can be constructed using digital circuits (Nr) in the ten configurations shown in Fig. 1, making it suitable for IC implementation. Commercialization f' (-J+).

However, in this configuration, the Kb combined frequency division number N in 3 is as large as 1/ζ 1
) The loop gain of the LL loop is 1, on the other hand, 1]
Since the loop c and l trough times of the L loop are inversely proportional to the loose-cain, in the i configuration, when switching the frequency or turning on the power
1Hj.

The response time of the synthesizer is Ik<1.
．． The question Y4 is 9゜As a way to solve this problem, instead of using the i1] frequency divider 13a, use a migrater and convert the output of the frequency divider to a number /i H7, by converting the frequency θ to the degree One possible method is to reduce the overall frequency division ratio N by
Insert the same No. 71 for i′, ls, which is one core as in Fig. 1.
As shown in Figure 1, the synthesizer output is converted to a lower frequency by the mixer 19 using the output of the local oscillator signal multiplier 21, and is supplied to the main frequency divider (programmable counter) 13b.

According to this method, the pre-frequency divider can be omitted, so that the frequency division number at the input of the phase comparator 15 from the synthesizer output matches the division number M of the main frequency divider 13b, and as shown in FIG. The loop gain can be increased by significantly reducing the number of branched stations compared to what is shown.

On the other hand, in this mixdown method, the mixer 19V
As a local oscillator signal, an extremely stable and highly polished signal is required. However, in this configuration, the output of the reference oscillator 16 is multiplied by the local oscillator signal multiplier 21 to obtain the local oscillator signal for the mixer. However, from base “A, +11=
*The oscillation frequency of the device 16 is usually a number TVI) Iz~10
Since the local oscillation frequency of the mixer 19 is selected to be approximately MH7, the VHF band ~ i G is the same as the synthesizer output.
In order to obtain 117.4”-=degree, the local signal multiplier 2
A multiplication number of about 1 to about 100 is required.

Therefore, in the local oscillator signal multiplier 21, multiplier circuits 21a, 21b, and 21c are connected in series in multiple stages as shown in the figure, and band-pass filters 21d, 21e, and 21f for spurious removal are inserted on the output side of each stage, respectively. I feel safe. Therefore, the circuit scale of the local oscillator signal multiplier 21 becomes extremely small. Furthermore, the circuit included in the local oscillator signal multiplier 21 uses many coils, etc., so it requires a lot of money.
It is difficult to convert to IC. Therefore, a problem arises in that it becomes a hindrance to making the synthesizer more compact and more reliable.

<Summary of the Invention> In order to eliminate these drawbacks, the present invention: ■ divides the CO output using a prescaler and then converts the frequency to a lower frequency using a mixer to reduce the total frequency division number and reduce the frequency. By increasing the response time and using the output from the reference oscillator as a local oscillator signal, the circuit B1
This structure suppresses the increase in noise and makes it suitable for use with ICs.

<Embodiment> FIG. 3 (d) shows an embodiment of this invention, and parts corresponding to those in FIG. , a mixer 22b that frequency converts the output thereof, a main frequency divider 2.2.c that frequency divides the output of the mixer 22b, and a prescaler limit 1 counter that controls the prescaler 22a. 22d.

The main frequency divider 22C is a programmable frequency divider (dividing number M'
) is used, and the operation of the prescaler control counter 22d of the prescaler 22a1 (is the operation of the prescaler control counter 13C of the prescaler 16' divider 13a1 at the first [2+), respectively. The oscillation frequency of the standard oscillator 1G is twice the radio frequency interval fch,
It is assumed that there is one solip every several MH7.

In this configuration, when the output of 1'CVCOII is output to the output terminal 12 as a synthesizer output,
In the variable frequency dividing section 22, the frequency is divided into approximately aM H2 by the pre-frequency divider 22a, and the frequency of the frequency division is as follows:
Next, a mixer 2 which uses the output of the reference oscillator 16 as a local signal
21), the signal is frequency-converted into a signal with a low frequency of about several hundred K+-1Z. After this signal d is further divided by +VL' by the main frequency divider 22C, the phase comparator 15
A reference signal (frequency = fch) obtained by dividing the output of the random oscillator 16 by a frequency divider 17 is applied to the 20th input terminal of the phase comparator 15. The phase comparator 15 compares the phases of the two input signals and outputs the result as an error signal. This error signal is fed back to the VCO 1 through the loop filter 18. As a result, at the output terminal 12, the wireless station θ has a frequency L times the frequency fch at several intervals (i is added to the code number inputted from the frequency setting terminal 14). When the frequency division numbers M1 and A of the b1 unit 22c and the secondary side 1 counter 22d change, the frequency division numbers also change accordingly, so a frequency synthesizer is constructed by adding t to this A and h'v. With this configuration, the sink frequency division number can be made significantly smaller than in the case shown in FIG.

Synthesizer output frequency f3yN and radio frequency fc
Is the comparison with h equal to 7 in the case of Figure 1?
It can be expressed in two ways.

L=A・(P+1)+(M'+f(-A)・P=(M
'+K)P0A(2) In order to obtain the same output frequency fsYN as in the case of FIG. 1, it is better to set T, = N. At this time, equation (1) and equation (
From 2), it can be seen that M'+ has a [p1 coefficient of =M (3). On the other hand, the total frequency division number N1 in the variable frequency divider 22 in FIG.
It is expressed as the product of the frequency division number of a and 22C, and N'M1・P=(
M-K)・P(4). Comparing Equation (4) with Equation (1), it can be seen that the frequency division number can be reduced by the amount of frequency conversion performed using the good frequency converter 22'I). - As an example, f
c h=25 K t(z .

f SYN" 800 MHz, P2128, in the configuration shown in Figure 1, M-250, l'J = 32000, but in the configuration shown in Figure 3, it becomes 240 (oscillation frequency of oscillator 1G = 6MH7,) Then M'=10, N'=128
Of, N1 is N's 1. /200 or less. P
The loop gain of the L L loop is proportional to the reciprocal of the dividing number N and N', so in this example, the loop gain is set to 2.
It can be made larger by 00 times or more. Therefore, frequency response is improved, and frequency switching time etc. can be significantly shortened.

In this way, the embodiment of FIG. 3 can be realized by simply adding the mixer 22b to the conventional one shown in FIG. It is possible to significantly shorten the frequency switching time etc. without requiring the additional mixer 22b.
It is extremely easy to realize this because it only needs to operate at a low frequency of 8 degrees. An example of the configuration of the mixer 22b is shown in FIG. The output of the reference oscillator 1G is input to the mixer input terminals 23 and 24 as the output of the pre-frequency divider 22a, and these inputs are supplied to the exclusive OR circuit 25, and the output is passed to the low-pass filter; If so, the I gate wave number conversion output is mixer output terminal 2.
7 and supplies this output to the main frequency divider 22c. Since the mixer 22b can be constructed easily in this way, the number of parts increases little due to implementation, and the adjustment points are all the same. The mixer 22F) shown in FIG.
It can be integrated into an integrated circuit, which is very advantageous for making synthesizers more compact and highly reliable.

The frequency division number of the prescaler 22a is P, not less than 1 in P+1,
In general, if P and Q (numbers different from P) can be made to be seven, P and Q are both integers greater than or equal to 2, and in this case, the formula (
2) tj: Use Q instead of (P + 1). i
4i:: Ai of the combination counter 22a: 0 or a positive integer smaller than either LJ or Q, and the frequency division pW of the main frequency divider 22C (' is an integer of 2 or more.

<Effects> As explained above, according to this invention, miniaturization, ICization,
It is possible to realize a frequency synthesizer that has an extremely short response time when changing the frequency i blade or when turning on the power, while having a configuration that allows easy adjustment. .

Therefore, if it is applied to various pure mobile communication methods (mobile 11IJ car, city phone, cordless telephone, personal radio, etc.) which are expected to develop more and more in the future, the time spent searching for air channels will be reduced.
It becomes possible to conduct sky channel exploration more frequently,
Therefore, the wireless cell can be used more efficiently and can contribute to the subscriber capacity of the system.

■In a non-glandular board that performs intermittent reception, since the rise time of the non-synthesizer becomes faster when it is turned on, it becomes possible to detect the received signal in a shorter time, and therefore the intermittent reception of unit time. If the number of pregnancies is reduced, the time during which the lights are turned on can be reduced, which can greatly contribute to reducing the power consumption of wireless devices.

This has the effect of increasing the performance of each method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional pulse swirl frequency synthesizer, and FIG. 2 is a block diagram showing the configuration of a conventional mixdown frequency synthesizer.
FIG. 3 is a block diagram showing seven embodiments of the invention;
Figure 4 shows an example of the configuration of mixer 2.2b in Figure 3.
This is a schematic diagram. 11: Voltage controlled oscillator, 12: Output 111^i child, 14
: Frequency setting terminal, 15: Phase ratio axis unit, 16: Reference oscillator, 17: Fixed frequency divider, 18: Loop filter, 22:
22a: front side frequency divider, 22b: mixer, 2
2C: Sufficient cylinder, 22d: Prescaler control counter. Patent applicant Takuo Kusano, agent for Nippon Telegraph and Telephone Public Corporation 1 Figure 2 Figure 3 Figure '4 Figure

Claims (1)

[Claims] (1) A voltage controlled oscillator whose oscillation frequency can be controlled from outside ↑-11, a variable frequency divider which divides and outputs the output signal of the voltage controlled oscillator by an integer ratio according to the set frequency, and its A phase comparator that compares the phase of the frequency-divided output signal from the variable dividing section and the normal/quasi signal, and a means for controlling the pressure extraction generator and installation device based on the output of the phase comparator. In the frequency synthesizer, the variable frequency dividing section d has a pre-frequency divider in which two frequency division ap (an integer of 2 or more) and Q (an integer of 2 or more that is equal to or greater than P) can be selected 1R, and a pre-divider in front of it 1+#. 1. A mixer that converts the output of the frequency divider into a 1M wave number lower frequency; 1. A main frequency divider that divides the output from the mixer by M (an integer of 2 or more) according to a set frequency; When the output of the prescaler is counted according to the set frequency A (O or a positive integer smaller than P and Q) cycles, the division number of the prescaler is set to the above P, and and a prescaler control counter that sets the frequency division number of the prescaler to l He Q every time a frequency division pulse is output from the main frequency divider. frequency synthesizer.