JP2001285061A - Pll frequency synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform switching between a variable mode and a fixed mode and to set the frequency division ratio of a reference counter for a PLL frequency synthesizer circuit. SOLUTION: This PLL frequency synthesizer circuit, which is provided with a crystal oscillator 20, the reference counter 33, a voltage controlled oscillator 30, a programmable counter 27, a loop filter 29 and a phase comparator 28, outputs the output signal of the oscillator 30 and has a mode changeover switch 7 that selects either or both modes between the fixed mode in which a desired piece of frequency division ratio data among pieces of frequency division ratio data stored in a counter value holding circuit 2 is inputted to both the counters 27 and 33, and the variable mode in which frequency division ratio data outputted from a shift register 26 is inputted to either or both counters 27 and 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer circuit used in communication equipment such as a portable telephone and a cordless telephone, and more particularly to a double superheterodyne wireless communication used in two frequency bands. The present invention relates to a PLL frequency synthesizer circuit suitable for a device.

[0002]

2. Description of the Related Art In recent years, a lock-up time has been required to be shortened for a PLL frequency synthesizer circuit used in a communication device, a video device, and the like. This is because a PLL frequency synthesizer circuit used in a double superheterodyne system is required. The same can be said. Here, a double superheterodyne system using a PLL frequency synthesizer circuit will be described below. For example, Japanese Patent Application Laid-Open No. 10-154946
FIG.
It will be described according to. FIG. 8 is a circuit block diagram of a wireless section of a wireless portable telephone that can be used in two frequency bands, a digital band and an analog band. As shown, the circuit block includes an antenna 10 for both digital and analog bands, a transmission / reception switching circuit 23, a bandpass filter 11 for a reception RF signal, and a reception RF for downconverting the reception RF signal to a first IF signal. Mixer 1
2, first IF signal band-pass filter 13, first IF
Receiving IF mixer 14 for down-converting the signal to a second IF signal, IF band PLL frequency synthesizer circuit 17, band pass filter 18 for selecting a signal output from the mixer, IF band PLL frequency synthesizer circuit, and RF A mixer 19 for frequency mixing signals transmitted and output from the band PLL frequency synthesizer circuit,
It comprises a VCXO (crystal oscillator) 20 and an RF band PLL frequency synthesizer circuit 21.

There are two frequency bands, a digital band and an analog band, in a portable telephone, and it has been decided to unify all these two bands into a digital band system. Also, a plurality of communication channels are prepared at intervals of 25 kHz. For example, in a certain system, the frequency interval between the transmission frequency and the reception frequency in each channel is 130 MHz in the digital band and 55 MHz in the analog band. In this example, in the case of the digital band, the transmission frequency band is 940 to 948 MHz.
z, the reception frequency band is 810 to 818 MHz, and in the case of the analog band, the transmission frequency band is 925 to 940 MHz,
The reception frequency band is 870 to 885 MHz.

First, the case of the digital band will be described. For example, when a communication channel having a transmission frequency of 940 MHz and a reception frequency of 810 MHz is used, at the time of transmission, the IF band PLL frequency synthesizer circuit 1 is used.
The frequency of the 405.45 MHz signal oscillated and output from 7 and the 534.55 MHz signal oscillated and output from the RF band PLL frequency synthesizer circuit 21 are mixed by the mixer 19. 940 MHz which passed through the band-pass filter 18 among the signals output from the mixer 19
Is input to the transmission system circuit 22 as a transmission carrier. In the transmission system circuit 22, π / 4 shift QPSK
The modulated baseband signal is directly orthogonally modulated by the transmission carrier, and the output modulation wave is transmitted from the antenna 10 via the transmission / reception switching circuit 2 switched to the transmission side.

During reception, the oscillation frequency of the RF band PLL frequency synthesizer circuit 21 is 534.55 MHz.
z to 810.45 MHz and the IF band P
The 405.45 MHz signal oscillated and output from the LL frequency synthesizer circuit 17 and the 810.45 M signal oscillated and output from the RF band PLL frequency synthesizer circuit 21
The frequency of the Hz signal is mixed by the mixer 19. Of the signals output from the mixer 19, the target signal of 1215.9 MHz that has passed through the band-pass filter 18 and the transmission / reception switching circuit 23 that has been received from the antenna 10 and has been switched to the reception side, the received RF signal band-pass The 810 MHz reception RF signal passed through the filter 11 is frequency-mixed by the reception RF mixer 12. Of the signals output from the RF mixer 12, a 405.9 MHz signal that has passed through the first IF band-pass filter 13 becomes a first IF signal, and the first IF signal and the IF band PLL frequency synthesizer circuit 17 oscillate and output the signal. Done 40
The 5.45 MHz signal is frequency-mixed by the receiving IF mixer 14. Of the signals output from the receiving IF mixer 14, the 450 kHz signal that has passed through the second IF bandpass filter 15 becomes the second IF signal, is input to the demodulation system circuit 16, and is subjected to π / 4 shift QPSK demodulation.

Transmission and reception are performed as described above. When switching between transmission and reception, the oscillation frequency of the RF band PLL frequency synthesizer circuit 21 is maintained while the IF band PLL frequency synthesizer circuit 17 remains at 405.45 MHz. Is switched between 534.55 MHz and 810.45 MHz. When the communication channel is switched, the RF band PLL frequency synthesizer circuit 2 is switched.
The oscillation frequency of 1 is 534.55 to 542.55 at the time of transmission.
MHz and 810.45 to 818.45 MHz during reception.

Next, the case of the analog band will be described. For example, when a communication channel having a transmission frequency of 925 MHz and a reception frequency of 870 MHz is used, at the time of transmission, the IF band PLL frequency synthesizer circuit 17 is used.
And the oscillation frequency of the RF band PLL frequency synthesizer circuit 21 is 54.5 MHz and 870.50 M, respectively.
Hz. The 54.5 MHz signal oscillated and output from the IF band PLL frequency synthesizer circuit 17 and oscillated from the RF band PLL frequency synthesizer circuit 21 are output.
The output signal of 870.50 MHz is frequency-mixed by mixer 19. 925 MH of the signal output from the mixer 19 that has passed through the band-pass filter 18
The target signal of z is input to the transmission system circuit 22 as a transmission carrier. In the transmission system circuit 22, the π / 4 shift QPS
The K-modulated baseband signal is directly quadrature-modulated by the transmission carrier, and the output modulated wave is transmitted from the antenna 10 via the transmission / reception switching circuit 23 switched to the transmission side.

At the time of reception, the oscillation frequencies of the IF band PLL frequency synthesizer circuit 17 and the RF band PLL frequency synthesizer circuit 21 are 405.45, respectively.
MHz and 870.45 MHz, and the IF band P
The 405.45 MHz signal oscillated and output from the LL frequency synthesizer circuit 17 and the 870.45M signal oscillated and output from the RF band PLL frequency synthesizer circuit 21
The frequency of the Hz signal is mixed by the mixer 19. Of the signals output from the mixer 19, the target signal of 1275.9 MHz passed through the band-pass filter 18 and the band-pass filter for the received RF signal via the transmission / reception switching circuit 23 received from the antenna 10 and switched to the reception side. 1
1 is received by the receiving RF signal of 870 MHz.
The frequency is mixed by the F mixer 12. The RF mixer 1
The signal of 405.9 MHz that has passed through the first IF band-pass filter 13 among the signals output from the second IF
405.45 oscillated and output from the first IF signal and the IF band PLL frequency synthesizer circuit 17.
The frequency of the MHz signal is mixed by the receiving IF mixer. 450k of the signal output from the reception IF mixer 14 that has passed through the second IF bandpass filter 15
The Hz signal becomes the second IF signal, and is input to the demodulation system circuit 27 and subjected to π / 4 shift QPSK demodulation.

Transmission and reception are performed as described above. When switching between transmission and reception, the IF band PLL frequency synthesizer circuit 17 operates at 54.5 MHz and 405.45.
MHz, and the oscillation frequency of the RF band PLL frequency synthesizer circuit 21 is switched between 870.50 MHz and 870.45 MHz.
Further, when the communication channel is switched, the oscillation frequency of the RF band PLL frequency synthesizer circuit 21 becomes 87
0.50 to 885.50 MHz, 870.45 at reception
It will be switched between ~ 885.45 MHz.

Here, focusing on the IF band PLL frequency synthesizer circuit 17, the PLL frequency synthesizer circuit 17 has two kinds of frequencies, 54.5 MHz and 405.
It only synthesizes 45 MHz. That is, assuming that the oscillation frequency of the VCXO 20 is 12.8 MHz and that the PLL frequency synthesizer circuit 17 has a pulse swallow counter, the respective counter set values in the PLL frequency synthesizer circuit 17 can be calculated from the following calculation. It looks like 9.

That is, assuming that a dual modulus prescaler division ratio is 16, the frequency F synthesized by the pulse swallow method is F = ((16 × B) +
A) × 12.8 MHz / R

Therefore, when F = 54.5 MHz, 54.5 MHz = ((16 × 68) +2) × 12.8M
Hz / 256 When F = 405.45 MHz, 405.45 MHz = ((16 × 506) +13) × 1
2.8 MHz / 256.

As described above, in the system shown in FIG. 8, the frequencies to be synthesized by the IF band PLL frequency synthesizer circuit 17 are 54.5 MHz and 405.45 MHz.
Therefore, the set value B of the 11-bit programmable counter in the PLL frequency synthesizer circuit 17 is 68
And 506, the set value A of the 4-bit programmable counter
Are only 2 and 13.

Here, the number of bits of the programmable counter and the dividing ratio of the dual modulus prescaler are:
Reference is made to National Semiconductor's dual PLL frequency synthesizer LMX2332L. Furthermore,
The dual PLL frequency synthesizer LMX2332L
Is used, the setting of the counter value is as follows. This will be described with reference to FIGS.

FIG. 10 is a block diagram of a counter section of the dual PLL frequency synthesizer LMX2332L. The output of the 22-bit shift register 24 is connected to four counters. 15-bit RF reference counter 3, a 15-bit IF reference counter 5, an 18-bit RF programmable counter 4 for dividing the output of an RF dual modulus prescaler (not shown), and dividing the output of an IF dual modulus prescaler (not shown). And a 15-bit IF programmable counter 6.

FIG. 11 shows a shift register 2 of 22 bits.
4 is a format of DATA which is input data,
It has a configuration of 2 control bits and 20 data bits. Since the control bits are two bits, four types of data bits can be controlled. That is, when C1 and C2 = “00”, the IF reference counter 5 is set with 20 data bits, and when C1 and C2 = “01”, the RF reference counter 3 is set with 20 data bits. When C1 and C2 = “10”, the IF programmable counter 6 is set with 20 data bits, and when C1 and C2 = “11”, the RF programmable counter 4 is set with 20 data bits. It is possible to do. Here, the number of data bits is 20 bits, which is larger than the number of bits of each of the four counters, because various settings other than the counter value are assigned to the remaining bits. Further, since the dual PLL frequency synthesizer LMX2332L employs a pulse swallow method, both the IF and RF have two programmable counters. The IF programmable counter 6 includes an IF 11-bit programmable counter (not shown) and an IF 4-bit programmable Although not shown, the counter and the RF programmable counter 4 include an RF 11-bit programmable counter and an RF 7-bit programmable counter.

FIG. 12 shows a 22-bit shift register 24.
6 is a time chart when data is set to the data. First,
The load enable signal LE is dropped to Low, and the data signal DATA is taken in by the clock signal CK. Next, the 2-bit DA just before LE rises to High.
TA corresponds to the control signals C1 and C2.
The bit selects one of the four counters.

As described above, for example, when a PLL frequency synthesizer circuit is used in the double superheterodyne system, a system configuration may be adopted in which only two types of programmable counter values are required on the IF side. However, even in that case, in the conventional PLL frequency synthesizer circuit, it is necessary to input all 22-bit data to the 22-bit shift register. For example, in the above-described example of the analog band, the IF band PLL frequency synthesizer circuit 17 performs 54.
Since the frequency is switched between 5 MHz and 405.45 MHz, during reception, the IF 11-bit programmable counter value is 506 and the IF 4-bit programmable counter value is 13, so that the input of DATA is as shown in FIG.
At the time of transmission, since the IF 11-bit programmable counter value is 68 and the IF 4-bit programmable counter value is 2, the input of DATA is as shown in FIG. That is,
Even though only two types of counter values are used, it takes 22 clocks to set the counter value.
In this case, the lockup time after switching between transmission and reception is unnecessarily extended. Because, in recent years, the lock-up time has been increasingly required to be shortened, and some places require several tens of microseconds. However, at the same time, there is a great demand for lower power consumption. For example, the clock signal CK in the block in FIG. 10 must be slowed down. If the frequency of the clock signal CK is 1M
If the frequency is 22 Hz, the clock is 22 microseconds for 22 clocks, and the lock-up time is extended accordingly.

Therefore, the prior art which has taken measures against the above problems will be specifically described. For example, JP-A-11-2
This corresponds to a PLL frequency synthesizer circuit disclosed in Japanese Patent Publication No. 39057, which will be described with reference to FIG.

FIG. 14 is a block diagram showing an example of a conventional PLL frequency synthesizer circuit. As shown, the PLL frequency synthesizer circuit S1 includes a voltage controlled oscillator 3 that changes the frequency in accordance with an input control voltage.
0 (hereinafter referred to as VCO 30), a programmable counter 27 for dividing a signal output from the VCO 30 by a dividing ratio,
A reference oscillator 20 for generating a reference signal, a signal output from the programmable counter 27 and the reference oscillator 2
A phase comparator 28 that compares a phase with a signal output from 0 and outputs a DC voltage corresponding to the phase difference, and a PLL circuit 31 including a loop filter 29. A microcomputer 25 for outputting frequency data, a shift register 26, a counter value holding circuit 2 for setting and holding a frequency dividing ratio in advance, and a mode changeover switch 7 for selecting the shift register 26 and the counter value holding circuit 2 Consists of However, the switch 7 can connect and disconnect the shift register 26 and the programmable counter 27 or the counter value holding circuit 2 and the programmable counter 27, which is the same as that shown in FIG. This is a major difference from the prior art.

In the PLL frequency synthesizer S1 configured as described above, the signal of the reference frequency fr output from the reference oscillator 20 is input to the phase comparator 28, and the VCO 30
Is compared with a signal obtained by dividing the output frequency fvco into 1 / N by a programmable counter 27, and only a DC component is extracted by a loop filter 29.
Input to O30. The VCO 30 operates to change the frequency in accordance with the input control voltage so as to match the phase of the reference frequency output from the reference oscillator 20,
A loop is performed to stabilize the output frequency fvco of O30 at a constant value.

Here, fvco = N × fr holds.

At this time, the division ratio 1 / N is set so that a counter value holding circuit 2 (fixed mode) for storing one or more preset division ratio data and arbitrary division ratio data can be generated. One of the microcomputers 25 (variable mode) to be operated is selected by the mode changeover switch 7.

For example, assuming that the fixed frequency division ratio effective for the fixed mode is 1500 and the programmable counter 27 is composed of 14 bits, 2 representing 1500 is used.
The base number data is “00010111011100”.
This data is stored in the counter value holding circuit 2,
When used in the fixed mode, a switching signal is input to the input terminal 32 by operating an operation unit (not shown), and the mode switching switch 7 is set to the fixed mode, whereby data is output from the counter value holding circuit 2. The dividing ratio of the programmable counter 27 is set to 1500, and the dividing ratio is 1
An oscillation frequency corresponding to 500 is obtained from the VCO 30.

Next, in the case of a so-called variable mode in which the oscillation frequency of the VCO 30 is freely set, a switching signal is input to the input terminal 32 and the mode switch 7 is set to the variable mode.

For example, when the frequency division ratio is set to 1000, the microcomputer 25 sends the following data.
00001111101000. The serial data is converted into parallel data by the shift register 26 and input to the programmable counter 27. The programmable counter 27 sets a division ratio of 1000, and an oscillation frequency corresponding to the division ratio is obtained from the VCO 30.

As described above, in the conventional PLL frequency synthesizer S 1, when a specific frequency is generated from the VCO 30, the frequency division ratio is set based on the frequency division ratio data read from the counter value holding circuit 2. Therefore, it is not necessary to always transmit the frequency division ratio data from the microcomputer 25 to the programmable counter 27. Therefore, if the PLL frequency synthesizer circuit S1 is used in the IF band PLL frequency synthesizer circuit 17 of the wireless section of the double superheterodyne wireless communication device, for example, the lock-up time when switching between transmission and reception in the analog band can be shortened. I can do it.

[0028]

SUMMARY OF THE INVENTION However,
When a conventional PLL frequency synthesizer circuit is used for a radio unit in a double superheterodyne wireless communication device, a switching signal for externally selecting data to be transmitted to a programmable counter is performed. In consideration of this, one input terminal is added.

In recent years, there has been an increasing demand for miniaturization of portable devices such as portable telephones, and so has the PLL frequency synthesizer circuit used therein. Therefore, an increase in the number of terminals is not preferable because it hinders miniaturization of the portable device.

Further, the conventional PLL frequency synthesizer circuit shown in FIG. 14 does not consider that there is no reference counter for dividing the reference signal and that the division ratio of the reference counter may change. This is because, when the PLL frequency synthesizer circuit is used in a radio section of a double superheterodyne radio communication device, the reference frequency may be switched depending on the system configuration. For example, in the above-described transmission and reception in the analog band, the reference frequency on the IF side is 12.8 MHz /
Although 256 = 50 KHz, separate values can be intentionally set. In general, if the reference frequency is high, the lock-up time is short, but the characteristics such as C / N deteriorate. Therefore, for example, it is necessary to change the reference frequency in transmission and reception to make the system configuration suitable for a mobile phone. Conceivable. However, since the conventional PLL frequency synthesizer circuit does not take into account the possibility that the frequency division ratio of the reference counter may change, the PLL frequency synthesizer circuit must be used in the radio section of all double superheterodyne wireless communication devices. Can not.

Accordingly, the present invention has been made in view of the above-mentioned problems of the prior art. By increasing the number of control bits in the bit data shown in FIG. It is another object of the present invention to switch modes and further to enable setting of a dividing ratio of a reference counter in a PLL frequency synthesizer circuit provided with a reference counter as shown in FIG.

[0032]

Means for Solving the Problems The P of the present invention (first invention)
The LL frequency synthesizer circuit includes a first frequency divider for dividing the output signal of the reference oscillator, a second frequency divider for dividing the output signal of the voltage controlled oscillator, and a first frequency divider for dividing the output signal of the voltage controlled oscillator. A phase comparator for detecting a phase relationship between an output signal and an output signal from the second frequency divider, and outputting an error signal corresponding to a phase difference between the two signals as a control voltage of the voltage controlled oscillator via an integrator. And an output signal of the voltage-controlled oscillator.
In the PLL frequency synthesizer circuit to be output, data storage means for storing one or more frequency division ratio data, data generation means capable of outputting arbitrary frequency division ratio data, and data stored in the data storage means A fixed mode in which desired frequency division ratio data in the frequency division ratio data is input to both frequency dividers and a variable mode in which frequency division ratio data output from the data generating means is input to both frequency dividers And a mode selecting means for selecting one of the modes.

Further, in the PLL frequency synthesizer circuit according to the present invention (second invention), in the PLL frequency synthesizer circuit according to the first invention, a mode switching signal for switching the mode selecting means is transmitted from the data generating means. It is characterized by being output.

Further, the PLL frequency synthesizer circuit of the present invention (third invention) is a PLL frequency synthesizer circuit of the first or second invention.
In the LL frequency synthesizer circuit, the data storage means for storing the frequency division ratio of the first frequency divider and the second frequency divider can change stored data. Things.

Further, a PLL frequency synthesizer circuit according to the present invention (fourth invention) is characterized in that all means in the PLL frequency synthesizer circuit according to the first, second or third invention are integrated. It is assumed that.

That is, in order to achieve the above object, the present invention eliminates a counter switching terminal from a shift register or a counter switching circuit from a counter value holding circuit and removes an input to the shift register from the conventional configuration. A programmable counter that provides an alternative to the switching terminal by increasing the number of control bits among the data bits of the serial data, and also divides the output of the voltage controlled oscillator,
The frequency division ratio of all the counters can be controlled even for a PLL frequency synthesizer circuit having a reference counter for dividing the output of the reference signal oscillator.

Therefore, according to the PLL frequency synthesizer circuit according to the present invention, by eliminating the switching terminal and controlling the switching switch with the control bit of the data bit, the conventional function is not lost when the IC is realized. The number and the chip area can be prevented from increasing.

Further, since the division ratio can be set for both the programmable counter and the reference counter, it can be used for the radio section of all double superheterodyne radio communication devices.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a PLL according to the present invention.
FIG. 3 is a block diagram showing an embodiment of a frequency synthesizer circuit, in which the same or corresponding parts as those of the above-described conventional technology are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in the figure, the PLL frequency synthesizer circuit S0 includes a VCO 30 for changing the frequency in accordance with an input control voltage, a programmable counter 27 for dividing a signal output from the VCO 30 by a dividing ratio, a reference A reference oscillator 20 for generating a signal fr; a reference counter 33 for dividing a signal output from the reference oscillator 20 to a desired frequency division number;
7 includes a phase comparator 28 that compares the phase of the signal output from the signal with the signal output from the signal and outputs a DC voltage corresponding to the phase difference, and a loop filter 29. A microcomputer 25 for outputting frequency-divided data, a shift register 26 for outputting arbitrary frequency-division ratio data, a counter value holding circuit 2 for holding a counter value of a plurality of bits, the shift register 2
6 and a mode changeover switch 7 for selecting the counter value holding circuit 2. However, the switch 7
Are a shift register 26 and a programmable counter 27
The connection and disconnection with the reference counter 33 or between the counter value holding circuit 2 and the programmable counter 27 and the reference counter 33 can be performed.

In the PLL frequency synthesizer S0 configured as described above, the signal of the reference frequency fr output from the reference oscillator 20 is input to the reference counter 33,
The frequency is divided by the reference counter 33 to 1 / R.
Further, the output of the reference counter 33 is the phase comparator 2
8, the output frequency fvco of the VCO 30 is compared with a signal obtained by dividing the output frequency fvco into 1 / N by the programmable counter 27, only the DC component is extracted by the loop filter 29, and this control voltage is input to the VCO 30. VCO3
At 0, the frequency is changed according to the input control voltage to operate to match the phase of the reference frequency output from the reference counter 33, and a loop is performed to stabilize the output frequency fvco of the VCO 30 to a constant value. .

Here, it holds that fvco = N × (fr / R).

At this time, the division ratios 1 / N and 1 / R are set by a counter value holding circuit 2 (fixed mode) for storing one or more division ratio data set in advance and arbitrary division ratio data. One of the microcomputers 25 (variable mode) that enables generation of
Is selected by the user.

Next, the counter section C0 in FIG. 1 will be described in detail with reference to FIGS.

FIG. 2 is a block diagram showing one embodiment of a counter section of the PLL frequency synthesizer circuit according to the present invention.
FIG. 3 shows the input data format of a 24-bit shift register, which is one module in the counter section. In each figure, the same or corresponding parts as those of the above-mentioned prior art are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 2, the counter section C of the PLL frequency synthesizer circuit according to the first embodiment of the present invention
0 indicates a 15-bit RF reference counter 3, an 18-bit RF programmable counter 4, a 15-bit IF reference counter 5, and a 15-bit IF programmable counter 6 as in the conventional counter unit shown in FIG. It comprises a shift register 1, a counter value holding circuit 2, and a mode changeover switch 7. Here, the mode switching signal 8 shown in FIG.
It is output from the 24-bit shift register 1 and is not directly supplied from outside. This point is different from the prior art shown in FIG. 14 described above. Further, in the present invention, the division ratio can be set for each reference counter for dividing the signal from the reference oscillator (not shown). The mode can be switched.

FIG. 3 is an extension of the data format of FIG. 11 shown in the prior art, in which the number of control bits for generating the mode switching signal 8 is increased by 2 bits (C3, C4) (FIG. 3). Shaded part inside).

[0048]

[Table 1]

Table 1 shows the increased 2-bit operation. For example, when C3 and C4 = 0, 0, the normal operation, that is, from the 24-bit shift register 1 through the mode changeover switch 7 to each counter. When the counter value is set, and when C3 and C4 = 0, 1, the first counter value is set from the 24-bit shift register 1 to the counter value holding circuit 2 through the data bus 9, and at the same time, the mode switching signal 8 holds the counter value. Select the data of circuit 2 and select C3, C
When 4 = 1, 0, the second counter value is set from the 24-bit shift register 1 to the counter value holding circuit 2 via the data bus 9, and at the same time, the mode switching signal 8 selects the data of the counter value holding circuit 2.

Next, the operation of the counter section according to the present invention will be described with a specific example. For example, the PL of the present invention is applied to a double superheterodyne wireless device shown in FIG.
Considering the case of using an L frequency synthesizer circuit,
First, it is necessary to set the counter value corresponding to the transmission / reception frequency of the analog band in the counter value holding circuit 2 immediately after the power is turned on. That is, since the counter value of the IF programmable counter 6 becomes the value shown in FIG. 9, for example, the counter value at the time of reception of the analog band is changed to the first counter value,
The counter value at the time of transmission of the analog band is set as the second counter value, and each value is set in the counter value holding circuit. FIG. 4 shows a case where a counter value for transmission and reception in the analog band is actually set for the data format of FIG. 3 described above. FIG. ) Corresponds to transmission in the analog band. FIG. 5 is a time chart when the transmission / reception counter value in the analog band is set in the counter value holding circuit 2 through a 24-bit shift register. In the description of the related art with reference to FIG. 10, it took 22 clocks to set the counter value. However, when setting the counter value in the counter value holding circuit 2 according to the present invention, the control bits are increased by 2 bits. Therefore, 24 clocks are required.

Next, there is a case where the counter values of the two types of IF programmable counters 6 are already held in the counter value holding circuit 2 and are currently operating in the analog band transmission mode. Since the counter value is already held in the counter value holding circuit 2, there is no need to set the counter value again, and when shifting to the analog band reception mode, it is only necessary to set the four bits in FIG. . FIG.
Is a time chart for the setting. Since only four control bits are set, only four clocks are required. Similarly, when shifting from the analog band reception mode to the analog band transmission mode, only the four bits shown in FIG. 6B are set, so the number of clocks required for setting is four.

As described above, immediately after the power is turned on, 24 clocks are required for each counter value in order to cause the counter value holding circuit to set the counter value.
If the FF is not performed, the value is held, so that the data from the counter value holding circuit 2 can be supplied to each counter when switching between analog transmission and reception, and the lockup time required for the switching is shortened.

[0053]

As described above, according to the present invention, a circuit for holding a plurality of counter values is provided so that the setting and selection of the counter values can be performed without newly increasing the number of input signals. When applied to a counter, the PLL frequency synthesizer circuit according to the present invention is used in a double superheterodyne wireless communication device.
For example, the lockup time required for switching from transmission to reception is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a PLL frequency synthesizer circuit according to the present invention.

FIG. 2 is a diagram showing one embodiment of a counter unit in the PLL frequency synthesizer circuit according to the present invention.

FIG. 3 is a diagram showing a format when a frequency division ratio is set for an embodiment of the PLL frequency synthesizer circuit according to the present invention.

FIG. 4 is a diagram showing a data string when a frequency division ratio is set for an embodiment of the PLL frequency synthesizer circuit according to the present invention.

FIG. 5 is a waveform diagram showing an operation of the PLL frequency synthesizer circuit according to the embodiment of the present invention when a division ratio is set.

FIG. 6 is a diagram showing a data string when a frequency division ratio is set for an embodiment of the PLL frequency synthesizer circuit according to the present invention.

FIG. 7 is a waveform diagram showing an operation of the PLL frequency synthesizer circuit according to the embodiment of the present invention when a frequency division ratio is set.

FIG. 8 is a circuit diagram of a wireless unit in a double super heterodyne wireless communication device using a PLL frequency synthesizer circuit.

FIG. 9 is a diagram showing specific setting values of a frequency division ratio in a counter in an IF band PLL frequency synthesizer circuit.

FIG. 10 is a block diagram of a counter section in a conventional PLL frequency synthesizer circuit.

FIG. 11 is a diagram showing a format when a frequency division ratio is set in a conventional PLL frequency synthesizer circuit.

FIG. 12 is a waveform chart showing an operation when a frequency division ratio is set in a conventional PLL frequency synthesizer circuit.

FIG. 13 is a diagram showing a data string when a frequency division ratio is set in a conventional PLL frequency synthesizer circuit.

FIG. 14 is a block diagram showing a configuration of a conventional PLL frequency synthesizer circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 24-bit shift register 2 Counter value holding circuit 3 RF reference counter 4 RF programmable counter 5 IF reference counter 6 IF programmable counter 7 Mode changeover switch 8 Mode changeover signal 9 Data bus 10 Digital and analog band shared antennas 11, 13, 15 , 18 band pass filter 12, 14, 19 mixer 16 demodulation system circuit 17 IF band PLL frequency synthesizer circuit 20 VCXO (crystal oscillator) 21 RF band PLL frequency synthesizer circuit 22 transmission system circuit 23 transmission / reception switching circuit 24 22 bit shift register 25 micro Computer 26 Shift register 27 Programmable counter 28 Phase comparator 29 Loop filter 30 Voltage controlled oscillator (VCO) 31 P L circuit 32 input terminal 33 reference counter S0 PLL frequency synthesizer circuit S1 PLL frequency synthesizer circuit C0 counter

Claims (4)

[Claims] A first divider for dividing an output signal of a reference oscillator; a second divider for dividing an output signal of a voltage controlled oscillator; and an output from the first divider. Signal and the second
A phase comparator that detects a phase relationship with an output signal from the frequency divider and outputs an error signal corresponding to a phase difference between the two signals through an integrator as a control voltage of the voltage-controlled oscillator. A PLL frequency synthesizer circuit using the output signal of the voltage-controlled oscillator as an output, a data storage unit for storing one or more division ratio data, a data generation unit capable of outputting any division ratio data, A fixed mode in which desired frequency division ratio data among the frequency division ratio data stored in the data storage means is input to the two frequency dividers, and the frequency division ratio data output from the data generation means is divided into the two frequency division data. A PLL frequency synthesizer circuit comprising: a mode selection unit that selects one of the variable modes to be input to the frequency divider. 2. The PLL frequency synthesizer circuit according to claim 1, wherein a mode switching signal for switching the mode selecting means is output from the data generating means. 3. The data storage means for storing the frequency division ratio of the first frequency divider and the second frequency divider, wherein stored data can be changed. 3. The PLL frequency synthesizer circuit according to 1 or 2. 4. The method according to claim 1, wherein all means are integrated.
A PLL frequency synthesizer circuit according to claim 1, 2 or 3.