JPS60128823A - Stationary decoupling relay - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a static inverse time relay, in particular to a static inverse time relay, which converts an analog input quantity into a corresponding frequency pulse train and counts this nof pulse train. This invention relates to a static inverse time-limiting relay that obtains time-limiting characteristics.

[Technical background of the invention]

There are various types of protective relays that protect power systems, and among them, inverse time-limiting overcurrent relays have conventionally utilized the inverse time-limiting characteristic obtained by the well-known inductor plate type mechanism to achieve the necessary characteristics. It is configured to obtain

[Problems with background technology]

The induction disk type has a moving part, so it is prone to problems such as chattering, and there are also anti-time relays that use electronic circuits, but the circuit configuration is complicated.

[Purpose of the invention]

The present invention has been made with the aim of solving the above-mentioned problems (2).It is also an object of the present invention to provide a static anti-time relay that can obtain highly reliable anti-time characteristics with a simple circuit. There is.

[Summary of the invention]

In the present invention, the amount of electricity input from the power system and the constant amount of electricity are input in a switchable manner using a changeover switch, and when the amount of input electricity exceeds a predetermined value, first a pulse corresponding to this input amount of electricity is input. is counted, and when this is greater than a predetermined value, the selector switch is switched to the constant amount of electricity side, and the pulse train due to the constant amount of electricity is counted, and when this is greater than a predetermined value, an output is derived.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a static inverse time relay according to the present invention. Although V in Fig. 1 is not shown, the amount of electricity corresponding to the operating setting value of the relay varies from the amount of electricity corresponding to the magnitude of the current in the power system that has been full-wave rectified by the current transformer and rectifier circuit. ■. I minus I. It's a considerable voltage.''

is a constant voltage. 1 is a changeover switch that selectively outputs one of the two inputs according to the signal 11;
Here, when the signal 11 is at logic level "0", I
- When the voltage V corresponding to Io is "1", the voltage is a constant voltage ■
. shall be output. 2 is a voltage that converts the output voltage of the changeover switch 1 into the corresponding frequency/wavelength train.
A frequency conversion circuit, 3, is a counter for counting the frequency/wavelength sequence output from the voltage-frequency conversion circuit 2, and 4 is a logic level “1” when the count value of the counter 3 reaches a predetermined value of 1 or more. 1", and if the count value of the counter 3 is less than a predetermined value, the level detection circuit outputs a logic level "0". 5 also outputs "1" when the output of the level detection circuit 4 becomes "1". ", and then the level detection circuit 4
Even if the output of
A latch circuit that continues to hold the output "1" until the output 10 becomes "1", and 6 is an output circuit that detects the second "1" of the output of the level detection circuit 4 and outputs the level detection circuit. Cleared when output 10 of 9 is "1". 7 is NOT
The circuit 8 is an AND circuit. Reference numeral 9 is a level detection circuit that outputs "0" when the voltage V of the I-Io phase is positive, and "1" otherwise. The count value is cleared when
It is controlled so that counting is possible only when the output 10 of the level detection circuit 9 is "0".

The output circuit 6 can be easily realized by using a binary counter having a reset function and outputting the second bit.

Next, the present invention constructed as described above will be explained in detail.

FIG. 2 is a time chart showing the output of each circuit in FIG. 1. (a) shows the output signal 10 of the level detection circuit 9, and (b) shows the output signal 10 of the voltage-frequency conversion circuit 2,
(C) is the counted value of the counter 3, k is the level detection circuit 4
detection level, (d) is the output of the level detection circuit 4, (e
) indicates the output 11 of the latch circuit 5, and (') indicates the output of the output circuit 6, respectively.

At point A in the figure, the input current ■ increases due to a fault in the grid, and I
>Io. The output signal (a) (10 in FIG. 1) of the level detection circuit 9 changes from logic level "1" to "0" at point A because the voltage V corresponding to I-Io is positive.
”. When the signal (,) is "1", counter 3
The count value is forcibly set to zero as shown in (c) even though the Norse sequence shown in (b) is input.

Next, since the signal (,) became "0" at point A, (C)
Start counting the pulse train as shown in . Note that at this point, the pulse train counted by the counter 3 is equal to the voltage V since the output 11 of the ratte circuit 5 is "0" as shown in (,).
This is the frequency corresponding to

- When the count value of the counter 3 is reached, the output of the level detection circuit 4 becomes "1". - Next, the output 11 of the latch circuit 5
Also becomes rlJ. This signal causes the output of the selector switch 1 to change from voltage V to constant voltage V. can be switched to. Since the input voltage of the voltage-frequency conversion circuit 2 changed from V to vo,
A pulse train of a constant frequency Fo corresponding to this is output.

In addition, in this circuit, all bits of counter 3 are "1" for k.
However, the counted value of the counter 3 becomes zero at the next pulse as shown in B. At this time, the output of the level detection circuit 4 also becomes "0", but the output of the level detection circuit 9 becomes "0".
Since 0 is "O", the output of the latch circuit 5 remains "1" - The counter 3 starts counting from zero, and when the count value reaches 1 again, the level detection circuit 4 starts counting as described above. This is the second output. The output of the result output circuit 6 (f
) is 11'', and the final output is N in Figure 1.
The OT circuit 7 and the AND circuit 8 stop inputting pulses to the counter 3, and this state continues.

Also, for example, if the input is zero at 0 point, the above-mentioned V
As soon as the output 10 of the level detection circuit 9 becomes "1", the counter 3, latch circuit 5, and output circuit 6 are reset and ready for the next input.

Next, it will be explained below that the inverse time characteristic is obtained by the operation of each circuit as described above.

FIG. 3 shows an inverse time characteristic in which the vertical axis represents the operating time t1 and the horizontal axis represents the input current (2).

In general, the inverse time limit characteristic is approximated by equation (1).

kol to, Io are constants This approximate expression can be obtained in this circuit as follows.

In this circuit, T-I. The voltage V corresponding to is expressed by the following equation using a coefficient α.

■=α(I-I.)...(2) This voltage V is converted to a frequency F by the voltage-frequency conversion circuit 2.
is converted into a pulse train. If this conversion coefficient is β, the frequency F is expressed by the following equation.

F=βV...(3) This pulse train of frequency F is counted by the counter 3, and the time t/ until the counted value becomes equal to or less is expressed by the following equation using equations (2) and (3). .

When the count value of the counter 3 becomes "1", the outputs of the level detection circuit 4 and latch circuit 5 become "1" as described above.

When the output of the latch circuit 5 becomes "1" as described above, the output voltage of the changeover switch 1 changes from V to V. becomes.

This V. F because it is converted to the frequency Fo by the voltage-frequency conversion circuit 2. is expressed by the following equation.

F0=βv0...(5) This pulse train is counted again by counter 3, and the counted value is
The time t until . is constant as given by the following equation.

Therefore, the total operating time t is expressed as (4) t (6). This is the same as equation (3), α, β, v.

By determining the above, the inverse time characteristic shown in FIG. 3 can be realized.

In addition to the above description, the present invention has the following features.

(9) That is, the operation time can be easily set. The operation time setting means having a plurality of operation time characteristics as shown in FIG. 4, and selecting and using one of them. In order to set the operating time with the circuit configuration shown in FIG. 1, as shown in FIG. It may be provided between the circuits 8. This frequency dividing circuit 1
2, a frequency F corresponding to the input current and a constant frequency F. Since both are divided by the same ratio, the above-mentioned operation time setting can be easily achieved.

Furthermore, as shown in FIG. 6, the operating time can be similarly set by using a voltage dividing circuit 23 between the changeover switch 3 and the voltage-frequency conversion circuit 40, which divides the output voltage of the changeover switch at a predetermined ratio.

Another embodiment of the invention is shown in FIG. In Figure 7,
Components with the same reference numerals as in FIG. 1 will not be described.

In Fig. 7, 3/, 4/, and 5/ are a counter, a level detection circuit, and a latch circuit, respectively, and are counters 3 and C, respectively.
10) Same as level detection circuit 4 and latch circuit 5.

FIG. 8 shows output waveforms of each circuit shown in FIG. 7.

Components with the same reference numerals as in FIG. 2 will not be described. (C)’.

(d)' and (e)' are the outputs of the counter 3', level detection circuit 4', and latch circuit 5', respectively. In FIG. 7, as in FIG. 2, the output 1 of the level detection circuit 9 is at point A'.
Assume that 0 has changed.

As described above, the counter 3 counts the output (b) of the voltage-frequency conversion circuit 2. When this count value becomes 1' at the detection level of the level detection circuit 4, the output (d) of the level detection circuit 4, the output (,) of the latch circuit 5, and the output (b) of the voltage-frequency conversion circuit 2 are The changes shown in the figure are the same as in the previous example. On the other hand, the counter 3' has a constant frequency F since the output (e) of the latch circuit 5 becomes rlJ. Start counting.

From this point on, counter 3/ is frequency F as shown in (C)/. Count the pulse trains. When this count value becomes 1' at the detection level of the level detection circuit 4', the output of the level detection circuit 4' becomes 1' as shown in (d)'.

Next, the latch circuit 5' also becomes "1" and becomes the final output.

The reason why the count values of the counters 3 and 3' become zero again at point B/point C/ is because each counter continues to count the R pulse sequence. At this time, the outputs of the level detection circuits 4 and 4' also become "0", but since the outputs of each level detection circuit are held by the latch circuits 5 and 5', there is no problem in the response of the circuit. . Also, in this circuit configuration, if the input becomes zero during the above response, the output 10 of the level detection circuit 9 is instantaneously applied to the counters 3, 3' and the latch circuit 5.
, 5' are reset to prepare for the next input fluctuation.

In this embodiment, as in the previous embodiment, the operation time can be easily set by using a frequency dividing circuit or a voltage dividing circuit.

〔Effect of the invention〕

As described above, according to the present invention, the inverse time limit, characteristics, and operation time setting can be realized with a simple circuit.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of an embodiment of a static counter time relay according to the present invention, Fig. 2 is a time chart for explaining the operation, and Fig.
The figure is a general inverse time characteristic diagram, Figure 4 is an operation time settling diagram,
5 and 6 are diagrams showing only the main parts of other embodiments, and FIG.
FIG. 8 is a block diagram of another embodiment of the static inverse time relay according to the present invention, and FIG. 8 is a time chart for explaining the operation. 1... Selector switch 2... Voltage-frequency conversion circuit 3.31... Counter 4, 4', 9... Level detection circuit 5.5'... Latch circuit 6... Output circuit 7 ...NOT circuit 8...AND circuit 12...
Frequency divider circuit 13...External signal 14...Voltage divider circuit (7317) Agent Patent attorney Noriyuki Chika (and 1 others)
given name)

Claims (1)

[Claims] In a static inverse time relay having an operation time limit that is inversely proportional to the magnitude of the amount of electricity when the amount of electricity input from the power system is equal to or greater than a predetermined value, the time limit is constant with the amount of electricity input from the power system. a changeover switch that selects and outputs one of the electric quantities inputted with each electric quantity; a voltage-frequency conversion circuit that converts the electric quantity from the changeover switch into a pulse train according to the electric quantity; a counter that counts output pulses, a latte circuit that sends out an output when the counter value reaches a predetermined level, and the counter circuit, latch circuit, and output circuit are set only when the amount of input electricity is greater than or equal to the predetermined value. The selector switch is equipped with a level detection circuit to determine the current state, and the selector switch is switched to the constant electricity amount side at the first operation time period corresponding to the magnitude of the input electricity amount, and the second operation time according to the magnitude of the constant electricity amount. A static inverse time relay characterized in that an output is derived from an output circuit (1) after waiting for an operating time limit.