JPS60124951A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60124951A
JPS60124951A JP23458083A JP23458083A JPS60124951A JP S60124951 A JPS60124951 A JP S60124951A JP 23458083 A JP23458083 A JP 23458083A JP 23458083 A JP23458083 A JP 23458083A JP S60124951 A JPS60124951 A JP S60124951A
Authority
JP
Japan
Prior art keywords
film
wirings
aluminum
wiring
psg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23458083A
Other languages
Japanese (ja)
Inventor
Mitsuyoshi Araki
荒木 光好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23458083A priority Critical patent/JPS60124951A/en
Publication of JPS60124951A publication Critical patent/JPS60124951A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the disconnection of Al wirings due to corrosion or oxidation by a method wherein an insulation fil or a conductive film coating conductor wirings is left only on both sides of the conductor wirings by anisotropic etching. CONSTITUTION:The Al wirings 2 are formed on a semiconductor substrate 1, and next a PSG (phospho-silicate glass) film 4 is adhered over the whole surface. Then, the film 4 is etched by anisotropic etching and thus left only side surfaces of the wirings 2. A PSG film 5 is adhered again over the whole surface. In such a manner, discontinuous lines do not appear on the film 5, and the wirings 2 are protected by complete coating and then prevented from oxidation.

Description

【発明の詳細な説明】 (al 発明の技術分野 本発明は半導体装置の製造方法にがかり、特に配線の形
成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming wiring.

(bl 従来技術と問題点 周知のように半導体集積回路(IC)などの半導体装置
においては、半導体基板面に半導体素子やその他の素子
が形成され、これらから導出するアルミニウム(AI)
またはアルミニウムシリコン(AISi : Si含有
量10%以下)からなる配線層が、その上面に設けられ
ている。アルミニウムが配線として利用されるわけは電
気伝導度が高く、絶縁膜との接着力が強くて、安価に得
られ、しかもパターン形成が容易であるからである。
(bl) Prior Art and Problems As is well known, in semiconductor devices such as semiconductor integrated circuits (ICs), semiconductor elements and other elements are formed on the surface of a semiconductor substrate, and aluminum (AI) derived from these elements is formed on the surface of a semiconductor substrate.
Alternatively, a wiring layer made of aluminum silicon (AISi: Si content of 10% or less) is provided on the upper surface. Aluminum is used as wiring because it has high electrical conductivity, strong adhesion to insulating films, is inexpensive, and is easy to pattern.

第1図にアルミニウム配線の断面構造を示しており、1
は半導体基板、2はアルミニウム配線。
Figure 1 shows the cross-sectional structure of aluminum wiring.
is a semiconductor substrate, and 2 is an aluminum wiring.

3は燐珪酸ガラス(PSG)膜からなる絶縁保護膜であ
る。この形成法は、まずスパッタ法又は蒸着法によって
膜厚1μm程度にアルミニウム膜を被着した後、その上
にノボラック系樹脂からなるレジスト膜のパターンを形
成し、これをマスクにして塩素(C12)系ガス、ある
いは塩素化合物ガスでドライエツチングして幅2〜3μ
mのアルミニウム配線2を形成する。その上面に、PS
G膜3を化学気相成長(CV D)法又はプラズマ気相
成長(プラズマCVD)法で被着する。
3 is an insulating protective film made of a phosphosilicate glass (PSG) film. In this formation method, first, an aluminum film is deposited to a thickness of about 1 μm by sputtering or vapor deposition, and then a pattern of a resist film made of novolac resin is formed on it. Using this as a mask, chlorine (C12) is applied. Dry etching with system gas or chlorine compound gas to a width of 2 to 3μ
m aluminum interconnections 2 are formed. On the top surface, PS
The G film 3 is deposited by chemical vapor deposition (CVD) or plasma vapor deposition (plasma CVD).

ところで、最近利用されているドライエツチングは異方
性エツチングであって、高精度にパターンニングされる
利点があり、上記例のアルミニウム配線も同様に高精度
に形成される。しかし、その反面では配線層側部が急峻
になって、時には逆テーパー状に形成されることもある
。一方、PSG膜3は全方向から被覆されて、被覆性(
カバレージ)が良いが、図示のように配線層の側部には
半導体基鈑1」二から成長したPSG膜と、配線の側面
から成長したPSG膜との境界が不連続に形成される。
By the way, the dry etching that has been used recently is anisotropic etching, which has the advantage of highly accurate patterning, and the aluminum wiring in the above example can also be formed with high accuracy. However, on the other hand, the side portions of the wiring layer become steep, and sometimes are formed in a reverse tapered shape. On the other hand, the PSG film 3 is coated from all directions, with coverage (
However, as shown in the figure, the boundary between the PSG film grown from the semiconductor substrate 1'' and the PSG film grown from the side of the wiring is discontinuous on the side of the wiring layer.

そのために、その境界線から水やガスが侵入し易くてア
ルミニウム配線2を酸化し、やがては絶縁体となって断
線を起こす問題がある。
Therefore, there is a problem in that water and gas easily enter through the boundary line, oxidize the aluminum wiring 2, and eventually become an insulator and cause disconnection.

アルミニウム配線の断線には、アルミニウム配線の相互
リーク電流で断線する等、他の原因も知られているが、
結果的に断線は水分やガスが絶縁保護膜を透過してアル
ミニウムを腐食し酸化して起こる現象で、このようなア
ルミニウム配線の断線はrcの信頼性上からの1要な課
題である。
There are other known causes of disconnection in aluminum wiring, such as disconnection due to mutual leakage current between aluminum wiring.
As a result, disconnection is a phenomenon that occurs when moisture or gas permeates through an insulating protective film to corrode and oxidize aluminum, and such disconnection of aluminum wiring is an important issue from the viewpoint of RC reliability.

(C1発明の目的 4発明番、1、上記のような腐食や酸化によるアル(d
l 発明の構成 その[」的は、半導体基板上に導体配線をパターンニン
グし、次いで絶縁膜又は導電性膜を成長して前記導体配
線を被覆した後、異方性エツチングによって該絶縁膜又
は導電性膜をエツチングし、前記導体配線の両側に該絶
縁膜又は導電性膜を残存させる工程が含まれる半導体装
置の製造方法によって達成することができる。
(C1 Purpose of Invention 4 Invention No. 1. Al(d) caused by corrosion and oxidation as mentioned above.
l Structure of the Invention The object of the invention is to pattern a conductive wiring on a semiconductor substrate, then grow an insulating film or a conductive film to cover the conductive wiring, and then anisotropically etching the insulating film or conductive film. This can be achieved by a method for manufacturing a semiconductor device, which includes a step of etching a conductive film and leaving the insulating film or conductive film on both sides of the conductor wiring.

tel 発明の実施例 以下9図面を参照して実施例によって詳細に説明する。tel Embodiments of the invention Examples will be described in detail below with reference to nine drawings.

第2図ないし第5図は本発明にかかる形成方法の工程順
断面図を示しており、第2図ば4’導体基板1上に膜厚
1.um、幅2〜3μmのアルミニウム配線2を形成し
た図で、形成法は前記)J法と同じである。次いで、第
3図に示すようにCVD法によって膜厚数1000人(
0,2〜1μm)のpsc膜4を被着する。CVD法で
全方向から被着ずれば、被覆性が良(てアルミニウム配
線2側面の隅部骨も十分に埋められる。その場合、前記
の様にアルミニウム配線2の側面には境界線が生じるこ
とは云うまでもない。
2 to 5 show step-by-step cross-sectional views of the forming method according to the present invention. In FIG. In this figure, an aluminum wiring 2 having a width of 2 to 3 μm is formed, and the formation method is the same as the J method described above. Next, as shown in Figure 3, a film thickness of several thousand layers (
A psc film 4 of 0.2 to 1 μm) is deposited. If it is deposited from all directions using the CVD method, the coverage will be good (and the corner bones on the sides of the aluminum wiring 2 will be sufficiently filled in. In that case, a boundary line will appear on the side of the aluminum wiring 2 as described above). Needless to say.

次いで、第4図に示すように全面のPSG膜を異方性1
−ノチング(トライエツチング)によってエツチングし
、アルミニウム配線2の側面にのみPSGllW4を残
存させる。エツチング剤はトリフロロメタン(CIIF
3)と四弗化メタン(C1i4 )との混合ガスを用い
る。ごの時、表面から一様にエツチングするたりて、十
分厚く被着しているアルミニウム配線の側面部のみにP
SG膜4を残存させることかできる。
Next, as shown in FIG. 4, the entire PSG film is anisotropically
- Etching is performed by notching (tri-etching) to leave PSGllW4 only on the side surfaces of the aluminum wiring 2. The etching agent is trifluoromethane (CIIF
3) and tetrafluoromethane (C1i4) is used. When etching the aluminum wiring uniformly from the surface, apply P only to the sides of the aluminum wiring that is sufficiently thickly coated.
It is possible to leave the SG film 4.

かくして、PSG膜4の膜厚をコントロールすれば、そ
の残存量を調節することが可能である。
Thus, by controlling the thickness of the PSG film 4, it is possible to adjust its remaining amount.

また、PSG膜のような絶縁膜では、そのエツチング量
をもコントロールし、必ずしも平面上のPSG膜4を全
部除去する必要はない。
Further, in the case of an insulating film such as a PSG film, the amount of etching is also controlled, and it is not necessarily necessary to completely remove the PSG film 4 on the plane.

次いで、第5図に示すように再びCVD法によって膜厚
数1000人のPSG膜5を被着する。そうすると、ご
のPSG膜5は不連続線が現れず、アルミニウム配線2
を完全に被覆して保護し、アルミニウム配線の酸化が防
止される。
Next, as shown in FIG. 5, a PSG film 5 with a thickness of several thousand layers is deposited again by the CVD method. In this case, discontinuous lines do not appear in the PSG film 5, and the aluminum wiring 2
This completely covers and protects the aluminum wiring, preventing oxidation of the aluminum wiring.

次に、第6図ないし第8図は本発明にかかる他の実施例
の工程順断面図である。本例では、第6図に示すように
予めパターンニングされた一フルミニウム配線2上に、
再度スパッタ法又は芸省法によって膜厚数1000人程
度O7ルミニウム膜12を破着する。次いで、第7図に
示すよ・うにアルミニウムIt!12全面を異方性エツ
チングによってエツチングし、アルミニウム配線2の側
面にのみ−rルミニウム膜12を残存させる。エツチン
グ剤は塩素(CI2 )系ガス、あるいは塩素化合物ガ
スである。
Next, FIGS. 6 to 8 are process-order sectional views of another embodiment according to the present invention. In this example, as shown in FIG.
The O7 aluminum film 12, which has a thickness of about 1000 layers, is broken again using the sputtering method or the Art Ministry method. Then, as shown in FIG. 7, aluminum It! The entire surface of the aluminum wiring 12 is etched by anisotropic etching, leaving the -r aluminum film 12 only on the side surfaces of the aluminum wiring 2. The etching agent is a chlorine (CI2) gas or a chlorine compound gas.

次いで、第8図に示すようにCV D法によってPSG
膜13を被着すると、このPSG膜13は不連続線がな
くて、アルミニウム配線2が完全に被覆されて保護され
る。本例は配線層と同し導電性膜を配線(yq面に形成
した実施例であるが、導電性膜はアルミニウムに限るも
のではなく、アルミニウム膜12の代わりに燐ドープ多
結晶シリコン膜をスパッタ法で被着して、四塩化炭素(
CC14) −1i体のガスでドライエツチングしても
良く、またタンゲステン等の金属を利用してもよい。
Next, as shown in FIG. 8, PSG was formed by CVD method.
When the film 13 is deposited, the PSG film 13 has no discontinuities and the aluminum wiring 2 is completely covered and protected. In this example, the same conductive film as the wiring layer is formed on the wiring (y-q plane), but the conductive film is not limited to aluminum, and instead of the aluminum film 12, a phosphorus-doped polycrystalline silicon film is sputtered. carbon tetrachloride (
CC14) -1i gas may be used for dry etching, or a metal such as tungsten may be used.

更に、絶縁保護膜はPSG膜のみならず、プラズマCV
D法で被着した窒化シリコン(SiN)膜あるいはオキ
シ窒化シリコン(SfON)膜を使用しても同様となる
Furthermore, the insulating protective film is not only a PSG film, but also a plasma CV film.
The same result can be obtained even if a silicon nitride (SiN) film or a silicon oxynitride (SfON) film deposited by the D method is used.

(f) 発明の効果 以上の説明から明らかなように、本発明によればアルミ
ニウム配線の断線を防止させて、ICの高信頼化に著し
く貢献するものである。
(f) Effects of the Invention As is clear from the above description, the present invention prevents disconnection of aluminum wiring and significantly contributes to higher reliability of ICs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のアルミニウム配線の断面構造図、第2図
〜第5図及び第6図〜第8図は本発明にかかる形成方法
の工程順断面図である。 図中、1は半導体基板、2はアルミニウム配線。 3.4,5.13はPSG膜、 12はアルミニウム膜
を示している。 第1図 第2図 第3図 第5図 第6閏 第7図 第8図
FIG. 1 is a cross-sectional structural view of a conventional aluminum wiring, and FIGS. 2 to 5 and 6 to 8 are step-by-step cross-sectional views of a forming method according to the present invention. In the figure, 1 is a semiconductor substrate and 2 is an aluminum wiring. 3.4 and 5.13 are PSG films, and 12 is an aluminum film. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Leap Figure 7 Figure 8

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に導体配線をパターンニングし、次いで絶
縁膜又は導電性膜を成長して前記導体配線を被覆した後
、異方性エツチングによって該絶縁膜又は導電性膜をエ
ツチングし、前記導体配線の両側に該絶縁膜又は導電性
膜を残存させる工程が含まれCなることを特徴とする半
導体装置の製造方法。
A conductor wiring is patterned on a semiconductor substrate, and then an insulating film or a conductive film is grown to cover the conductor wiring, and then the insulating film or conductive film is etched by anisotropic etching to remove the conductor wiring. A method for manufacturing a semiconductor device, comprising the step of leaving the insulating film or the conductive film on both sides.
JP23458083A 1983-12-12 1983-12-12 Manufacture of semiconductor device Pending JPS60124951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23458083A JPS60124951A (en) 1983-12-12 1983-12-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23458083A JPS60124951A (en) 1983-12-12 1983-12-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60124951A true JPS60124951A (en) 1985-07-04

Family

ID=16973239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23458083A Pending JPS60124951A (en) 1983-12-12 1983-12-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60124951A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386453A (en) * 1986-09-29 1988-04-16 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH01129440A (en) * 1987-11-14 1989-05-22 Fujitsu Ltd Semiconductor device
EP0349070A2 (en) * 1988-06-29 1990-01-03 Koninklijke Philips Electronics N.V. A method of manufacturing a semiconductor device
JPH07147332A (en) * 1994-08-01 1995-06-06 Fujitsu Ltd Manufacture of semiconductor device
JPH07147333A (en) * 1994-08-01 1995-06-06 Fujitsu Ltd Semiconductor memory device and its manufacture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386453A (en) * 1986-09-29 1988-04-16 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH01129440A (en) * 1987-11-14 1989-05-22 Fujitsu Ltd Semiconductor device
EP0349070A2 (en) * 1988-06-29 1990-01-03 Koninklijke Philips Electronics N.V. A method of manufacturing a semiconductor device
EP0349070B1 (en) * 1988-06-29 1994-11-30 Koninklijke Philips Electronics N.V. A method of manufacturing a semiconductor device
JPH07147332A (en) * 1994-08-01 1995-06-06 Fujitsu Ltd Manufacture of semiconductor device
JPH07147333A (en) * 1994-08-01 1995-06-06 Fujitsu Ltd Semiconductor memory device and its manufacture

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