JPS60124842A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60124842A
JPS60124842A JP58232506A JP23250683A JPS60124842A JP S60124842 A JPS60124842 A JP S60124842A JP 58232506 A JP58232506 A JP 58232506A JP 23250683 A JP23250683 A JP 23250683A JP S60124842 A JPS60124842 A JP S60124842A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor device
manufacturing
orientation
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58232506A
Other languages
Japanese (ja)
Inventor
Koichi Sekine
弘一 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58232506A priority Critical patent/JPS60124842A/en
Publication of JPS60124842A publication Critical patent/JPS60124842A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To prevent deterioration of performance characteristics and to improve a poor yield by a method wherein the short side and the long side of a rectangular semiconductor device run parallel with specified orientations and the nest of such lattice defects as slips overlaps the useless region of a wafer. CONSTITUTION:The long side or the short side of a CCD line sensor 211-21n, 221-22n is arranged to be in parallel with an orientation (010) and the other side in parallel with an orientation (001), whereafter a pattern is drawn on the primary plane (100) of an Si wafer 1, an integrated circuit is formed, and then the Si wafer 1 is divided into chips. In this method, a region a1-a4 is located on the useless region (whereon no chips are formed) of the Si wafer 1. An orientation flat 3 is positioned on a plane (011) prone to cleavage.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法罠関し、特にＣＣＤライ
ンセンサやエリアセンサの如き長寸法のデバイスの製造
工程に使用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and is particularly used in the manufacturing process of long devices such as CCD line sensors and area sensors.

〔発明の技術的背景〕[Technical background of the invention]

半導体装置を製造する際に（１００）面を主表面とする
半導体ウェーハ（例えばＳｉウェーハ）を使用すると、
表面準位が少し高性能の素子特性が得られることは、特
公昭４２−２１４４６．２１９７５．２１９７６等によ
り従来から知られている。そして、これはラインセンサ
、エリアセンサ等の長寸法の半導体装置についても同様
である。When a semiconductor wafer (for example, a Si wafer) whose main surface is the (100) plane is used when manufacturing a semiconductor device,
It has been known from Japanese Patent Publication No. 42-21446.21975.21976 that surface states can provide slightly higher performance device characteristics. The same applies to long semiconductor devices such as line sensors and area sensors.

添付図面の第１図を参照して従来技術を説明する。第１
図はＣＣＤラインセンサを主表面に形成したＳｉウェー
ハの平面図である。なお、以下の図面の説明において同
一要素は同一符号で示しである。主表面が（１００）面
のＳｉウェーハ】には、長寸法のＣＣＤラインセンサ２
．１〜２□。、２□、〜２□。The prior art will be described with reference to FIG. 1 of the accompanying drawings. 1st
The figure is a plan view of a Si wafer on which a CCD line sensor is formed on the main surface. In addition, in the following description of the drawings, the same elements are indicated by the same reference numerals. [Si wafer whose main surface is the (100) plane] has a long CCD line sensor 2.
．． 1~2□. , 2□, ~2□.

が形成されている。また、オリエンテーションフラット
３はへき開容易な（０１１）面に設けられている。is formed. Further, the orientation flat 3 is provided on the (011) plane that is easy to cleave.

ここで、ＣＣＤラインセンサ２１１〜２１ｎＩ２２１〜
２□。は、ファックス用として用いるものでは長辺が約
３０ｍｍ、短辺か約１〜２ｍｍとなるので、８１ウエー
ハ１上では図示の如く２列に配置されることＫなる。Here, CCD line sensor 211~21nI221~
2□. When used for fax, the long side is about 30 mm and the short side is about 1 to 2 mm, so on the 81 wafer 1 they are arranged in two rows as shown in the figure.

〔従来技術の問題点〕[Problems with conventional technology]

ところで、Ｓｉウェーハ１を熱処理するとスリップと呼
ばれる結晶欠陥がウェーハ周辺部で発生し、これが第１
図の斜線で示す領域ａ０〜ａ４に集中しやすいという傾
向がある。従って、この（０１０）。By the way, when the Si wafer 1 is heat-treated, crystal defects called slips occur at the periphery of the wafer.
There is a tendency to concentrate in areas a0 to a4 indicated by diagonal lines in the figure. Therefore, this (010).

（００１）向の４偶の領域に形成されたＣＣＤイメージ
センサ２１１１２１゜、２□０，２□。等では暗電流が
局所的に増大し、白キズと呼ばれる画像欠陥を生じるな
ど、画質の劣化と歩留シの低下がもたらされる。特に、
ＣＣＤラインセンサ、ＭＯ８形ラインセンサ、エリアセ
ンサ等の如きデバイスでは、寸法が特異なのでこの傾向
が著しい。CCD image sensors 211121°, 2□0, 2□ formed in four even areas in the (001) direction. etc., the dark current increases locally, causing image defects called white scratches, resulting in deterioration of image quality and reduction in yield. especially,
This tendency is remarkable in devices such as CCD line sensors, MO8 type line sensors, area sensors, etc. because of their unique dimensions.

〔発明の目的〕[Purpose of the invention]

本発明は上記の従来技術の欠点を克服するためになされ
たもので、半導体ウェーハにスリップ等の格子欠陥が発
生した場合にも、このウェーハで製造した半導体装置の
性能を劣化させることが少くかつ歩留りを低下させるこ
とも少くし半導体装置の製造方法を提供することを目的
とする。The present invention has been made to overcome the above-mentioned drawbacks of the prior art, and even when lattice defects such as slips occur in a semiconductor wafer, the performance of semiconductor devices manufactured using this wafer is less likely to deteriorate. It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the reduction in yield.

〔発明の概要〕[Summary of the invention]

上記の目的を実現するため本発明は、主表面が（ｉｏｏ
）面の半導体ウェーハによって長方形状（正方形を含む
）の半導体装置を製造するＫあたって、長方形状の短辺
、長辺が（０１０）、　（００１）方位に平行になるよ
うにした半導体装置の製造方法を提供するものである。In order to achieve the above object, the present invention provides that the main surface is (ioo
) to manufacture rectangular (including square) semiconductor devices using semiconductor wafers, the short and long sides of the rectangle are parallel to the (010) and (001) directions. A manufacturing method is provided.

〔発明の実施例〕[Embodiments of the invention]

以下、添付図面の第２図および第３図を参照して本発明
のいくつかの実施例を説明する。第２図は一実施例に係
る製造方法によってＣＣＤラインセンサを主表面に形成
したＳｉウェーハの平面図である。第１図に示す従来の
ものに対して、パターンを４５°だけ回転させ、ＣＣＤ
ラインセンサ２．１〜２□。、２□１〜２□。の長辺も
しくは短辺の一方が（０１０）方位に平行になり、他方
が（００１）方位に平行になるようにする。このように
してＳｉウェーハ１の（１００）主表面にパターンを描
き、集積回路を形成し、チップに分割すると、Ｓｉウェ
ーハ１の無効領域（チップが形成されない領域）にスリ
ップの多く発生している領域ａ０〜ａ４が重なることＫ
なる。なお、オリエンテーションフラット３はへき開の
容易な（０１１）面に設けられている。Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 2 and 3 of the accompanying drawings. FIG. 2 is a plan view of a Si wafer on which a CCD line sensor is formed on the main surface by a manufacturing method according to an embodiment. The pattern is rotated by 45 degrees compared to the conventional one shown in Figure 1, and the CCD
Line sensor 2.1-2□. , 2□1-2□. One of the long sides or short sides of is parallel to the (010) direction, and the other is parallel to the (001) direction. When a pattern is drawn on the (100) main surface of the Si wafer 1 in this way, an integrated circuit is formed, and it is divided into chips, many slips occur in the inactive area (area where chips are not formed) of the Si wafer 1. Areas a0 to a4 overlap K
Become. Note that the orientation flat 3 is provided on the (011) plane that can be easily cleaved.

第２図は他の実施例に係る製造方法によってＣＣＤライ
ンセンサを主表面に形成したＳｉウェーハの平面図であ
る。図示の如くオリエンテーション３を（ｏｏｉ）面に
設け、これを基準にマスク位置合せ、スクライビング、
等を行う。なお、（００１）面は（０１１）面に比べる
とへき開が容易ではないが、よシ深くスクライブするこ
とによって容易にへき開できる。FIG. 2 is a plan view of a Si wafer with a CCD line sensor formed on its main surface by a manufacturing method according to another embodiment. As shown in the figure, orientation 3 is provided on the (ooi) plane, and mask alignment, scribing, and
etc. Although the (001) plane is not as easy to cleave as the (011) plane, it can be easily cleaved by scribing more deeply.

ナオ、オリエンテーションフラットは（０１０）面に設
けるようにしてもよい。また、製造する半導体装置は長
方形状の細長いラインセンサに限らず、長方形状（正方
形を含む）のエリアセンサでもよい◎ 〔発明の効果〕 上記の如く本発明によれば、主表面が（１００）面の半
導体ウェーハによって長方形状の半導体装置を製造する
にあたって、長方形の長辺、短辺が（０１０）、　（０
０１）方位に平行になるようにしたので、スリップ等の
格子欠陥の多く発生する領域とウェーハの無効領域を重
ねることができ、半導体装置の性能を劣化させたり歩留
シを低下させたりすることの少い半導体装置の製造方法
が得られる。However, the orientation flat may be provided on the (010) plane. Further, the semiconductor device to be manufactured is not limited to a rectangular elongated line sensor, but may also be a rectangular (including square) area sensor. [Effects of the Invention] As described above, according to the present invention, the main surface is (100) When manufacturing a rectangular semiconductor device using a flat semiconductor wafer, the long and short sides of the rectangle are (010) and (0
01) Since the orientation is parallel to the direction, the area where many lattice defects such as slips occur and the invalid area of the wafer can overlap, which can degrade the performance of semiconductor devices and reduce yield. Thus, a method for manufacturing a semiconductor device can be obtained.

また、オリエンテーションフラット＆　（００１）方位
もしくは（ｏｉｏ）方位と平行にすることにより、マス
ク位置合せ、スクライビングの位置合せ等を容易にする
ことができる。さらに、端部に形成されたチップがオリ
エンテーションフラットによυ欠けてしまう欠点（第２
図のＣＣＤラインセンサ２、。）をなくすことができる
。Further, by making the orientation flat & parallel to the (001) direction or (oio) direction, mask alignment, scribing alignment, etc. can be facilitated. Furthermore, the chip formed at the end is chipped due to the orientation flat (second
CCD line sensor 2 in the figure. ) can be eliminated.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来方法に係る半導体ウェーハの平面図、第２
図は本発明の一実施例に係る半導体ウェーハの平面図、
第３図は本発明の他の実施例に係る半導体ウェーハの平
面図である。 １・・・半導体ウェーハ、 ２□、〜２、□、２□１〜２□。・・・ＣＣＤラインセ
ンサ、３・・・オリエンテーションフラット面。 （７）Figure 1 is a plan view of a semiconductor wafer according to the conventional method;
The figure is a plan view of a semiconductor wafer according to an embodiment of the present invention.
FIG. 3 is a plan view of a semiconductor wafer according to another embodiment of the present invention. 1... Semiconductor wafer, 2□, ~2,□, 2□1-2□. ... CCD line sensor, 3... Orientation flat surface. (7)

Claims (1)

【特許請求の範囲】 １、主表面が（１００）面である半導体ウェーハに集積
回路を形成し、該半導体ウェーハを長方形状のチップに
分割する半導体装置の製造方法において、 前記長方形状の長辺もしくは短辺の一方を（０１０）方
位に平行にすると共に他方を（００１）方位に平行にし
、前記チップごとに分割することを特徴とする半導体装
置の製造方法。 ２、前記チップはラインセンサである特許請求の範囲第
１項記載の半導体装置の製造方法。 ３、前記チップはエリアセンサである特許請求の範囲第
１項記載の半導体装置の製造方法。 ４、主表面が（１００）面である半導体ウェーハに集積
回路を形成し、該半導体ウェーハを長方形状のチップに
分割する半導体装置の製造方法において、 前記半導体ウェーハの（０１０）方位もしくは（００１
）方位のいずれか一方と平行にオリエンテーションフラ
ット面を形成し、前記長方形状の長辺もしくは短辺の一
方を（０１０）方位に平行にすると共に他方を（００１
）方位に平行にし、前記チップごとに分割することを特
徴とする半導体装置の製造方法。 ５、前記チップはラインセンサである特許請求の範囲第
４項記載の半導体装置の製造方法。 ６、前記チップはエリアセンサである特許請求の範囲第
４項記載の半導体装置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device in which an integrated circuit is formed on a semiconductor wafer whose main surface is a (100) plane, and the semiconductor wafer is divided into rectangular chips, comprising: Alternatively, one of the short sides is made parallel to the (010) direction and the other short side is made parallel to the (001) direction, and the semiconductor device is divided into chips. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the chip is a line sensor. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the chip is an area sensor. 4. A method for manufacturing a semiconductor device in which an integrated circuit is formed on a semiconductor wafer whose main surface is a (100) plane, and the semiconductor wafer is divided into rectangular chips, the semiconductor wafer having a (010) orientation or a (001) orientation.
) direction, one of the long sides or short sides of the rectangular shape is made parallel to the (010) direction, and the other side is made parallel to the (001) direction.
) A method for manufacturing a semiconductor device, characterized in that the semiconductor device is divided into chips parallel to the direction. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the chip is a line sensor. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the chip is an area sensor.
JP58232506A 1983-12-09 1983-12-09 Manufacture of semiconductor device Pending JPS60124842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58232506A JPS60124842A (en) 1983-12-09 1983-12-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58232506A JPS60124842A (en) 1983-12-09 1983-12-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60124842A true JPS60124842A (en) 1985-07-03

Family

ID=16940392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58232506A Pending JPS60124842A (en) 1983-12-09 1983-12-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60124842A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009130128A (en) * 2007-11-22 2009-06-11 Denso Corp Dividing method of wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009130128A (en) * 2007-11-22 2009-06-11 Denso Corp Dividing method of wafer

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