JPS60124121A - Driving circuit of power mos field effect transistor - Google Patents

Abstract

PURPOSE:To supply a precise control pulse to a P-MOSFET by providing a floating circuit formed by a coupling transformer, etc. with a buffer TRs having low impedance. CONSTITUTION:When a control pulse A is outputted from a PWM circuit 3, a pulse B is applied from a driving TRT10 to a floating circuit through a coupling transformer CT and used as power supply rectified and smoothed by a capacitor C10 to the buffer TRs T11, T12. The pulse B turns on and off the TRs T11, T12 and makes spike-like current i1, i2 for charging and discharging the gate capacity of the P-MOSFETQ1 flow to turn on and off the FETQ1, but the voltage of the capacitor C10 is kept at a fixed level because the currents i1, i2 are fine and the gate voltage E can be kept at a prescribed value for an ON period. In addition, the FETQ2 can be also controlled by a driving circuit with a floating constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit for a power MOS field effect transistor, and more particularly to a drive circuit suitable for a switching regulator etc. that operates a power MOS field effect transistor. It is something.

[Background technology and its problems]

In recent years, Power MOS! , field effect transistor (hereinafter,
Single-VcP-MOS transistors) are capable of high-speed switching operations, and have also been commercialized. Therefore, in addition to power transistors in conventional audio power amplifiers, they are also used as switching elements in switching regulators, etc. Figure 1 is a circuit diagram showing an example of a HAR abscisin type switching regulator using a P-MOS (P-MOS) transistor. The output of the switched power supply 1 is formed by a rectifier circuit 1c, etc., and is supplied to a Herabsisine type DC-AC conversion circuit consisting of PMOS transistors Q, , Q, capacitors C+, C*, and a transformer T. I'm in the middle of the day.

2 is a drive circuit that supplies control pulses that alternately switch the P-MO8) transistors Q, , Q, and the pulse width of the control pulses is determined by a pulse modulation circuit.
It is controlled by a PWM circuit 3.

In addition, 4 is Stark, 5 is front BC drive circuit 2゜PW
A rectifier circuit 6 forms an operating power source for the M circuit 3, and a rectifier circuit 6 connects the alternating signal output from the transformer TK to diodes D+ and D2.
This is a detector that generates a control signal proportional to the DC output obtained by rectifying the DC output.

In this switching regulator, the control pulses P1 and P2 shown in FIG. Child T. You can get K.

Therefore, the pulse width of the control pulses P+ and P2 (
If 1) is controlled by the PWM circuit 3 according to the DC output, the DC output will always be constant from fO to 5.

By the way, switching is 71 P-MOS +.
Regarding the transistors Q and K, their source electrodes are at two-keying potential (responses for the voltage to be switched), so the circuit that drives these transistors 71 must also be a floating circuit.

Figure 3(a) shows the control voltage (P) from the coupling transformer CTK.
,yt shows an example of a drive circuit in which off-setting is performed. When a control pulse P1 is applied to the base of the drive transistor Tr+, a floating control pulse P is supplied between the gate and source of the P-MO8 transistor Q1. I will. In this case, the capacitive load C between the gate and source of P-MO8) transistor Q is approximately 2000PF.
Since L is the same, the equivalent circuit seen from the secondary side of the coupling transformer CT is K as shown in FIG. 3(b). In this circuit, the control pulse P1 is supplied with a low impedance between the gate and the source at the rising edge of the control pulse P1, but at the falling edge of the control pulse P, the diode D is turned off (the drive transistor R1 is turned off). Since the impedance state becomes low, which indicates OFF, the charge level of the capacitive load CL is attenuated by the time constant CL:R, as shown in Fig. 3 (
As shown in the waveform section c), the falling edge is blunted. Therefore, during the hatched period, the other P-MO8) transistor Q2t cannot be controlled to be on, resulting in a narrow control range and a marked deterioration in the efficiency of the switching regulator.

Therefore, a method can be considered in which the drive transistors Tr+ to Tr4Y are connected in a push-pull manner and the control pulse P1 is supplied via the coupling transformer CTY, as shown in FIG. 4(a). In this method, the control pulse P1 is always supplied by the ON state of the drive transistors Tr, .Tri+ or Trz.Tr4, so its equivalent circuit is
As shown in Figure (b), it is possible to obtain a steep pulse waveform for both the rise and fall.If the influence of the coupling transformer CT ratio and the cage inductance L6 is multiplied by 5, the waveform as shown in Figure 4 (c) K can be obtained. Ringing occurs at the rising and falling points, and as in the case of FIG. 3(a), there is a problem in that the control range is narrowed and at the same time, the efficiency of the switching regulator is reduced.

[Purpose of the invention]

This invention was made in view of the actual situation,
By providing a low impedance buffer transistor in the t'7C floating circuit formed by a coupling transformer, a drive circuit is provided that can supply accurate control pulses to the P-MO8) transistor. It is something to do.

[Summary of the invention]

In order to achieve the above object, the present invention provides a rectifier circuit for rectifying the control pulse on the secondary side of a coupling transformer to which the control pulse is supplied, and the rectifier circuit rectifies the control pulse.
The DC voltage is used as an operating power source for the complementary-connected buffer transistors, the buffer transistors are driven by the control pulse, and the output thereof drives the P-MO transistor (8).

Therefore, a low impedance buffer amplifier is formed in the floating drive circuit, making it possible to supply a control pulse with a predetermined pulse width to the goat electrode of the P-MO8) Ranjisk. .

〔Example〕

FIG. 5 shows a drive circuit for a P-MOS transistor according to the present invention, where 3 is the PWM circuit described above, Lo is a drive transistor, and CT is a coupling transformer. The part surrounded by the dashed line is the floating drive circuit for the PMOS) transistor Q! show,
D,,,C,. are a diode and a capacitor %TIIIL, which constitute a rectifier circuit, are complementary buffer transistors, R1° and OlI are K-th resistors and diodes s that supply base current, and R11+R12 are gate bias resistors.

Complementary type buffer transistor T! I
+Tax is provided.

Next, the operation of this drive circuit will be explained with reference to the waveforms shown in FIG. Control pulse P output from PWM circuit 3
1 is a drive transistor T.

The waveform BK is supplied to the floating circuit through the coupling transformer 0 as shown in the waveform BK. And diode D,
. As a result, the capacitor C+o is charged to the peak value of the control pulse P1, and this charging voltage serves as the operating power source for the buffer transistor T++ + T+*. -MOS) V supplied to the gate of transistor Q1. At this time, the capacitive load of the gate electrode (
CL) K is a spike-like 'K a as shown in the waveform DK.
i 1 flows, but the power consumption at this time is extremely small. Therefore, the capacitor C1 of the rectifier circuit
The terminal voltage of ゜ is kept almost constant, P-MOS) transistor Q.

The gate voltage control pulse P and the on-period waveform EK of can be maintained at a predetermined value as shown.

Next, when the control pulse P falls, one buffer transistor 711 is turned off, and at the same time the other buffer transistor TI2 is turned on, causing a leak-like current to flow from the capacitive load (CL) of the gate electrode. i, flows. Therefore, the gate voltage of the P-MOS transistor decreases rapidly, becomes the same potential as the source electrode, and is turned off.

Since the drive circuit of the present invention operates in the same manner as described above, the control pulses P and Y, which rise and fall quickly by the buffer transistors T++, T12Ill, P-MOS, which is at a floating potential, transistor Q,
can be supplied to the gate. In this case, the operating voltage Oλ supplied to the buffer transistor Tl1lTI2 is obtained by rectifying the control pulse P
This configuration has the effect of eliminating the need for a third power source that is connected to a 70-channel power source.

Note that the p-MOS transistor Q is directly driven by the control pulse P2 to the buffer 7 and transistor T21.
+ Switching can be performed by driving T22, but this P-MOS) transistor Q2vc is also connected to the coupling transformer CI! It is controlled by a drive circuit with a floating circuit configuration as described above.
It's okay. In this case, there is an effect that the PWM circuit 3 and the P, MOS transistor Q 2 (Q,') can be completely isolated in terms of direct current.

〔Effect of the invention〕

As explained above, the P-MOS transistor drive circuit of the present invention focuses on the fact that since the gate of the P-MOS transistor is formed with a capacitive load, the average DC current during drive is extremely small. The power is obtained by rectifying the peak value of the control pulse.

Therefore, there is an advantage that the buffer transistor 7 can be used to prevent the rise and fall characteristics of the control pulse from deteriorating in the floating circuit, and the switching of the P-MOS transistor can be performed reliably.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a switching regulator as an example to which the drive circuit of the present invention can be applied, Figure 2 is a control pulse waveform diagram, and Figure 3i:1J(a) is an example of a floating drive circuit. conventional circuit diagram,
Figure 3(b) is an equivalent circuit diagram of Figure 3(a), and Figure 3(c) is an equivalent circuit diagram of Figure 3(a).
) is a waveform diagram of the control pulse output from the circuit of 3j5(a), FIG. 4(a) is a circuit diagram showing another example of a floating drive circuit, and FIG. 4(b) is a diagram of the control pulse output from the circuit of Diagram (a)
Equivalent circuit diagram of FIG. 4 (cl is a waveform diagram of the control pulse outputted by the circuit of FIG. 4(a), #!5 is a wiring diagram of the drive circuit shown in one embodiment of the present invention), fR6 The figure is number 5
FIG. 3 is a waveform diagram of the main part of the figure. In the figure, CT is a coupling transformer, D. IC+. are the diodes and capacitors that make up the rectifier circuit, Tit +T□
are buffer transistors with different conduction types Qs,
Q indicates a power MOS field effect transistor. Figure 2 Figure 3 (6) (b) n. Figure 4

Claims (1)

[Claims] A rectifier circuit for rectifying the control pulse is provided on the secondary side of the coupling transformer to which the control pulse is supplied, and the DC voltage obtained by the rectifier circuit is connected to a buffer that is prementionally connected. - A drive circuit for a power MOS field effect transistor, characterized in that it serves as an operating power source for the transistor, drives the hump 7 transistor with the control pulse, and drives a power MOS field effect transistor with its output.