JPS60123967A - Analog multiplier circuit - Google Patents

Analog multiplier circuit

Info

Publication number
JPS60123967A
JPS60123967A JP58232357A JP23235783A JPS60123967A JP S60123967 A JPS60123967 A JP S60123967A JP 58232357 A JP58232357 A JP 58232357A JP 23235783 A JP23235783 A JP 23235783A JP S60123967 A JPS60123967 A JP S60123967A
Authority
JP
Japan
Prior art keywords
analog
signal
digital
input
analog signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58232357A
Other languages
Japanese (ja)
Inventor
Akira Matsuo
松尾 暁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58232357A priority Critical patent/JPS60123967A/en
Publication of JPS60123967A publication Critical patent/JPS60123967A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06GANALOGUE COMPUTERS
    • G06G7/00Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To simplify the constitution and reduce the cost of an analog multiplier circuit, by supplying an input analog signal to the reference voltage input terminal of an digital-to-analog converter and a digital signal to be multiplied to the digital signal input terminal of the converter. CONSTITUTION:Correcting value information read out from a ROM10 is introduced to the digital signal input terminal of a D/A converter 20 and, at the same time, an analog signal IS before multiplication correction is introduced to the full scal adjustment terminal BI of the converter 20. An analog output signal corresponding to the value which is equal to the analog signal IS multiplied by the correcting value information is outputted from the output terminal OUT of an output arithmetic amplifier OP as a corrected analog signal.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、例えば光学式情報読取装置のシェーディング
補正用として井芒セ壬用いられる乗算回路のように、ア
ナログ信号に予め定めておいたデジタル補正信号を乗算
して、その乗算結果を補正済のアナログ信号として出力
する乗算回路の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital correction method predetermined for an analog signal, such as a multiplication circuit used for shading correction in an optical information reading device, for example. The present invention relates to an improvement in a multiplication circuit that multiplies signals and outputs the multiplication result as a corrected analog signal.

〔発明の技術的背景〕[Technical background of the invention]

一般に、ファクシミリ読取装置Leのような光学式情報
読取装置では、光源の照明やレンズ等の光学系の光通過
量が位置により変化し、また固体撮謙素子等の光センサ
の受光特性に素子間のバラツキがちるため、これらを補
正して位置的に均一な読取信号を得る必要がある。この
だめ、従来では、光センサへの受光路中にシェーディン
グ板と呼ばれる受光光量補正部材を設けたシ、あるいは
光センサの負荷抵抗を各素子毎に異ならせて出力信号を
補正する等の対策が講じられているが、近年注目されて
いる補正手段として、光センサの出力信号に予め設定し
ておいた補正係数を乗算して補正するものがある。第1
図は、その構成の一例を示すもので、この回路は光セン
サの各素子で得られた光検出信号を先ずアナログデジタ
ル変換回路(A/D ) 1でデジタル信号に変換し、
このデジタル化信号をリード・オンリー・メモ!I (
Rou)zに記1意しておいた補正係数情報とデジタル
乗算器3で乗算して、その乗算結果をデジタルアナログ
変換回路(D/A)4によシアナログ信号に変換して補
正済の光検出信号を得るように構成されている。このよ
うな回路であれば、光源の照明強度および光学系の元通
過滑の位置的不均一をはじめ、受光素子kl丼的に補止
することができ、しかも元センサの各受光素子単位で精
度の良い補正を行なえる利点がある。
In general, in optical information reading devices such as the facsimile reading device Le, the illumination of the light source and the amount of light passing through the optical system such as the lens change depending on the position, and the light receiving characteristics of the optical sensor such as the solid-state sensor vary depending on the distance between the elements. Since there are variations in the values, it is necessary to correct these to obtain a positionally uniform read signal. To avoid this, conventional countermeasures have been taken, such as installing a received light amount correction member called a shading plate in the light receiving path to the optical sensor, or correcting the output signal by varying the load resistance of the optical sensor for each element. However, as a correction means that has received attention in recent years, there is a method that corrects the output signal of an optical sensor by multiplying it by a preset correction coefficient. 1st
The figure shows an example of its configuration. This circuit first converts the photodetection signal obtained from each element of the optical sensor into a digital signal using an analog-to-digital conversion circuit (A/D) 1.
Read-only memo with this digitized signal! I (
Rou) The digital multiplier 3 multiplies the correction coefficient information written in z, and the multiplication result is converted into a digital analog signal by the digital-to-analog conversion circuit (D/A) 4 to produce the corrected signal. The device is configured to obtain a photodetection signal. With this type of circuit, it is possible to compensate for positional non-uniformity in the illumination intensity of the light source and the optical system's original slippage, as well as for each light-receiving element. It has the advantage of being able to perform good correction.

〔背景技術の問題点〕 ところが、このような従来の回路は、光センサのアナロ
グ信号出力を一旦デジタル信号に変換し、乗算ののちア
ナログ信号に戻すものであるため、A/D変換回路1や
D/A 11換回路4を必やとし、さらには一般に高価
で複雑なデジタル乗算器を使用することから、構成が著
しく複雑で、また高価となる欠点があった。
[Problems with the Background Art] However, such conventional circuits first convert the analog signal output of the optical sensor into a digital signal, and then convert it back to an analog signal after multiplication. Since it requires a D/A 11 conversion circuit 4 and generally uses an expensive and complicated digital multiplier, it has the disadvantage that the configuration is extremely complicated and expensive.

〔発明の目的〕[Purpose of the invention]

本発明は、構成が1111単で安価なアナログ乗算回路
を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive analog multiplication circuit with a simple configuration.

〔発明の概要〕[Summary of the invention]

本発明は、上記目的を達成するために、栽準電圧に従っ
て入力デジタル信号をアナログ信号に変換するデジタル
アナログ牙換回路を設け、このデジタルアナログ変映回
路のへ準屯圧入力端子に入力アナログ信号を供給すると
ともに、デジタル信号入力端子に乗算すべきデジタル信
号を供給して、アナログ信号出力端子から上記入力アナ
ログ信号とデジタル信号との乗算値に相当するアナログ
信号を得るようにし、これによりA/D変換回路や高価
なデジタル乗算器を不要にしたものである。
In order to achieve the above object, the present invention provides a digital-to-analog conversion circuit that converts an input digital signal into an analog signal according to a standard voltage, and inputs an input analog signal to a standard voltage input terminal of the digital-to-analog conversion circuit. At the same time, a digital signal to be multiplied is supplied to the digital signal input terminal, and an analog signal corresponding to the multiplication value of the input analog signal and the digital signal is obtained from the analog signal output terminal. This eliminates the need for a D conversion circuit or an expensive digital multiplier.

〔発明の実施例〕[Embodiments of the invention]

第2図は本発明の一実施例における乗算回路の回路構成
図で、図中10はリード・オンリー・メモリ(Rou)
、2oはデジタル・アナログ変換回路(D/A 9換回
路)をそれぞれ示している。ROIJ70は、乗算情報
として、例えば光学式情報読取装置のシェーディング補
正値を6ビツトのデジタル16報として記憶したもので
、ト1示しない制御回路からのアドレス指定および読出
し指令に応じて上記補正値情報を読出すものとなってい
る。
FIG. 2 is a circuit configuration diagram of a multiplication circuit in an embodiment of the present invention, and 10 in the figure is a read-only memory (Rou).
, 2o indicate digital-to-analog conversion circuits (D/A 9-conversion circuits), respectively. The ROIJ 70 stores, for example, shading correction values of an optical information reading device as multiplication information as 16 6-bit digital reports. It is designed to read out.

一方、D/A変換回路20は、6ビツトノ(イナリコー
ドのデジタル信号をアナログ出力電圧信号Kf換するも
ので、変換時の基準電圧を指定するための、いわゆるフ
ルスケール調整端子BIを有している。なお、V−、V
+は゛電源電圧、入力端子、V/Uはバイポーラ・ユニ
ポーラ切換入力端子、工人は電流加算入力<111^子
、SLは出力電圧レンジ(フルスケールレンジ)設定用
端子をそれぞれ示している。
On the other hand, the D/A conversion circuit 20 converts a 6-bit (inari code) digital signal into an analog output voltage signal Kf, and has a so-called full scale adjustment terminal BI for specifying a reference voltage at the time of conversion. In addition, V-, V
+ indicates the power supply voltage, input terminal, V/U indicates the bipolar/unipolar switching input terminal, "Skill" indicates the current addition input <111^, and SL indicates the output voltage range (full scale range) setting terminal.

そして、このようなり/A変換回路20は、デジタル信
号入力端子(6ビツト)に、前記ROVLIOから読出
された補正値情報を導入するとともに、フルスケール調
整端子BIに乗算補正前のアナログ信号ISを導入し、
出力演算増幅器OPの出力端1子OUTより上記アナロ
グ信号Isに補正値情報を乗算した値に相当するアナロ
グ出力信号を袖肥後のアナログ信号として出力している
Then, the A/A conversion circuit 20 inputs the correction value information read from the ROVLIO to the digital signal input terminal (6 bits), and inputs the analog signal IS before multiplication correction to the full scale adjustment terminal BI. introduced,
An analog output signal corresponding to the value obtained by multiplying the analog signal Is by the correction value information is outputted from the output terminal OUT of the output operational amplifier OP as an analog signal of Sodehigo.

このような構成で・らるから、レリえば光セン→ノ〜の
走査制御動作に同期して光センサの位11ηに対応する
補正値情報をROM 10から順次T’j;l出し、D
/A変換回路20のデジタル信号入力端子M3B。
With such a configuration, the correction value information corresponding to the position 11η of the optical sensor is sequentially output from the ROM 10 in synchronization with the scanning control operation of the optical sensor →
/A conversion circuit 20 digital signal input terminal M3B.

2nd、 3rdl 4t、h l 5tb l LS
B に供給すると、これらの補正値情報はアナログ値に
変換される際に、フルスケール調整端子BIに供給され
るブ0センサの受光出力信号(アナログ信号)工Sの大
きさに応じてあたかも変換係数が付与されることになり
、この結果出力演算増幅器OPの出力端子OUTからは
結果的に前記受光出力信号ISとデジタル補正値情報と
の乗算値に相当するアナログ信号が出力されることにな
る。したがって、@記補正値情報を光源の照度や光学系
の光通過量の位置的不均一および光センサの各素子間の
受光特性の不均一を全体的に均一にすべく、各受光素子
毎に予め設定し、ROMに記憶しておけは、光センサの
受光出力を各受光素子毎に補正し、全体的に均一化する
ことができる。つまり、前記第1図に示した回路と全く
同様にアナログ信号の補旧を行ない得る。
2nd, 3rdl 4t, h l 5tb l LS
When the correction value information is converted to an analog value, it is converted as if it were converted into an analog value according to the magnitude of the light reception output signal (analog signal) of the sensor S supplied to the full scale adjustment terminal BI. A coefficient is assigned, and as a result, an analog signal corresponding to the multiplication value of the received light output signal IS and the digital correction value information is output from the output terminal OUT of the output operational amplifier OP. . Therefore, in order to uniformize the illuminance of the light source, the positional non-uniformity of the amount of light passing through the optical system, and the non-uniformity of the light-receiving characteristics between each element of the optical sensor, the correction value information is If it is set in advance and stored in the ROM, the light receiving output of the optical sensor can be corrected for each light receiving element and made uniform overall. In other words, analog signals can be updated and updated in exactly the same way as the circuit shown in FIG.

しかも本実施例であれば、D/A変換回路2θをあたか
も乗算器として動作するように構成したので、A/D変
換回路や構成の複雑なデジタル来算器を不要にすること
ができ、この結果回路の4・+4成を大幅に簡略化し得
るとともに、安価な回路を提供できる。
Moreover, in this embodiment, since the D/A conversion circuit 2θ is configured to operate as if it were a multiplier, it is possible to eliminate the need for an A/D conversion circuit or a digital multiplier with a complicated configuration. As a result, the 4/+4 configuration of the circuit can be greatly simplified and an inexpensive circuit can be provided.

なお、本発明は上記実施例に限定されるものではなく、
例えば光センサの受光出力の補旧ばかシでなく、圧光セ
ンサやその他のセンサの検出出力の補正用として適用す
ることができ、さらにはただ単にアナログ信号とデジタ
ル信号との乗算を行なう場合にも適用できる。寸だ本発
明の応用例として、A/D変換回路のノ、(準電圧入力
端子にアナログ信号を供給し、これによシアナログ信号
どうしを乗算してその結果をデジタル信号として得るよ
うにしてもよい、。
Note that the present invention is not limited to the above embodiments,
For example, it can be used not only to correct the received light output of an optical sensor, but also to correct the detected output of a pressure sensor or other sensors, and even when simply multiplying an analog signal and a digital signal. can also be applied. As an application example of the present invention, an analog signal is supplied to the quasi-voltage input terminal of an A/D conversion circuit, and the quasi-analog signals are multiplied by each other to obtain the result as a digital signal. Good too.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように本発明は、基準電IEK従って入力
デジタル信号をアナログ信号に変換するデジタル・アナ
ログ変換回路を設け、このデジタル・アナログ変換回路
の栽xa t+τ圧入力端子に入力アナログ信号を供給
するとともに、デジタル信号入力端子に乗A、すべきデ
ジタル信号を供給して、アナログ信号出力端子から上記
アナログ信号とデジタル信号との乗算値にイ目当するア
ナログ信号を得るようにしたものである。
As described in detail above, the present invention provides a digital-to-analog conversion circuit that converts a reference voltage IEK, that is, an input digital signal, into an analog signal, and supplies an input analog signal to the input terminal of the digital-to-analog conversion circuit. At the same time, a digital signal to be multiplied by A is supplied to the digital signal input terminal, and an analog signal corresponding to the multiplication value of the analog signal and the digital signal is obtained from the analog signal output terminal. .

したがって、本発明であれば、構成が簡単で安価なアナ
ログ乗算回路を提供することができる。
Therefore, according to the present invention, it is possible to provide an analog multiplication circuit with a simple configuration and low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来における乗算回路のブロック構成図、第2
図は本発明の一実施例における乗算回路の回路構成図で
ある。 10・・・ROIJ、、20・・・D/A変換回路。
Figure 1 is a block diagram of a conventional multiplication circuit;
The figure is a circuit configuration diagram of a multiplication circuit in one embodiment of the present invention. 10...ROIJ, 20...D/A conversion circuit.

Claims (2)

【特許請求の範囲】[Claims] (1)入力アナログ信号に入力デジタル信号を乗算して
その乗算結果をアナログ信号として出力するアナログ乗
算回路において、デジタル信号入力を基準電圧に従って
アナログ信号に変換するデジタルアナログ変換回路の上
記基準電圧を指定するだめの端子に前記入力アナログ信
号を供給するとともに、前記デジタルアナログ変換回路
のデジタル信号入力端子に前記入力デジタル信号を供給
し、前記デジタルアナログ変換回路のアナログ信号出力
端子から前記入力アナログ信号と入力デジタル信号との
乗算値に相当するアナログ信号を出力するようにしたこ
とを特徴とするアナログ乗算回路。
(1) In an analog multiplier circuit that multiplies an input analog signal by an input digital signal and outputs the multiplication result as an analog signal, specify the reference voltage of the digital-to-analog conversion circuit that converts the digital signal input into an analog signal according to the reference voltage. The input analog signal is supplied to a terminal of the terminal, the input digital signal is supplied to a digital signal input terminal of the digital-to-analog conversion circuit, and the input analog signal and the input signal are input from the analog signal output terminal of the digital-to-analog conversion circuit. An analog multiplication circuit characterized in that it outputs an analog signal corresponding to a multiplied value with a digital signal.
(2)入力アナログ信号がファクシミリ読取装置の光セ
ンサから供給されるものであり、入力デジタル信号が前
記光センサについての補正値情報を記憶しているリード
・オンリ・メモリから供給されるものであることを特徴
とする特許請求の範囲第(1)項記戦のアナログ乗算回
路。
(2) The input analog signal is supplied from an optical sensor of the facsimile reading device, and the input digital signal is supplied from a read-only memory that stores correction value information for the optical sensor. An analog multiplication circuit according to claim (1), characterized in that:
JP58232357A 1983-12-09 1983-12-09 Analog multiplier circuit Pending JPS60123967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58232357A JPS60123967A (en) 1983-12-09 1983-12-09 Analog multiplier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58232357A JPS60123967A (en) 1983-12-09 1983-12-09 Analog multiplier circuit

Publications (1)

Publication Number Publication Date
JPS60123967A true JPS60123967A (en) 1985-07-02

Family

ID=16937938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58232357A Pending JPS60123967A (en) 1983-12-09 1983-12-09 Analog multiplier circuit

Country Status (1)

Country Link
JP (1) JPS60123967A (en)

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