JPS60123045A - Package for electronic parts and manufacture thereof - Google Patents
Package for electronic parts and manufacture thereofInfo
- Publication number
- JPS60123045A JPS60123045A JP58230823A JP23082383A JPS60123045A JP S60123045 A JPS60123045 A JP S60123045A JP 58230823 A JP58230823 A JP 58230823A JP 23082383 A JP23082383 A JP 23082383A JP S60123045 A JPS60123045 A JP S60123045A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- component
- sealing resin
- package
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＩＣ，ＬＳＩの小形、薄形パンケージ、例え
ばチップキャリヤパッケージ、あるいはＩＣ，ＬＳＩチ
ップをセラミック又は樹脂等の基板に直接搭載するハイ
ブリッドＩＣや電子時計用回路基板等に広く用いられて
いるいわゆるチップオンボード等に利用する電子部品パ
ッケージ及びその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to small and thin IC and LSI pancakes, such as chip carrier packages, and hybrid ICs and ICs in which IC and LSI chips are directly mounted on ceramic or resin substrates. The present invention relates to an electronic component package for use in so-called chip-on-boards, which are widely used in circuit boards for electronic watches, and a method for manufacturing the same.
従来例の構成とその問題点
第１図に樹脂材料を使用した従来のＩＣ，ＬＳＩのチッ
プキャリヤパッケージの構造を示す。以下にこの従来例
の構成について、第１図Ａ、Ｂとともに説明する。第１
図Ａ、Ｈにおいて、ベース板１は樹脂材料より成り、ダ
イパッド２．ワイヤボンディングバッド３．外部電極４
．側面導体５゜金属箔１２．絶縁層１３を有している。Structure of a conventional example and its problems FIG. 1 shows the structure of a conventional IC or LSI chip carrier package using a resin material. The configuration of this conventional example will be explained below with reference to FIGS. 1A and 1B. 1st
In Figures A and H, the base plate 1 is made of a resin material, and the die pad 2. Wire bonding pad 3. External electrode 4
．． Side conductor 5° metal foil 12. It has an insulating layer 13.
これらの形成は例えば通常の両面スルーホールプリント
基板と同様のプロセスによってなされ、側面導体５けス
ルーホールを半分に切断して得られる。次にダイパッド
２の上に、ダイボンディング用接着剤７等を用いて丁Ｃ
，Ｌ８丁チップ６を固着する。These are formed, for example, by a process similar to that of a normal double-sided through-hole printed circuit board, and are obtained by cutting five through-holes with side conductors in half. Next, apply die bonding adhesive 7 on top of die pad 2.
, L8 chips 6 are fixed.
続いてチップ６の電極８とワイヤポンディングパッド３
とをボンディングワイヤ９にてワイヤボンディングし接
続する。最後に枠１０を置き、枠内にエポキシ、シリコ
ーン等の封止樹脂を充填硬化して完成する。使用する際
は、外部電極４をプリント基板等の電極にハンダづけし
て回路を構成する０
本方法によれば、封止に樹脂を使用しているのでコスト
が安く、容易に実施できる利点があるが次に示すような
欠点があった。Next, the electrode 8 of the chip 6 and the wire bonding pad 3
and are connected by wire bonding with a bonding wire 9. Finally, the frame 10 is placed, and a sealing resin such as epoxy or silicone is filled and cured in the frame to complete the process. When in use, the external electrode 4 is soldered to the electrode of a printed circuit board, etc. to form a circuit. According to this method, since resin is used for sealing, the cost is low and it can be easily implemented. However, it had the following drawbacks.
（１）電子機器の小形、高密度化の要求に対応する為に
、チップキャリヤパッケージにも小形化が要求される。(1) In order to meet the demands for smaller size and higher density of electronic devices, chip carrier packages are also required to be smaller.
チップキャリヤパッケージを小形にする為には、ベース
板１の外形寸法をなるべく小さくシ、かつ厚さをなるべ
く薄くすると同時に、枠１０の高さをなるべく低くして
封止樹脂１１の厚さを薄くシ、全体として小形、薄形化
をはからなければならない。例えばベース板１の外形寸
法は一辺が５〜１０ ｍｍ、厚さは０．１〜１．０ ｍ
ｍ、封止樹脂１１のチップ６上での厚さは０．２〜０．
８ ｍｍ程度となる。一般に樹脂は湿気を透過する性質
をもっており、樹脂封止した半導体は封止樹脂中を透過
した大気中の湿気によって劣化する事が知られている。In order to make the chip carrier package compact, the outer dimensions of the base plate 1 should be made as small as possible and the thickness should be made as thin as possible, and at the same time, the height of the frame 10 should be made as low as possible and the thickness of the sealing resin 11 should be made as thin as possible. The overall size must be made smaller and thinner. For example, the external dimensions of the base plate 1 are 5 to 10 mm on each side and 0.1 to 1.0 m thick.
m, the thickness of the sealing resin 11 on the chip 6 is 0.2 to 0.
It will be about 8 mm. In general, resin has the property of transmitting moisture, and it is known that a resin-sealed semiconductor is deteriorated by atmospheric moisture that permeates through the sealing resin.
金属箔１２はパッケージの裏面からの湿気侵入に対して
は遮断効果があるが、表面からの湿気侵入に対しては全
く無防備である。特に上に述べた様に、樹脂の厚さが薄
い場合にはその影響が大きく、高温、高湿中で使用する
と半導体の寿命は著しく短くなる。The metal foil 12 has a blocking effect against moisture intrusion from the back side of the package, but is completely defenseless against moisture intrusion from the front surface. In particular, as mentioned above, when the thickness of the resin is thin, this effect is large, and when used in high temperature and high humidity, the life of the semiconductor will be significantly shortened.
（２）封止樹脂の充填方法として金型を使用せず、オー
プンエアーで行なった場合、第１図に示した様に封止樹
脂の表面が平坦にならず、一般に凸状になる。この為、
チップキャリヤパッケージを基板にマウントするとき、
真空吸着コレットでは正しく水平に吸着できなくなシ、
マウント精度が低下する。(2) When the sealing resin is filled in the open air without using a mold, the surface of the sealing resin is not flat as shown in FIG. 1, but generally becomes convex. For this reason,
When mounting the chip carrier package on the board,
Vacuum suction collets may not be able to properly suction horizontally.
Mounting accuracy decreases.
発明の目的
本発明は、上記従来例の欠点を除去するものであり、封
止材料はコストの安い樹脂材料で、しかも樹脂の厚さを
薄くした薄形構造でありながら、耐湿性の向上をはかる
ことを目的とするものである。更に、樹脂の充填方法が
金型を使用しない場合においても、パッケージの表面を
平坦とし、マウント精度の向上をはかろうとするもので
ある。Purpose of the Invention The present invention eliminates the drawbacks of the above-mentioned conventional examples.The sealing material is a low-cost resin material, and the resin has a thin structure with a thinner thickness, while improving moisture resistance. The purpose is to measure. Furthermore, even when the resin filling method does not use a mold, the surface of the package is made flat and the mounting precision is improved.
発明の構成
本発明は、上記目的を達成する為に封止樹脂の表面に気
密層（例えば金属層）を設ける様にしたものである。こ
の気密層によってパッケージの表面からの大気中の湿気
の侵入を遮断し、封止樹脂の厚さを薄くした薄形構造に
おいても半導体の劣化を防いでＩＣ１Ｌｓ■の長寿命化
を得るものである。また、気密層として平坦構造のもの
を用いることによって、封止樹脂の充填が金型を使用し
ない方法であってもパッケージの表面を平坦とし、マウ
ント精度を向上できる効果を得るものである。Structure of the Invention In order to achieve the above object, the present invention provides an airtight layer (for example, a metal layer) on the surface of the sealing resin. This airtight layer blocks atmospheric moisture from entering through the surface of the package, prevents deterioration of the semiconductor even in a thin structure with a thin sealing resin, and extends the life of the IC1Ls■. . Further, by using a flat structure as the airtight layer, even if the sealing resin is filled by a method that does not use a mold, the surface of the package can be made flat and mounting accuracy can be improved.
実施例の説明
本発明の一実施例について、第２図Ａ、Ｂ、第３図Ａ、
Ｄと共に説明する。本実施例は、樹脂材料を使用したＩ
Ｃ，ＬＳＩのチップキャリヤパッケージである。第２図
Ａ、Ｂは、チップキャリヤパッケージのベース板の平面
図及びａ−ａ・断面図であり、第３図Ａ−Ｄは組み立て
工程図である。DESCRIPTION OF EMBODIMENTS Regarding one embodiment of the present invention, FIGS. 2A and B, FIGS. 3A,
This will be explained together with D. In this example, an I
C, LSI chip carrier package. 2A and 2B are a plan view and a cross-sectional view along line aa of the base plate of the chip carrier package, and FIGS. 3A and 3D are assembly process diagrams.
まず、チップキャリヤパッケージのミース板について第
２図とともに説明する。First, the Mies plate of the chip carrier package will be explained with reference to FIG.
第２図において、ベース板２１は樹脂材料より成り、ダ
イポンディングパッド２２．ワイヤポンディングパッド
２３．外部電極２４．側面導体２５、金属箔３２．絶縁
層３３を有している。これらの形成は第１図において述
べた従来例の場合と同様の方法でなされる。次に組み立
て工程について第３図とともに説明する。まず、第３図
Ａに示す様にベース板２１のダイポンディングパッド２
２の上に、ダイボンディング用樹脂２７等を用いてＩＣ
，ＬＳＩチップ２６をダイボンディングする。次に第３
図Ｂに示す様に、チップ２６の電極２８とワイヤポンデ
ィングパッド２３とをボンディングワイヤ２９にてワイ
ヤボンディングし、接続する。引き続いて第３図Ｃに示
す様に、枠３０を接着剤３４を用いてベース板２１に接
着しく封止樹脂の粘度によっては置くだけでもよい）エ
ポキシ又はシリコーン等の封止樹脂３１を枠３０内に充
填する。これ迄の工程は第１図に示した従来例と全く同
様である。最後に、第３図りに示す様に絶縁層３６をも
つ金属板３５を封止樹脂３】の表面にのせて封止樹脂３
１を硬化させる。In FIG. 2, a base plate 21 is made of a resin material, and a die-bonding pad 22. Wire bonding pad 23. External electrode 24. Side conductor 25, metal foil 32. It has an insulating layer 33. These formations are performed in the same manner as in the conventional example described in FIG. Next, the assembly process will be explained with reference to FIG. First, as shown in FIG. 3A, the die-ponding pad 2 of the base plate 21 is
2 using die bonding resin 27 etc.
, the LSI chip 26 is die-bonded. Then the third
As shown in FIG. B, the electrode 28 of the chip 26 and the wire bonding pad 23 are connected by wire bonding using a bonding wire 29. Subsequently, as shown in FIG. 3C, a sealing resin 31 such as epoxy or silicone may be attached to the frame 30 by adhering the frame 30 to the base plate 21 using an adhesive 34 (depending on the viscosity of the sealing resin). Fill inside. The steps up to this point are completely similar to the conventional example shown in FIG. Finally, as shown in the third diagram, the metal plate 35 with the insulating layer 36 is placed on the surface of the sealing resin 3.
1 is cured.
硬化前の封止樹脂３１が液状であれば、金属板３５はそ
のま＼樹脂の上にのせて、まだ、粉末又は固形の場合は
一度加熱して液状とし、その上にのせて硬化処理すれは
封止樹脂が硬化すると同時に金属板３５は封止樹脂の接
着作用によって封止樹脂３１上に強固に接着する。金属
板３５の材質は、銅、アルミ、ニッケル等入手容易な吃
のでよく、特に制限はなく、厚さは０．０１． ｍｍ程
度以上であれば充分大気からの湿気侵入を防ぐ事ができ
る。If the sealing resin 31 is in a liquid state before hardening, the metal plate 35 is placed on top of the resin as it is, but if it is still a powder or solid, it is heated once to make it into a liquid state, and then placed on top of it for hardening treatment. At the same time as the sealing resin hardens, the metal plate 35 is firmly adhered onto the sealing resin 31 by the adhesive action of the sealing resin. The material of the metal plate 35 may be any easily available material such as copper, aluminum, nickel, etc., and there are no particular restrictions, and the thickness may be 0.01 mm. If it is about mm or more, it is possible to sufficiently prevent moisture from entering from the atmosphere.
絶縁層３６は金属板３５とボンディングワイヤ２９とが
接触するのを防ぐだめのものであり、ワイヤと金属板の
間隔が広ければ不必要である。必要によっては、金属板
３５の上面に絶縁層を設けたり、又は金属板３５０更に
上側を封止樹脂で被覆してもよい。The insulating layer 36 serves to prevent the metal plate 35 and the bonding wire 29 from coming into contact with each other, and is unnecessary if the distance between the wire and the metal plate is wide. If necessary, an insulating layer may be provided on the upper surface of the metal plate 35, or the upper side of the metal plate 350 may be coated with a sealing resin.
本実施例によれば、樹脂材料を使用したＩＣ。According to this embodiment, an IC using a resin material.
Ｌ Ｓ Ｉのチンプキャリャハンゲージにおいて、封止
樹脂３１上に金属板３５を接着したので・くノケージ表
面からの大気中の湿気の侵入を防いで、半導体の劣化を
防ぎ、ＩＣ，ＬＳＩの長寿命化が得られると同時に、パ
ッケージの表面が平坦となってマウント精度が向上する
利点がある。金属板３５の厚さは０．０１ ｍｍ程度以
上と、非常に薄いのでパッケージ全体の高さにはほとん
ど影響を与えることがなく、金属板３５の湿気遮断効果
によって封止樹脂３］の厚さを薄くできるので、薄形パ
ッケージが可能となる。又、金属板３５の接着と封止樹
脂３１の硬化とは同時に々されるので、金属板３５の接
着工程を別に設ける必要はない。In the LSI chimp carrier hangage, the metal plate 35 is bonded onto the sealing resin 31. This prevents moisture from entering the atmosphere from entering the cage surface, prevents semiconductor deterioration, and improves the performance of ICs and LSIs. This has the advantage of not only extending the life of the package but also making the surface of the package flat and improving mounting accuracy. The thickness of the metal plate 35 is approximately 0.01 mm or more, which is very thin, so it has almost no effect on the overall height of the package, and the thickness of the sealing resin 3 is reduced by the moisture blocking effect of the metal plate 35. Since it can be made thinner, thin packages are possible. Moreover, since the bonding of the metal plate 35 and the curing of the sealing resin 31 are performed simultaneously, there is no need to provide a separate process for bonding the metal plate 35.
本発明の構成を具体化する他の実施例を以下に示す。Other embodiments embodying the structure of the present invention will be shown below.
（１）第３図において、封止樹脂３１上に金属層を形成
するのに、封止樹脂３１が硬化後金載板を接着するか、
またはメッキ、スパッター蒸着、溶射等の方法によるも
の。(1) In FIG. 3, in order to form a metal layer on the sealing resin 31, after the sealing resin 31 has hardened, the metal plate is bonded or
Or by methods such as plating, sputter deposition, thermal spraying, etc.
（２）気密層として金属によらず、セラミック。(2) Use ceramic instead of metal as the airtight layer.
ガラス等の非金属材料を使用したもの。Items using non-metallic materials such as glass.
（３）気密層の上面を樹脂で被覆したもの。(3) The upper surface of the airtight layer is coated with resin.
（４）封止樹脂の充填方法としてオープンエアーの他、
金型成型法によるもの。(4) In addition to open air as a filling method for sealing resin,
Made by mold molding method.
（５）第３図においてベース板２１が他の構造のもの、
及び利質が樹脂以外のもの。(5) In FIG. 3, the base plate 21 has a different structure,
and materials other than resin.
（６）第３図において枠３０を使用しないもの。(6) The frame 30 in FIG. 3 is not used.
（力 第３図においてベース板２１が回路基板の場合、
すなわち、ハイブリッドＩＣにおいてＩＣ。(Force In Fig. 3, when the base plate 21 is a circuit board,
That is, an IC in a hybrid IC.
ＬＳＩチップを直接基板上に搭載した場合や、電子時計
用回路基板に広く用いられている、いわゆるチップオン
ボードの場合等。Examples include cases in which an LSI chip is mounted directly on a board, and cases in which a so-called chip-on-board is used, which is widely used in circuit boards for electronic watches.
（８）全実施例の任意の組合わせ。(8) Any combination of all embodiments.
発明の効果
本発明は、上記のよう々構成であり、以下に示す効果が
得られるものである。Effects of the Invention The present invention is configured as described above, and provides the following effects.
（１） ＩＣ，ＬＳＩチップの樹脂パッケージにおいて
、封止樹脂の表面に気密層を設ける様にしだので、大気
中の湿気がパッケージ中に侵入するのを防ぐことができ
る。その為、半導体の劣化を防ぎ、ＩＣ，ＬＳＩの長寿
命化が得られる。気密層の厚さは０．０１ ｍｍ程度以
上と薄いものであり、気密層の防湿効果によって封止樹
脂の厚さは薄くてもよいので、薄形構造が可能となる。(1) In resin packages for IC and LSI chips, since an airtight layer is provided on the surface of the sealing resin, moisture in the atmosphere can be prevented from entering the package. Therefore, deterioration of the semiconductor can be prevented and the lifespan of ICs and LSIs can be extended. The thickness of the airtight layer is as thin as approximately 0.01 mm or more, and the sealing resin may be thin due to the moisture-proofing effect of the airtight layer, so a thin structure is possible.
（２）封止樹脂の表面に平坦な構造の気密層を設けるこ
とによって、封止樹脂の充填に金型を使用しない場合で
も、パッケージの表面は平坦となる。(2) By providing an airtight layer with a flat structure on the surface of the sealing resin, the surface of the package becomes flat even when a mold is not used to fill the sealing resin.
そのため、基板上にパッケージをマウントするとき、真
空吸着コレットで吸着しても正しく水平に吸着され、マ
ウント精度が向上する。Therefore, when mounting a package on a substrate, even if the package is attracted by a vacuum suction collet, the package is correctly and horizontally attracted, improving mounting accuracy.
第１図Ａ、Ｂは、従来のＩＣ，ＬＳＩのチップキャリヤ
パッケージの断面図および平面図、第２図Ａ、Ｂは本発
明の一実施例における電子部品パッケージの断面図およ
び平面図、第３図Ａ−Ｄは同電子部品パッケージの各製
造工程における断面図である。
２１・・・ベース板、２２・・・ダイポンディングパッ
ド、２３・・・ワイヤポンディングパッド、２４・・・
外部電極、２５・・・側面導体、２６・・・ＩＣ，ＬＳ
Ｉチップ、２７・・・ダイボンディング用樹脂、２８・
・電極、Ｉ２９・・・ボンディングワイヤ、３０・・枠
、３１・・・封止樹脂、３２・・・金属箔、３３・・絶
縁層、３４・・・接着剤、３５・・・金属板、３６・・
絶縁層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図1A and 1B are a sectional view and a plan view of a conventional chip carrier package for IC and LSI, FIGS. 2A and 2B are a sectional view and a plan view of an electronic component package according to an embodiment of the present invention, and 3. Figures A to D are cross-sectional views at each manufacturing process of the electronic component package. 21... Base plate, 22... Die bonding pad, 23... Wire bonding pad, 24...
External electrode, 25... Side conductor, 26... IC, LS
I chip, 27... Resin for die bonding, 28.
- Electrode, I29... Bonding wire, 30... Frame, 31... Sealing resin, 32... Metal foil, 33... Insulating layer, 34... Adhesive, 35... Metal plate, 36...
insulation layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2
Claims (6)
板と、この基板の上記部品搭載部に固着された部品と、
上記部品の電極と上記基板の部品接続電極とを電気的に
接続する導電部材と、少くとも上記部品を覆う封止材と
、この封止材上又は封止材内に設けられた気密層とを有
する電子部品パンケージ。(1) - A board having a component mounting part and a component connection electrode on its main surface, and a component fixed to the component mounting part of this board,
a conductive member that electrically connects the electrode of the component and the component connection electrode of the substrate; a sealing material that covers at least the component; and an airtight layer provided on or within the sealing material. Electronic component pancage with.
記載の電子部品パッケージ。(2) The electronic component package according to claim 1, wherein the airtight layer is made of a metal plate.
項記載の電子部品パッケージ。(3) Claim 1 in which the airtight layer is made of glass
Electronic component package as described in section.
１項記載の電子部品パッケージ。(4) The electronic component package according to claim 1, wherein the airtight layer is made of ceramic.
特許請求の範囲第１項記載の電子部品パッケージ。(5) The electronic component package according to claim 1, which uses an airtight layer having an insulating layer on at least one side.
板の上記部品搭載部に部品を固着する部品固着工程と、
上記部品の電極と上記基板の部品接続電極とを接続する
電極接続工程と、少なくとも上記部品を覆う様に上記基
板上に封止材を設ける封止工程と、上記封止工程後又は
封止工程中に上記封止材上又は封止材内に気密層を形成
する気密層形成工程とからなる電子部品パッケージの製
造方法。(6)-A component fixing step of fixing a component to the component mounting portion of a board having a component mounting portion and a component connection electrode on the main surface;
an electrode connection step of connecting the electrode of the component and a component connection electrode of the substrate; a sealing step of providing a sealing material on the substrate so as to cover at least the component; and a sealing step after the sealing step or a sealing step. and forming an airtight layer on or within the sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58230823A JPS60123045A (en) | 1983-12-07 | 1983-12-07 | Package for electronic parts and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58230823A JPS60123045A (en) | 1983-12-07 | 1983-12-07 | Package for electronic parts and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60123045A true JPS60123045A (en) | 1985-07-01 |
Family
ID=16913838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58230823A Pending JPS60123045A (en) | 1983-12-07 | 1983-12-07 | Package for electronic parts and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60123045A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50135985A (en) * | 1974-04-16 | 1975-10-28 | ||
| JPS5494877A (en) * | 1978-01-11 | 1979-07-26 | Toshiba Corp | Production of electronic part device |
| JPS5561050A (en) * | 1978-10-31 | 1980-05-08 | Sony Corp | Manufacture of electronic parts |
-
1983
- 1983-12-07 JP JP58230823A patent/JPS60123045A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50135985A (en) * | 1974-04-16 | 1975-10-28 | ||
| JPS5494877A (en) * | 1978-01-11 | 1979-07-26 | Toshiba Corp | Production of electronic part device |
| JPS5561050A (en) * | 1978-10-31 | 1980-05-08 | Sony Corp | Manufacture of electronic parts |
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