JPS60121809A - Receiver - Google Patents

Abstract

PURPOSE:To prevent deterioration in S/N by performing AGC control so that when a reception signal increases in input level, the gain of an intermediate frequency amplifier is decreased and then the gain of a high frequency amplifier is decreased. CONSTITUTION:When the reception signal increases in electric field intensity, an AGC voltage VAGC from a detecting circuit 5 rises and currents of transistors TR24 and 27 of differential amplifier circuits 100 and 300 increase. The circuits 100 and 200 receive constant currents from constant current sources 25 and 28, so the collector currents IC1 and IC2 of TRs 23 and 26 decrease and the high frequency amplifier circuit 2 and intermediate frequency amplifier circuit 4 both decrease in gain. In this case, the fixed bias voltage VB2 of the TR26 is lower than the fixed bias voltage VB1 of the TR23, so the current IC2 decreases before the current IC1 decreases. Therefore, the circuit 4 decreases in gain earlier than the circuit 2 and a noise level generated by the circuit 2 instantaneously is decreased and sent to the circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiver equipped with an AGC circuit for controlling the gains of a high frequency amplification circuit and an intermediate frequency amplification circuit.

3 shows an example of a conventional AGC circuit, in which a transistor 9.
10. Multi-stage amplifiers 2, 3 .
4 gains are controlled.

The high-frequency amplifier circuits 2, 3, and 4 are each configured by a differential amplifier circuit, for example, and a constant current source circuit that provides a DC bias current flowing into each differential amplifier circuit includes transistors 9, 10, and 11, and an emitter resistor 1. .2.1
3 and 14.

The input signal of terminals 1 to 1) is amplified by high frequency amplifier circuits 2, 3 and 4, then detected by a detection circuit 5, and sent to output terminal G.
,! 9 taken out. The detected signal appearing at the terminal 61 is smoothed by a resistor and a capacitor 8, and is applied as a control voltage to the bases of NPN transistors 9 to 11 of the constant current source circuit, thereby controlling the constant current of each transistor 9 to 11. By varying the value, the amplification gain of the differential amplifier circuit can be varied as a result.

However, in the conventional AGC circuit shown in Figure 3, A
The decrease in the GC control voltage t thus causes each transistor 9, 10
．． The collector currents of the amplifiers 11 and 11 simultaneously begin to decrease by 1, and the gains of the multistage amplifiers 2 and 3.4 simultaneously begin to decrease.

By the way, the inventor has found that if the gain of the front-stage amplifier starts to decrease before the gain of the rear-stage amplifier reaches a low gain state, the output noise generated from the output of the front-stage amplifier is amplified by the rear-stage amplifier. The problem of deterioration of the S/N ratio was revealed. That is, in the multi-stage amplifier (), so that the S/N ratio of the front-stage amplifier and the rear-stage amplifier is the best when the front-stage amplifier and the rear-stage amplifier are each controlled to the maximum gain state,
Multi-stage amplifiers are generally designed (6) Therefore, as the gains of the front and rear amplifiers decrease, the noise level from the outputs of the front and rear amplifiers increases. If the gain of the front-stage amplifier starts to decrease before entering the gain state, the output noise of the front-stage amplifier will be amplified by the rear-stage amplifier, so the S/R of the multi-stage amplifier will decrease.
This results in a problem that the N ratio deteriorates.

On the other hand, in the conventional AGC circuit shown in FIG. 3, the gain control sensitivities of the multistage amplifiers 2, 3, and 4 exhibit variations due to variations in the resistance values of the emitter resistors 12° and 13.34 of the transistors 9 and 10.11. , has the disadvantage that AGC operation tends to be uncertain.

Therefore, an object of the present invention is to provide a receiver that enables suitable AGC operation of the high frequency amplifier circuit and intermediate frequency amplifier circuit in the receiving hole.

A brief overview of typical inventions disclosed in this application is as follows.

That is, a high frequency amplification circuit (2) in the receiver, an intermediate frequency amplification circuit (4) connected after the high frequency amplification circuit (2), and an intermediate frequency amplification circuit (4) for controlling the gain of the high frequency amplification circuit (2). 1 differential pair with 1 runno (23, 24),
a second differential pair of transistors (26, 27) for controlling the gain of the intermediate frequency amplification circuit (4), one of the first differential pair transistors (23) and the second differential pair of transistors;
A fixed bias voltage is applied to one of the differential pair transistors (26) of ff1, and the other of the differential pair transistors of ff12 (24) and the other of the differential pair transistors of ff12 (24) are applied.
27), and the level of the fixed bias voltage and the level of the A G Cft+lJ control voltage are determined by applying an AGC control voltage to the intermediate frequency amplifying circuit (4) when the human power signal level of the high frequency amplifying circuit (2) increases. The gain of the high frequency amplifier circuit (2) is reduced after the gain of the high frequency amplifier circuit (2) is reduced.

Therefore, when the input signal level increases, it is possible to reduce the gain of the preceding stage high frequency amplifier circuit (2) after setting the subsequent stage intermediate frequency amplifier circuit (4) to the minimum separate signal state, so that the gain of the preceding stage high frequency amplifier circuit (2) can be reduced. This ends by preventing deterioration of the S/N ratio.

Furthermore, a high frequency amplification circuit (2) and an intermediate frequency amplification circuit (4)
) gain control is determined by the differential switching characteristics of one transistor (23; 26) and the other transistor (24; 27) of the differential pair transistors (23, 24; 26, 27) connected to each other. Therefore, the variation in gain control sensitivity is reduced compared to the conventional method, and the AGC operation can be ensured.

The present invention will be explained below with reference to FIG.

FIG. 1 shows a circuit diagram of an embodiment of AM reception and reception according to the present invention. In the figure, reference numeral 15 receives a high frequency signal with an antenna. The high frequency signal is amplified by the high frequency amplifier circuit 2, and then sent to the mixing circuit 16, where the frequency is converted by the local oscillation signal upstream from the local oscillation circuit 17 and converted into an intermediate frequency signal (for example, 4 S S K Hz). be done. This signal is amplified by the intermediate frequency amplification circuit 4, then detected by the detection circuit 5, converted into a low frequency signal, and sent to the low frequency amplification circuit 18.

The high frequency amplifier circuit 2 is formed by, for example, a differential amplifier circuit, and the bias circuit 100 for the differential amplifier circuit is
A pair of transistors 23 and 2 connected in a differential manner
4 and a constant current power supply circuit 25. The constant current source circuit 25 may be a simple resistance element. Among the pair of transistors, the base of the transistor 23 is supplied with a constant DC voltage Vo+ from the power supply circuit 200, and the base of the other transistor 24 is supplied with the voltage A obtained from the detection circuit 5.
A GC control voltage V hac is applied, and a power supply Vc is connected to its collector.

The intermediate frequency amplification circuit 4 is also configured in the same circuit format as the high frequency amplification circuit 2. Bias circuit 3 of amplifier circuit 4
Similarly to the bias circuit 100, the circuit 00 also includes a pair of transistors 26 and 27 and a constant current source circuit 28. The constant current source circuit 28 can also be constructed from a simple resistive element. Among the pair of transistors, a constant DC voltage VR2 is applied to the base of the transistor 26 from the power supply circuit 200. This voltage 112 is selected to be lower in absolute value than VB+.

The power supply circuit 200 is composed of resistors 20, 21 and 22 forming a potentiometer circuit connected to a constant voltage power supply Vz. It goes without saying that the power supply circuit 200 may be constructed by connecting a plurality of constant voltage elements such as PN junction semiconductor diodes in series instead of these resistors.

The AGC voltage cc is branched from the detection circuit 5 and is obtained through a decoupling circuit consisting of a resistor 7 and a capacitor 8.

To explain the operation, when the input signal level of the high-frequency amplifier circuit 2, that is, the electric field strength of the received signal increases and the above-mentioned AGC control voltage VA (JC) increases, the collector currents of the transistors 24 and 27 increase. Here, since the sum of the collector currents of the transistors 23 and 24 and the sum of the collector currents of the transistors 26 and 27 are each constant, the collector currents of the transistors 23 and 26 each decrease.Therefore, the bias circuit of the amplifier circuits 2 and 4 The bias current I C1lI C2 decreases, and the amplification gain of the amplifier circuit 2.4 is reduced.At this time, the fixed bias voltage VB of the transistor 23 is
Since the fixed bias voltage 132 of the transistor 26 is lower, the collector current 7M of the transistor 26 decreases faster than the collector current IC of the transistor 23 decreases. Therefore, the gain of the amplifier circuit 4 (a differential circuit made up of a pair of emitter-coupled transistors) is lowered faster than that of the amplifier circuit 2.

As is clear from the above explanation, when the input signal level of the high frequency amplifier circuit 2, that is, the received signal level is extremely low, the AGC control voltage Vxac is also extremely low, and the constant current source circuit 25 is connected to the collector-emitter path of the transistor 23.
Since the current from the constant current source 28 flows through the collector-emitter path of the transistor 26, the high frequency amplifier circuit 2 and the intermediate frequency amplifier circuit 4 each amplify the input signal in a high gain state.

Next, when the received signal level increases slightly, the AGC control voltage J
The voltage applied to the voltage V8a rises to a level between the fixed bias voltage Vn2 and the fixed bias voltage VB1, and the constant current source circuit 2 is connected to the collector-emitter path of the transistor 23.
5 flows, and the current of the constant current source circuit 28 flows through the collector-emitter path of the transistor 27, so the high frequency amplifier circuit 2 operates in a high gain state and the intermediate frequency amplifier circuit 4 operates in a low gain state. .

The received signal level increases further and the AGC control voltage ~
When the AGC is raised to a level close to the fixed bias voltage \lB, the current of the constant current source circuit 25 also flows to the collector-emitter path of the transistor 24, so the gain of the high-frequency amplifier circuit 2 also decreases. Start.

In this way, when the received signal level increases, the gain of the high frequency amplifier circuit 2 placed in the previous stage starts to decrease after the intermediate frequency amplifier circuit 4 placed in the latter stage enters a low gain state, so that the overall receiver This makes it possible to prevent deterioration of the S/N ratio.

Furthermore, the received signal level becomes stronger and the AGC voltage Vha
1 until c exceeds the fixed bias voltage V B 1
In other words, the currents in the collector-emitter paths of the transistors 23 and 26 become zero, and the high-frequency amplification circuit 2 and the intermediate-frequency amplification circuit 4 each operate in their lowest gain states.

Adjustment of the AGC operation order for each amplifier circuit is performed by adjusting the output voltages 1B1 and 7B2 of the power supply circuit 200. If the voltage of the port 1 is made equal to the voltage of Ve2, the AGe voltage VAac will simultaneously control the collector current c2 of the transistor 26 and the collector current 1c1 of the transistor 23, so the amplifier circuit 2 The gain of the amplifier circuit 4 is controlled at the same time as the amplifier circuit 4 in the subsequent stage.

In the present invention, the bias voltage is VBI > Vn2
By setting the following relationship, the bias current of the amplifier circuit is controlled sequentially from the latter stage amplifier circuit to the front stage amplifier circuit.

As described above, according to the present invention, the gain reduction of the subsequent stage amplifier and the gain reduction of the previous stage amplifier are performed in an orderly manner.
It is possible to prevent deterioration of the S/N ratio, which has been a problem in the past.

Furthermore, according to the present invention, since the AGC circuit uses a single transistor connected in a differential manner as a basic circuit, variations in transistor characteristics (for example, base-emitter voltage VBE) are caused by the differential compensated by the circuit. For example, in FIG. 1, if the VBE of the transistor 24 is increased by a certain IC manufacturing technology, the VBE of the transistor 23 manufactured within the same silicon substrate is
Since p also varies in the direction of increasing, it results in no change in Ic1. Furthermore, since the AGc circuit of the present invention uses a differential circuit as its basic circuit, it is suitable for use in (1)C.

FIG. 2 shows a circuit diagram of an embodiment of an integrated circuit for a heterogain AM receiver according to the present invention. In this figure, the same parts as those in FIGS. 3 and 1 are given the same reference numerals, and their explanations will be omitted. In this embodiment, the amplifier circuit 2 is N
l) Use a NL transistor made of 9°40.4.3.46 or the like. Also, as the addition circuit 4, NPN
) Ransistor 58゜59.62+ 64,65+ 67
A differential amplifier circuit consisting of the following is used. Also, as the detection circuit 5, NPN transistors 70+74 and capacitors 7
Use one made of 6 grade. In addition, in this embodiment, a resistor of 48°5 is used as the fixed device circuit (power supply circuit) 200.
3.54, using diodes 49 to 52, apply a fixed bias voltage V81 to the base of transistor 23, which is larger than the connection point of diode 50゜51, and apply a fixed bias voltage V81 to the base of transistor 26, which is smaller than the connection point of resistor 53゜54. A fixed bias voltage Vn2 is applied. This allows the first
The same effects as the embodiment shown in the figure can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the differential pair transistors 23, 24, 26, 27 of the bias circuits 100, 300 can use MO3 field effect transistors in addition to bipolar transistors.

Further, while applying the same fixed bias voltage to the base of the transistor 23 of the bias circuit 100 and the base of the transistor 26 of the bias circuit 300, the base of the transistor 27 of the bias circuit 300 and the base of the transistor 26 of the bias circuit 300 are
By connecting a level shift circuit between the base of the transistor 24 and the base of the transistor 24, the base potential of the transistor 24 is made lower than the base potential of the transistor 27 for the same AGC control voltage Vhcc. It goes without saying that when the input signal level increases, it is possible to similarly reduce the gain of the intermediate frequency amplifier circuit 4 and then reduce the gain of the high frequency amplifier circuit 2.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the Ah4 reception according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the integrated circuit for heterogain AM reception according to the present invention, and FIG. AGC
FIG. 2 is a circuit diagram showing a circuit.

Claims (1)

[Claims] 1. An antenna (1, 5) for receiving high frequency signals. "High frequency amplification circuit (2) for amplifying the high frequency signal (2)
) 1 local oscillation port 1 m (1 m) for oscillating local oscillation signals
7), a mixing circuit (1, 6) for converting the frequency of the high frequency signal using the local oscillation signal, an intermediate frequency amplification circuit (4,) for amplifying the output signal of the mixing circuit; A detection circuit (5) for detecting the output signal of the open frequency amplification circuit (4), a decoupling circuit (7, 8) coupled to the detection circuit, and a second detection circuit (7, 8) for controlling the gain of the high frequency amplification circuit. 1 differential pair transistor (2'3.24
), a second circuit for controlling the gain of the intermediate frequency amplification circuit.
A fixed bias voltage is applied to one of the first differential pair transistors (23) and one of the second differential pair transistors (26). and the other of the first differential pair transistors (24) and the other of the second differential pair transistors (27).
) is applied with the AGC control voltage obtained from the decoupling circuit, and the level of the fixed bias voltage and the level of the AGC control voltage are
), the gain of the intermediate frequency amplification circuit (4) is reduced, and then the high frequency amplification circuit (4) increases.
2) A receiver characterized in that it is set to reduce the gain of (2). 2. The fixed bias voltage (Vnl) applied to one side (23) of the first differential pair transistors is -the fixed bias voltage (Vnl) applied to one side (26) of the second differential pair transistors (2). Vn2), and the AGC control voltage is commonly applied to the other one of the first differential pair transistors (24) and the other one of the second differential pair transistors (27). The reception according to claim 1, characterized in that: