JPS60121591A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To supply the voltage loss caused in an information writing mode by setting the potential of the signal supplied to a gate electrode at a level higher the absolute value of the potential of a digit line within a period during which the 1st and 2nd electrodes of a switching MISFET serve as a drain and a source respectively. CONSTITUTION:If the address inputs of MISFETs Q1-Q11, for example, are all set at a low level when address information a1 and -a1 are fixed, a drive MISFET Q of an address decoder consisting of those MISFETs Q1-Q11 is turned on. Thus a word clock XWC applied to a drain is delivered to the source side to set a word line W1 at a high level. In this case, the drive MISFETs of the address decoder circuit groups of an X system are turned off excluding an MISFET Q8. A bootstrap capacitor is set between the source and the drain of the word line drive MISFETs Q8 and Q14. Then the gate voltage is set higher than the drain voltage. Thus the drain voltage is delivered as it is to the source side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and for example, to a dynamic MIS (metal insulating film semiconductor) memory circuit.

A dynamic MIS memory circuit utilizes the presence or absence of charge accumulated in a storage capacitor.

Writing is performed in this storage capacity via a switching MISFET controlled by a word line, so when writing information on the power supply voltage side level, the charging pressure level is reduced by the threshold voltage of this MISFET. (
(When the write level and word line control level are the same)
.

For this reason, especially in dynamic MIS memory circuits that directly read out the stored storage level, such as dynamic MIS memory circuits that are composed of one transistor memory cell, consideration is given to increasing the power supply voltage to compensate for the voltage loss. There is. Therefore, a dynamic MIS memory circuit that operates at a low power supply voltage (for example, about 5 V) could not be put into practical use.

Note that a circuit for driving word or bit lines of a monolithic memory is shown in Japanese Patent Laid-Open No. 49-52938.

This invention relates to a switching MIS that constitutes a memory cell.
Dynamic MIS that prevents voltage loss in FETK
Made to provide memory circuits.

This invention adds a Pootstrap capacitor to the word clock pulse output circuit to increase the level of the word clock pulse and
This is intended to compensate for voltage loss in ET.

Hereinafter, this invention will be specifically explained with reference to examples. FIG. 1 shows a dynamic MI
In the circuit diagram showing the main parts of the S memory, ◎ (1) is a word clock generation circuit, which forms a selection pulse for the word mcW). This circuit uses address information (ao to aS
) is confirmed, the word clock (Xwc)
In order to generate
) at the rising edge of M I S F E T (
By turning on Qp or Q, it turns off and generates a word clock (Xwc).

(2) shows a part of the row-related address decoder circuit group. In this figure, two X-based address decoders are shown for convenience of explanation. Address information (al.

al) is confirmed, if M I S F E T
Assuming that the address inputs (Qo to Q+1) are all at low level, the drive MISFETQ of the address decoder made up of these MISFETs is turned on. The word clock (Xwc) thus applied to the drain is output to the source side, making the word line (W,) high level.

At this time, driving M other than Q of the X-system address decoder circuit group
ISFET is off.

A bootstrap capacitor is provided between the gate and source of the word line drive MI 5FET (Qs, Qsa), and by making the gate voltage higher than the drain voltage, it is considered that the drain voltage is directly output to the source side. There is.

The word clock (XWC) is applied to the write/read MISFETs (Qs., Q□) of the memory cells (4, 4') whose gates are connected to the selected word line (WS in the above example). For example, when writing a high level, the high level of the digit line is written to the storage capacitor (Cs 1 y Cg 2) via the MISFET (Q!., Q, .).

At this time, if the voltage level of the word line is within the voltage level of the digit line, the write voltage is set as the write voltage.

Word line voltage level - threshold voltage of MISFET (Qz., Q□). Therefore, when the write level is lowered and discharge due to leakage current of the storage capacitor (C8) is taken into consideration, it becomes difficult to carry out mesori operation under a low power supply voltage as described above.

Therefore, in this embodiment, in order to prevent write voltage loss due to the threshold voltage of the switching MISFET of the memory cell, the delay circuit (3) and the bootstrap capacitance CCmθ are designed.

That is, the word clock (X
A timing signal (Xw c ) delayed by a predetermined time (td) from wc) is formed, and one end of the bootstrap capacitor (c, I) is connected to the output terminal of the word clock generation circuit (1). Timing signal (Xwc'
) is applied.

As a result, address information (
The word clock (Xwc) that rises at the rising edge of ao or ao) charges the parasitic capacitance (CAT) and bootstrap capacitance at this output terminal, and then the bootstrap capacitance is charged at the rising edge of the timing signal <xwc'>. Since the other end is raised, the voltage level of the word clock increases by ΔV.

This voltage (aV) is applied to the capacitor (CIIT #c,
It is determined by charge division according to the capacity ratio of I), and is determined by the following formula (
1) % formula % (where ■φ is the voltage level of the word clock and timing signal.

Therefore, if we set ■φ-4.5V and C5T-CBI, lv becomes 2.25V, and due to this bootstrap effect, the voltage level of the word clock (Xwc) at this time can be raised to about 6.75V. Because the word line drive MISFET outputs the word clock voltage, which is the drain voltage, to the source side as it is due to its bootstrap effect, the gate voltage of the memory cell write/read MISFET is sufficient to operate this MISFET in a non-saturated manner. With a sufficient value, it becomes higher than the voltage of the digit line, and the voltage of the digit line is transmitted to the storage capacitor t< without voltage loss.

The delay circuit (3) is a dynamic inverter (Q1
4 #Qts ) and (Qts -Q*te) are connected in series, and the delay time (td) by this circuit must be set at least to the time required for the rising edge of the word clock (Xwc) mentioned above. Desirable for enhancing the strap effect. This will be easily understood from the above explanation of the operation. This time setting can be adjusted by the conductance of MI SFE'l' of the inverter.

According to this embodiment circuit explained above, the delay circuit (3
) and a capacitor, it is possible to increase the write level to the memory cell.

Along with this, it is also possible to lower the power supply voltage of the memory circuit, which not only facilitates connection with the TTC circuit, but also allows for a significant reduction in power consumption.

This invention is not limited to the above embodiments, and can take various embodiments.

As is clear from equation (1), the larger the bootstrap capacitance t (CBt) is against the parasitic capacitance in the word clock output line, the higher the voltage can be. is slow, so it is desirable to choose the smallest value necessary.

Moreover, the delay circuit (3) is a transmission gate MI S FET
Various modifications can be made, such as using .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an operational waveform diagram thereof. (1)... Word clock generation circuit, (2)... Row-related address decoder, (3)... Delay circuit, (4) ~
(41”...Memory cell.

Claims (1)

[Scope of Claims] 1. A digit line, an information storage means, and a first digit line coupled to the digit line!
a switching MI 5FET having a pole, a second electrode coupled to the information storage means, and a gate electrode, at least a first electrode of the switching MISFET serving as a drain, and a second electrode of the switching MISFET serving as a drain; a semiconductor memory device characterized by comprising means for making the potential of the signal supplied to the gate electrode of the switching MI 5FET higher than the absolute value of the potential of the digit line during a period when the switching MI 5FET is working as a source. . 2. The semiconductor memory device according to claim 1, wherein the means is a bootstrap means. 3. The bootstrap means has a pair of electrodes, one of which is connected to the switching MI.
Claim 2, comprising: a bootstrap capacitor coupled to the gate electrode of the SFET; and a timing signal generation circuit that supplies a predetermined timing signal to the other electrode of the charged bootstrap capacitor. The semiconductor storage device described above. Margin below