JPS60121409A - Focus detecting device of camera using selfscanning image sensor - Google Patents

Abstract

PURPOSE:To prevent saturation of a stored electric charge by resetting a transfer clock pulse generating means in response to fall of a prescribed level of the output of a monitor circuit and generating a shift pulse in response to a reset pulse. CONSTITUTION:A digital signal for discriminating the focusing state is generated in a circuit block 20 on a basis of a photoelectric converted signal from a photoelectric converting block 1 provided with a self-scanning image sensor such as a CCD, a luminance monitor circuit, etc., and focus detection of a TV camera is performed through a microcomputer 30. By fall of the prescribed level of the output of the monitor circuit in this block 1, the output of an AND gate AN1 is inverted to the high level, and the reset pulse of the high-level Q output is generated from a reset pulse generating flip-flop DF1 to reset a transfer clock pulse generating means 10. Simultaneously, the shift pulse is generated from a shift pulse generating flip-flop DF2, which is connected to said flip-flop, without delay. Consequently, the CCD is not saturated even in case of a bright object to detect the in-focus state accurately.

Description

Detailed Description of the Invention Technical Field The present invention relates to focus detection of a camera using a self-scanning image sensor having a charge storage section forming an image sensor 1t-alnoy and a transfer section for transferring the accumulated charge. Regarding painting.

Prior art In the above J: Una camera focus detection device and No. 1,
The charge storage section and the transfer section are respectively F1-diode array and CO.
D-Sif! ～CCD Couplcd consisting of registers
) is known as a self-scanning image sensor. In this case, when a positive pulse called an integral clear pulse is input to the CCD, each photodiode composing the photodiode array is charged to approximately the power supply voltage level, and then the integral clear pulse A disappears. discharge (hereinafter referred to as Nfill of negative charge)
Thinking of this, charge accumulation and discharge start. Then, when a positive pulse called a shift pulse is input to the COD, the accumulated charge is transferred from each 741 to the diode to the corresponding 1a) cell, and the CCl is transferred at a predetermined period.
) is input into the transfer sunset pulse -C
The accumulated charges received by the transfer section are sequentially transferred to the image signal output circuit. The accumulated charge that is sequentially transferred from this image signal horn circuit is converted into a voltage signal and output,
The focus adjustment state of the photographic lens can be detected by A/D converting them and then performing dedicated processing according to a predetermined program.

Incidentally, the timing of generation of the above-mentioned shift pulse must be avoided depending on the brightness of the subject. However, if the subject is dark, each photodiode in the charge storage section 81 will not be able to store enough charge, and if the subject is bright, each photodiode will The accumulated charge becomes saturated, and in any case, only 1q of reliable image signals can be obtained. For this reason,! The structure changes the generation timing of the shift pulse according to the l'l II degree, and includes a monitoring light receiving means, and the output recovers to the initial level approximately equal to the power supply voltage level upon generation of the integral clear pulse. A monitor circuit configured to reduce the output at a speed corresponding to the output of the monitoring light receiving means at the same time as the pulse disappears; 7t for determining that the output of this monitor circuit has decreased to a predetermined level;
1 constant means is provided, and the shift 1 to pulses are configured to be generated when a determination is made by this 'I'11 constant means. However, on the other hand, the shift pulse is generated independently of the transfer lock pulse. In other words, if the shift E pulse is generated while the accumulated charge is being transferred from the charge transfer section to the image signal output circuit by the transfer lock pulse, the old and new accumulated charges will be mixed in the charge transfer section. This causes the image signal to become meaningless.For this reason, in the past, a transfer lock pulse (
In COD, transfer lock pulses of two or more phases are necessary for charge transfer.Since charge transfer starts at the falling edge of V, only the period when the transfer lock pulse of that particular phase is rising. Shift 1 - Shift the configuration that allows generation of pulses Shift the configuration 5 above that changes the timing of pulse generation according to the luminance
- It was common to provide it with. However, in such conventional cases, it is not always determined that the output of the monitor circuit has decreased by a predetermined one level during the period in which the transfer lock pulse of the specific phase is rising. If that judgment is made while the transfer lock pulse is falling, the next time the transfer lock pulse is
When the pulse 'jff 4) approaches and the subject is bright, there is a problem that the accumulated charge of the 7th diode in the charge storage section is already saturated by the time the shift 1 pulse occurs.

An object of the present invention is to provide a focus detection device for a camera that solves the above-mentioned problems.

1. In the camera focus detection device of the present invention, reset pulse generation means is provided (6) for resetting the transfer lock pulse generation means or generating a set pulse in response to a determination that the monitor circuit output has decreased to a predetermined level. Connect the 27F pulse generating means to the Jl pulse generating means and reset the shift 1 pulse to the reset 1 pulse.

Next, an example of this ti Ming will be explained with reference to Figures 1 to 11 of the Song Dynasty.

First, the overall circuit of this embodiment is shown in Figure 1.
(1) As described in 4 below, for example, a CCD (T self-scanning image lens) equipped with a self-scanning image lens, a picture frame signal output circuit, a light receiving element for brightness monitoring, a brightness monitoring circuit, and a reference signal generation circuit. Photoelectric conversion block (10) is a transfer lock pulse generation block [Tosok (20) is photographed based on the signal from photoelectric conversion block (1)] Forms a digital signal that is the basis for determining the state of the focal point a of the nons The circuit block (30) is a microcomputer that determines the focus adjustment state of the first lens based on the digital signal from the circuit block (20) and also controls each circuit block.

Further, (40) controls the amplification factor of the amplification product in the circuit block (20) based on the output of the brightness monitor circuit in the photoelectric conversion block (1), and controls the amplification factor of the amplification product in the photoelectric conversion block (20).
1) A brightness determination circuit that controls the charge accumulation time (photocurrent integration time) of the self-scanning image sensor 1, (△N1
)(8N2) is an AND circuit that constitutes a gate means together with an OR circuit (OR1), and (DF1) is an AND circuit that resets flip-flops (FFO) (FF1) to (FF6), which will be described later. D flip 7 that generates
O block, (DF2> is a D flip 70 block that generates a shift pulse to transfer the charge accumulated in the charge storage section in the image sensor to the transfer section, (CI1) is a clock circuit that generates a reference clock pulse, (FFO) is an R-S flip-flop.

Figure 2 shows the above-mentioned photoelectric conversion block (1), so the photodiode array (P i > (P 2) (R3
)=-(Pn-2>(I)n-1>(Pn) Image sensor array (PA), fFi clear gate (ICG), Schiff 1 to Geh (SG), CCD
A self-scanning image sensor as described above is constructed in the shift register (SR). Here, the number of cells in the COD shift register (SR), which is the transfer unit, is three more than the number of photodiodes (number of pixels) in the image sensor array (PA), which is the charge storage unit, and the number of cells (R1)
〈R2) (R3) is for the blank feed described later, and is image 1? A diode ([
)1) (P 2>(P 3) -(Pn-2) (P
The accumulated charge of n-1) (Pn) is charged cell (R4) (R
5) (R6)...(Rn -1-1> (Rn +
2) Transferred to CRn +3). As shown in FIG. 3, the 7AI-diodes are connected in parallel to each other via a 1J switch (S) corresponding to an integral clear group 1 to (TcG) with respect to the power supply (V). It consists of a pair of diodes (Dl) (D2) and a FET (Q10),
One diode (Dl) is installed to receive light. The FFT (Q10) keeps the voltage across the diode (Dl) substantially constant, and is set at a constant value ignoring the capacitance of the diode (Dl), so its terminals are grounded. Now, when the switch (S) closes, die A
Charge is accumulated between the anode and cathode of the - node (D2), and the anode voltage becomes equal to the power supply voltage. and,
Next, when the switch (S) is heard, the diode (D2)
is FET (Q10) by photocurrent of diode (Dl).
), and its anode voltage decreases over time.

1 rope 15, this is based on the assumption that a negative charge is accumulated on the cathode of the diode (D2) at 31 degrees, which corresponds to the intensity of the light entering the diode (Dl). ,
The explanation will be given on the assumption that each photodiode accumulates charge at a speed corresponding to the intensity of light.

The above switch (Sl) is actually the integral clearing gate t(I
Pass through by the integral clear pulse input to CG>,
It consists of a # conductor analog switch that becomes inoperable when the pulse disappears. The shift gate (S G ) is a photodiode (Pl) (P 2 > (P 3) −=
The accumulated W4 charge of (Pn-2> (Pn-1) (Pn)10- is received by the shift pulse described later and the cells (R4) (R5) (R6) of COD shift 1 to resist (SR) are
>-... (Rn + 1> (Rn to 2) (R
n + 3> in parallel. )711-Diode (Pl) (P2) (t]3>...(Pn-2>
The charge accumulation l of (Pn-1> (Pn) is completed by inputting a shift pulse to the shift gate h (SG).

Furthermore, each time the transfer lock pulse (φ1) (φ2) (described later) is input, the CCD shift register (SR) sequentially transfers the accumulated charge of one cell at the falling edge of the transfer lock pulse (φ1) as described below. Output to the image signal output circuit. Note that a predetermined number (1
0 photodiodes (Pl) (F2)...(F
10) is covered with an aluminum film and is used for dark output correction as described later. (1-8) in Figure 2
(T9) is the image sensor-1 circuit (MO) described above (
R8) (vs)k: A power supply terminal for supplying power (+V).

However, the position of the image sensor array (PA) in the camera depends on the focus detection method.
niJ becomes 5'1. FIG. 4 shows an example of a focus detection optical system to which the present invention can be applied, where (TI-) is a photographing lens, (<', l-) is a condenser lens (+, , IM+-( +-2) is 1 Saisho 1 Nons (T
L, ) is a pair of re-imaging lenses arranged symmetrically with respect to the optical axis (fl), (M) is a mask, and (') is a mirror lens () that is equidistant to the film plane of the camera. T
I-) is the planned imaging plane of ゛. According to this optical system, Ii! l image plane (F
a However, the first one in the image sensor array (PA)
, the interval between the second images depends on the focusing state of the fine lens (TL),
That is, it changes depending on the state of deviation of the subject image formed thereby with respect to the expected imaging plane (F). Therefore, if the interval between the first and second images is detected based on the output of each pixel of the image sensor array ([)A), the amount of defocus and defocus that indicate the focus adjustment state of the R shadow lens (T L ) can be determined. The direction can be determined, and the output processing method necessary for this will be described later. In addition, in Figure 4, image 1'! The array (PA) includes a condenser lens (C1~) and a pair of reimaging lenses (1, 1).
A position that is conjugate to the expected imaging plane (F) at an interleave angle of (+2) is placed in the vicinity thereof.

Again in Figure 2, (MP) is a 77t diode which is a light receiving element for brightness monitoring, and (MO) is a brightness L.
(R8) is a reference M@ generation circuit, and (VS) is an image signal output circuit. The brightness monitor circuit (MC) consists of FETs (Q 1) (Q 2) (C3) and a capacitor (CI).

The gate of the FET (Ql) is connected to the integral clear gate (3) of the image sensor, and is passed through by the integral clear pulse that passes through the integral clear gate (ICG), which causes the fundener (C1) to change to the power supply voltage. (+V).FET (Ql
) and the capacitor (C1) connection point (Jl) is the FET (C
12) is connected to the anode of the FET1Q2), while the FET1Q2) is connected to the anode of the FET1Q2).

The gate of the FET (C12) is grounded, and the FET (C12) is provided so that the voltage across the photodiode (MP) can be kept substantially constant and the influence of the haze can be ignored. FETs (Q 2) (Q 3> are connected in series with the power supply, forming a buffer with low output impedance and high input impedance.
C3> is used in the source follower, so FE
The output terminal pulled out from the connection point of T (Q 2) (C3) (from the latter half, a voltage (Vllll) corresponding to the potential of the connection point (Jl) is output. When the integral clear pulse mentioned above disappears, the FET (01) is non-proprietary, and the capacitor (
C1) is discharged by the photocurrent of the photodiode (MP>), and the output voltage of the terminal (T1) drops accordingly. Figure 5 shows the temporal change in the output voltage of this terminal (T1). Yes, (1+) (L!z) (b)
(J4) (1s) shows that the speed of voltage drop changes depending on the brightness.

The rising edge indicated by (RN) is caused by the integral clear pulse. represents the induced noise.

The reference voltage generation circuit (R8) is an FFT (C4) (Q5
) (Q6) and a capacitor (C2),
These are the FETs (Q 1) (Q 2) (C3
) and capacitor (C1), and their circuit connection is also similar to F in the brightness monitor circuit (MC).
It is the same as the circuit connection of ET (Q 1) (Q 2) (Q 3) and capacitor (C1).

However, the connection point between FET (C4) and capacitor (C2) (
J2) is only connected to the gate of FET (C5), therefore, FET (Q 2) (Q 3)
FET (Q 5) which constitutes a buffer with low output impedance and high input impedance similarly to
Even after the integral clear pulse disappears, the voltage signal output from the output terminal (T2) drawn from the connection point of (Q6)
It is kept constant as shown in the figure. In other words, the connection point (Jl) at the extinction point 1 (To) of the fa clear pulse
(J2) potential is FET (Ql) (Q2
) (Q 3) and capacitor (C1) and FET (Q
4> (Q 5) (Q 6) and :1 ndensa (C
Since the characteristics of 2) are the same, they are equal to each other, so
The voltage signal output from the terminal (T2) is a reference voltage (
Vref).

Image signal output circuit (VS) G; It, FET (C7) (
Q8) (Q9) and a capacitor (C3), preferably also FETs (Q1) (Q2)
(Q3) and capacitor (C1) with the same characteristics. However, in circuit connection, I=ET(
A transfer lock pulse (φ 1) is applied to the goo j~ of C7), and the connection point (J3) between the FET (C7) and the capacitor (C3) is connected to the gate of the FET (QB>). and the image sensor's COD shift register (5).Therefore, each time one transfer pulse (φ1) is input, the FET (C7)
conducts, the capacitor (C3) is charged to the level of the power supply voltage (→-V), and the image signal output circuit (VS) is reset, but the COD shift register transferred by each transfer pulse (φ 1) It is repeatedly discharged according to the accumulated charge in (5), and eventually becomes a buffer with low output impedance and high input impedance? FET (C8) that makes up
From the output terminal (T3) pulled out from the connection point between and (Q9), the output corresponding to the accumulated charge of each photodiode, which is a pixel of the image sensor, is sequentially output as a voltage signal (MO9).
are output, and together they form an image signal.

Note that (CI> (C2) (C3) in the above circuit (MO) (R8) (Vs) was explained as a capacitor for convenience of explanation, but it can be replaced with a PN junction of a diode, and these In the case of Tohoseki J8, each circuit is manufactured as a diode.In addition, a photodiode (MP), which is a light-receiving element for the monitor, is placed near the image lens array (PA) to absorb a portion of the light that has passed through the photographic lens. It is placed at J: which receives the light.

Next, referring again to FIG. 1, an example of the circuit configuration of the transfer lock pulse generation block (10) that generates the transfer lock pulses 17- (φ1) (φ2) will be described.

(FF1) (FF2)...(FF6) are flip-flop circuits forming a frequency dividing circuit, and the T input of the first stage flip-flop (FF1) is connected to a clock circuit (C
A clock pulse (period: 271 seconds) from L1) is input. Flip 70 Tsubu (FF3) (FF4) (
The Q output of FF 5) (FF 6) is an OR circuit (OR2
), and the output of the 17 circuits (OR2) is input to one input of the AND circuit (AN4). The other input of the AND circuit (AN 4) is connected to the microcomputer (30) via the inverter (INl).
When the terminal (T22) outputs a signal of °0'', this AND circuit (AN
From 4), the signal of °1'' of the OR circuit (OR2) is 1.
Powered.

- One input of the AND circuit (ANS) is connected to the clock circuit (CL2), and the other input is connected to the above terminal (
T22) and therefore the terminal <T
When 22) outputs No. 13 of °1'', 18- goes up and outputs an ear 0 clock pulse from the 1 clock circuit (CI 2).Here, the clock pulse output from the clock circuit (C10) The period is determined by the clock circuit (C11
) The output of the flip-flop FF6, which divides the output clock pulse (C6), is set to several tens + 8 times wider than the period of the clock pulse outputted from the OR circuit (OR3). When either output signal of !i) is 1", the signal of "1" is transferred and the lock pulse (φ
2) COD shift 1 in photoelectric conversion block (1)
Outputs to Nojista (SR). Also, OR circuit (OR3>
An inverter (IN2) is connected to the inverter (IN2), and this inverter (IN2) transfers a signal with the opposite phase to (φ2) and a lock pulse (ψ1) to the photoelectric conversion block (1).
COD shift] to output to register (SR) and image signal output circuit ("V3) (see Figure 2).
The 1'' signal from the terminal (T22) of the microphone [1] microcoater (30) is a signal for performing the initial 1/rise operation on the image 1-line.

FIG. 6 shows an example of the I11 degree determination circuit (, '10) and the circuit block (20). In this diagram (T 10)
<T11> (T12) are the terminals (T1) (
T2) (T3) is the terminal connected to the terminal (
TI3> (T15) (T16) are connected to the data bus (DB) from the micro combi coater (30) as described later.
1>, a latch pulse, sample designation pulse, and sample designation reset pulse are input. , terminal (T
14) is connected to one input of the AND circuit (AN2) in FIG. First, to explain the brightness determination circuit (40), this circuit is the above-mentioned Y@degree monitor circuit (MC).
A comparator (AC1>(A
C2) (AC3) (AC4) -C.

The inverting inputs of these comparators are connected to 6G (T10) via a buffer (B1). On the other hand, these comparators (8 CI) (AC2) (AC3) (AC
The non-inverting input of 4) is a resistor (R1) and a constant current source (11).
connection point (+4>), connection point (+5) between resistor (R2) and constant current source (T2), connection point (+6) between resistor (R3) and constant current source (13), resistor (R4) and constant current It!(14) is connected to the connection point (J7) and the resistor (R1
) (R2) (R3) (R4) connects the buffer (B2) to the fr T terminal (T11>. With this kind of circuit connection, the connection point (J 4) (J !i
) (J 6) (, +7) is the voltage (■ r
ef) to resistances (R1) (R2) (R3) (
A voltage is generated by subtracting the voltage drop at R4), and the resistance value of the counter (R1) (R2) (R3) (R4) and constant current source (r 1) (12) <1 3> (14
) 471m value, the comparator ( A.C.
1) The outputs of (AC2) (AC3) (AC4) are sequentially “
Reversed from O'' to °゛1''. (DF3>(DF4)
(DF 5) each has a D input as a comparator (AC1) (A
C2) D flip 70 connected to the output of (AC3)
The latch pulse from the microcomputer (30) in Figure 1 is transmitted through the terminal (T13) a predetermined time (100111 seconds) after the fall of the integral clear pulse. is input. Then, when that latch pulse is input, D
Flip 70 Tsubu (DF 3> (DF 4>(DF5
) is the previous comparator (AC1) (AC2) (AC3)
The outputs of the Q outputs are respectively outputted to the Q outputs, and the inverted outputs are outputted from the Q outputs. (AN6) is an AND circuit in which one input is connected to the Q output of the D flip-flop (70 < DF3), and the other input is connected to the Q output of the D flip-flop (DF4).
(AN 7) has one input as D flip-flop < DF
(a) is an AND circuit in which the Q output of 4) is connected to the Q output of the D flip-flop (DF5).
, (DF5) Q output (d), and comparator (AC4)
The output (fl > is the output of the brightness determination circuit (40). In other words, those outputs are the outputs of the monitor light receiving element (PM
) indicates the brightness level detected by the 22-'TI signal.

To explain this in more detail with reference to Fig. 5 (), in Fig. 5 (J!l) ()2) (, R3) (fl14
) Gma integral clear pulse ll'4 iIj! If the voltage drop that occurs from point 117 (lO) to time point (13) after the above-described predetermined time (100 msec) is less than 0.35 V, if from 0.35 V to less than 0.7 V, 0.
7v to less than 1.4V, 1.4v to 2.8V
It shows the change in the output voltage of the brightness monitor circuit (MO) when less than It shows the output voltage change of the same monitor circuit (MO>) when a voltage drop of 2.8V occurs at <i
t> (Jz) (13) (1'+) (15) Which voltage drop will occur depends on the magnitude of the photocurrent of the monitor light receiving element (DM) as described above, and the brightness monitor circuit (MC) output voltage change is ()1)()2)(
)3) ()4) In the case of L11 low brightness,
A case like ()5) is a case of high brightness. now,
A reference voltage generation circuit in which the voltages of terminals (T4) (J5) (J6>(T7>) are input to the terminals (T11), respectively (
R8) output voltage (Vref), respectively 0.35V
.

The resistance values of the above-mentioned resistors (R1) (R2) (R3) (R4) and constant current source (11) (I 2) (13> (14)
> When the current value is set, the D flip-flop (DF 3) < DF 4) (DF
5) Q output, Tsuta output, and brightness monitor circuit (MC)
The output (a>(b)(c)(d)(e) is as shown in Table 1 below.

Table 1 Note that in the case of (J da), the output (d
) is the predetermined time (
"o" at the time (T2) before 100 msec) has elapsed.
becomes “1”.

The remaining circuits in FIG. 6 constitute the circuit block (20) in FIG. 1. 5 (22) is an image signal output circuit (VS) which is input from the terminal (T12) via the buffer (B3).
81 Electric Power IEfE (Vos),! :, buffer (B2
) is a subtraction circuit that generates an output (vl) corresponding to the difference from the output voltage (Vret') of the reference signal generating circuit (R8) inputted from the terminal (Tll) via the terminal (Tll). (24) is a predetermined number (10) of diodes (R2) to (PO) covered with an aluminum film that is applied to the image sensor array (PA). P
2) This is a peak value detection circuit that detects the peak value (V2) (II low level pixel signal) of the image signal corresponding to the accumulated charge excluding (Q9) and outputs it with a latch signal. Therefore, the accumulation of photodiodes in the image sensor array (PA) receiving the above-mentioned first and second images, which are not covered with an aluminum coating, is applied to the pixel signals corresponding to the charges, so-called dark output correction. A signal \/2 is generated. , a single micro-amp coater (30) transfers one pulse (φ
1) (ψ 2) J: CCD shift register (SR
When accumulated charges are sequentially transferred to the image signal output circuit (vg> from ), then cell (R12)
At the same time as the transfer of the accumulated charge is completed, a sample designating pulse is sent to the terminal (T16) via the data bus (DB1).
Output to. Therefore, the peak value detection circuit (24) takes in image signals corresponding to the accumulated charges of the cells (R5> to (R12), or in other words, the accumulated charges of the photodiodes (R2) to (R9)), and detects the peak value among them. The value will be detected/examined.

(26) is the output signal (V
1) An amplifier that differentially amplifies (V2), the amplification factor of which is the output (a) and (b) of the brightness determination circuit (40) described above.
<C,>(d) is an amplifier configured to be controlled by 26-. In this amplifier, (
OP) l is an operational amplifier whose input terminal (f)
((1) is a circuit (
22) and (24), respectively.

(7) to (R14) are resistors provided for setting the amplification factor of the operational amplifier (OP), and (R5)<r
< O) (R7) (R8) (R11) (R12
), then (R9) (R13) is 2
The resistance value of r, (R10) (R14) has a resistance value of 4. (ΔS 1) to (As 8) are analog switches, among which (As 1) to (As 4)
(a) (b) (c) (d) selectively enables the resistors (R7) to (R10) according to the outputs (a) (b) (c) (d) to set the feedback resistance value of the operational amplifier (OP). A
s5) to (As8) are outputs (a) (b>(G)
The bias resistance value of the amplifier (OP) is set by selectively enabling the resistors (R11) to (R14) according to (d). That is, the above <h><Iz><Iy)
(J4) When each voltage drop of <J5> occurs, the states of those analog switches and the enabled resistances are as shown in Table 2 below.

In the upper table of Table 2, A is the amplification factor of the operational amplifier (OP), and the output voltage of this amplifier (OP) is Vout = E+ (V
2-V 1) is represented by XA, which is input to the A/D converter <ADC>. However, E is the voltage of the constant voltage source (E), which is appropriately set according to the input level range of the A/D converter (ADC). Each output of the ADC is connected to the data bus (DB
1) is taken in via 1, and the focus adjustment state of the imaging lens is detected by digital calculation based on a predetermined program. In this way, the amplifier (26) in FIG. 1 changes the amplification factor according to the output of the brightness determination circuit (50) and outputs a signal suitable for signal processing in the A/D converter (ADC). It is possible to adjust the focus state of the photographic lens over a wide range of brightness.

Referring to FIG. 1 again, the terminal (T17) of the microcomputer (30) is the output terminal of the integral clear Paris. In addition, a signal of "1" is output from the terminal (THI) of the microcomputer (30) when generation of a shift pulse is permitted, and as described later, a signal of "1" is output from the image sensor array (PA) to the CCD shift register (S).
During the transfer of the accumulated charge to R), a signal "0" is output that inhibits the generation of shift pulses. Furthermore, the terminal (T18) of the microcomputer (30) outputs a signal of 1''=29- when the above-mentioned predetermined time has elapsed from the time point (10) of extinction of the integral clear pulse. (40)
It becomes a latch pulse for. The integral clear pulse output from the terminal (T17) is input to the integral clear gate (ICG) of the image sensor in the photoelectric conversion block (1) via the terminal (T6), while the integral clear pulse is input to the integral clear gate (ICG) of the image sensor in the photoelectric conversion block (1). Set the Q output to °゛1''
to open the AND circuit (AN 1). Also, when the flip 70 knob (FFO) is connected to the terminal (
Allow shift pulse generation from T18) °゛1''
When this signal is output, the AND circuit (AN 2) is also opened.

From the output terminal (T14) of the brightness determination circuit (40),
Only when the subject brightness is high as shown in ()S) in Figure 5, the time (t2) before a predetermined time (1001R seconds) has elapsed from the time when the integral clear pulse disappears (10)
A signal (0) of °°1" is output. On the other hand, as shown in (1'+) (1'2) (JJ) (14) in Fig. If it is low, the output of the terminal (718) of the microcomputer (30) becomes ``1'' at time (t3), and the output of the output terminal (Tl!1) of the brightness determination circuit 30-(40) ( e) is”
Therefore, when the subject brightness is high, the output of the AND circuit (AN 2) is kept at (12).
1" and the subject brightness is low, the output of the AND circuit (AN 1) becomes °1" at the time (t3), and either one of the 1" outputs goes to D via the OR circuit (OR1). It is input to the D input of the flip-flop (DFl).

Since the CK (clock) input of this D flip-flop is input with a reference clock pulse (period: 2 μs) from the 1-channel circuit (CLl), as shown in FIG. At the falling edge of the reference clock pulse immediately after the signal is input, a D flip (DFl) occurs.
The Q output becomes 1'', the flip-flop (FFO) is re-hit, the open AND circuit (8N1) or (AN2> is closed, and the flip-flop in the 1-pulse generation block (10) is 70 Tsubu (FF1)
to (FF6) are rerenated to 1 to 1, and their Q outputs (Q
l) to (C6) all become "0". And the AND circuit (AN 1) or (AN 2) becomes 1 like that
When closed at , the Q output of the D flip 70 tube (DF 1) returns to O''' at the next falling edge of the reference clock pulse.
In the end, a positive pulse with a time width of 2 μsec was output from the Q output. This positive pulse is the reset pulse. On the other hand, the D flip-flop (DF2) changes its Q output to 1'' at the fall of the t! quasi-clock pulse from the clock circuit (C11) immediately after the Q output of the D flip-flop (DF1> becomes 1''). , D flip 70 knob (D
Immediately after the Q output of [1) returns to °゛0'', the Q output changes to °°O''' at the 1"2 fall of the !^i% pulse of the same clock circuit.
Return to Do I, then D flip [1 knob (DF2
) produces a positive pulse with a time width of 2 μs that rises in synchronization with the fall of the reset pulse, and this is the pulse to shift 1. This shift] pulse is input to the terminal (T21) of the micro combi coater (30), and is also input to the shift gate (1) of the image sensor via the terminal (TI) to the photoelectric conversion block (1). SG).

The above is an explanation of the overall circuit configuration in Figure 1 and the circuit blocks that make it up.Next, before explaining the overall operation, we will refer to Figures 7 and 8 to explain the signal flow in each part. Let me explain.

Figure 7 shows the outputs of the 7 flips (FF1) to (FF6) and the transfer pulse (φ 1) immediately after being reset by the reset pulse that occurs on the Q output of the D flip 70 knob (DPI). and D flip 70tsu 7 (DF2)
It shows the relationship between the shift pulse which is the Q output of . As mentioned above, the flip 70 knob (
FFI) to (FF6) are reset, and their Q outputs (Ql) to (C6) all become °O". As a result, the output of the OR circuit (OR2) becomes °0".
The transfer lock pulse (φ2) falls to "O", and conversely, the transfer lock pulse (φ1) falls to "1". Then, when 2 μs elapses, the reset pulse falls, and this At the same time, the shift pulse rises to °'1'', and this shift pulse falls to °'0'' after another 2 microseconds.Next, the output of the OR circuit 33-(OR2> becomes '1'). , when the Q output (C3) of the flip-flop (FF3) becomes "1", which is 8 microseconds after the signal 1~pulse falls to "0", and the transfer ends. lock pulse (φ
1) is kept in the "1" state for 1011 seconds. The shift pulse is this transfer lock pulse (φ 1) is °°1″
It occurs and disappears while in this state. In this way, (t
2) Or immediately after the time point (t3), reset the transfer lock pulse generation block (10) and apply a shift pulse while the newly output transfer lock pulse (φ1) continues ( ). The image sensor array (
Photodiode array (P1) in PA) (
P2) (P3> -(Pn-2) (Pn-1)
This is to avoid unnecessarily delaying the end point of charge accumulation (integration) of (Pn). If a shift pulse is generated in synchronization with the first transfer lock pulse (φ 1) that occurs after time (t2) or (t3), then at time (t2) or ([3)] From photodiode 1' (
P 1) (P 2> (P 3> ・(Pn-2)(
There is a possibility that the charge accumulation of Pn-1) (1 1)) is performed unnecessarily, and if the subject is extremely bright, the charge accumulation may become saturated and a correct image signal may not be obtained. Further, since it is not always constant at what point after the time (t2) or (13) the shift 1 pulse is generated or reversed, there is a possibility that the image signal level will not be constant. On the other hand, in Fig. 7, 1' of (t2) or (t3): 2 periods (4 u seconds) of the reference clock pulse from point i
Since there will always be a Schiff 1 Hepulse within, I's J: Una fear is ff? It is nothing.

Furthermore, as shown in Fig. 7, the next transfer lock pulse (φ 1) (J output (Q 3 > (Q 4) (Q 5
) (Q6) After 120 microseconds, the signal becomes 1", and the time that this state is maintained is 8 microseconds.

All transfer lock pulses after this transfer cock pulse are in the "1" state for 8 II seconds and then in the O" state for 120 μs. Therefore, the period of the transfer glock pulse (ψ 1) is 128f1 second, and the sonode'-filicle is 1/2r = 4, and the state of °1" is 0".
The duration ratio of the state is +,/15.

In this way, the accumulated charge from the 1tr of the shift 1 register (SR) is transferred to the image signal output circuit (VS) at the falling edge of the transfer lock pulse. Signal processing, especially Δ/D converter (ADC)
An inexpensive △/D converter that can sufficiently maintain 1ifr of A/D time at (ADC> and (
], it is possible to achieve a [stop-down] of the camera using this.

Figure 8 transfers the output of the image signal output circuit (VS) and amplifier (26) after the shift pulse of the image sensor is generated, together with the output of the lock pulse (φ1) (φ2) and reference signal generation port N (R8). I'm in a "show" style. In the case of Figure 7,
When shift 1~pulse occurs, COD shift 1~1
It is assumed that the nozzle (SR) is in an empty state. To create this empty state, a photodiode (P
1) (P 2) (P 3>−(Pn-2> (P
Transfer the accumulated voltage v1 of n-1> (Pn) to the CCI) shift 1 register (SR)'J<, transfer the number of cells from COD shift 1 to the register (SR) and apply the lock pulse (φ 1) ( φ2) can be given to the register. For example, if the number of registers (SR) is 100, 100 transfer lock pulses (φ 1)
If and (φ2) are increased by 5, all the accumulated charges in that register will be discharged. lfl 1, when the image sensor is first started, one charge discharge operation will cause COD.
In reality, the accumulated charges in the shift registers (SR) are not completely discharged, so in this case, the discharge operation is usually not repeated several times and a complete empty state is created.

Such a series of operations is called an image 17 n→boo initialization operation. In FIG. 8, the generation of the shift pulse causes the diode (Pl) (P2) (
P 3> ・” (Pn-2) (Pn-1> (Pn
) is transferred to the CCD shift register (SR) in parallel, and the first transfer lock pulse (φ 1
), the accumulated charge in the cell (R1) is transferred to the image signal output circuit (VS). As a result, 37-Image 'WJ output output circuit S) has a cell (
The cell (R2) (R3) =-(ltn -1-3>) is outputted every time the transfer lock pulse (φ1) falls.
The output corresponding to the accumulated charge (Vos2) (Vos3
)...(■os(n+3)) are sequentially output from the image signal 01 output circuit (VS). Among those outputs, (Vosl ) (/Vos2 > (Vos3
) are the outputs corresponding to the accumulated charges of the idle feeding cells (R1) (R2) (R3), and (VO34) to (V
0813) is aluminum-coated die 1 to die A
-Do (Pl)0 to (Pcar), that is, storage 1i of cells (R4) to (R13)! ! This is the dark output corresponding to the I charge. As shown by ΔS, there is a difference between these two types of outputs (corresponding to the amount of accumulated charge) based on the dark current generated in the photodiodes (pl) to (P10).

The output of the arithmetic circuit (22) indicated by (Vl) is
3) was obtained by calculating V1=Vref -VO3, and the dark output (VO84) to (
Output 38 of the arithmetic circuit (22) corresponding to V 0813)
- Uu (Vos5) to (vos12) D corresponding puzzle'
b (7) h'j The above peak value detection d1 circuit (24)
be taken into account. Then, the peak value detection circuit (24) outputs the maximum value on the back as (v2) and 1°C.
Output. In the WS7 diagram, the dashed line indicates this (V2) (
), therefore, V-=V 1-V 2 is ■ou
An amplifier (2
G) corresponds to the output.

Next, the operation of the micro combi coater (30) shown in FIG. 1 and the operation of the entire circuit will be explained with reference to flowchart [7-7] of FIG.

First, when a star 1~ signal is given to the microcomputer (30) by operating a switch (not shown), #1
In step , the micro combi coater (30) connects the terminal (T
22> to perform the initialization operation of the image sensor.

In other words, the fast-cycle clock pulses from the transfer circuit (Cl3) as transfer lock pulses (φ1) (φ2) are transferred to the COD shift register (S R) via the transfer lock pulse (φ1) (φ2). is input. At this time, from the terminal (T19), shift 1 to 1, which prohibits the generation of pulses, is transmitted.
3 "o" is output and shift 1-pulse does not occur, so COD shift 1-regisk (s R> t
, t sequentially discharges its own accumulated charges without receiving accumulated charges from the image sentry array (PA). (Alternatively, it is not forbidden to generate shift pulses, but normal C
Generate an integral clear pulse at the CD driver 8 and exit 1, then immediately generate a shift 1~pulse so that the accumulated charge can be ignored, then transfer it to a lock pulse (CCl) Shift 1~] Even if the accumulated charge in the nozzle can be discharged, 1: No.

) This draining operation is repeated several times as a series of -1s, thereby leaving the COD shift register (SR) empty. Here, the lock pulse (φ 1) is transferred by the number of hills of one discharge operation + i COD shift register (SR) (
φ 2) is given, the termination J is completed. When the predetermined time period that guarantees several discharge operations has elapsed, the micro combi coater (30) changes the output of the terminal (T22) to “°
A lock pulse (φ 1 〉, and inverts the pulse with the opposite phase to the K clock pulse (φ2) and inputs it to the COD shift 1 register (SR).Next, the microcomputer 1 (30) inputs the terminal ＜ in step #2. T19>
outputs a 1" signal that allows the generation of shift 1-pulses, which opens the AND circuit (AN ÷). Then, in step #3, an integral clear pulse is output from the terminal (T17). and flip-flop (FFO)
is set, and AND rotation i'fi (AN4) is also interrupted. At the same time, the integral clear pulse is activated by the integral clear gate (T
CG) and image lenser array (PA
) are cleared, while the FETs (Q1) (Q4) conduct and charge the FETs (C2) to the level of the power supply voltage. This integral clear pulse disappears at the time of 0), and as a result, each of the diodes 7A1 to 7A1 of the image lens array (PA) starts accumulating charges, and at the same time, the light detected by the monitor photodetector (PM) 41- The output voltage (Vm) of the brightness monitor circuit (MC) begins to drop ( ) as shown in FIG. In addition, at the same time as the integral clear pulse disappears in the micro combi coater (30), the internal programmable preset counter is set at step #4, and this counter starts counting a predetermined time of 100 msec. Next, in step #5, the microcomputer (30) lowers the output voltage (Vm) of the brightness monitor circuit (MO).
<2.8V is determined based on the output (e) of the luminance T constant n path (40) input to the end "F (T20), and the output (e) is 1". So, in Figure 5 (1
When it is determined that the case shown in 5) is the case, the process moves to step #9 and the output of the terminal (T19) is set to °°0'', and the generation of shift pulses is prohibited.However, the output (8) When becomes 1'', as shown in Figure 6, a reset pulse is issued from the D flip-flop (DPI>) in a very short time, followed by a pulse from the D flip 70 block (DF2) to shift 1, and then J: to reset pulse 7
The lip-flop (FFO) is reset and the AND circuit (AN 1 > (AN 2)
is closed, so Schiff 1 is prohibited from occurring in step #9.
The ~ pulse is a shift pulse that may be newly generated after step #10, which will be described later.

On the other hand, if it is determined in step #5 that the output (e) is °゛O'' and one of the cases shown in Fig. 5 is <J+) (T2) (L) ()4), , the microcomputer (30) subtracts 1" from the contents of the programmable preset counter described above in step #6, and
In step 7, it is determined whether the content of the counter has reached °゛O''.If the content has not become ``0°'', the process returns to step #5, passes through step #6, and then returns to step #7. In step , it is again determined whether the contents of the programmable preset counter have reached 0''.

Here, if the time required for the step cycle of #5, #6, and #7 is shifted from 1S, it is set so that tsx N = ioom seconds.
6. If you repeat step #7, the contents of the programmable preset counter will become °°0''. That is, #4
At the step of , this counter outputs a signal of 1°, and this signal is passed through the AND circuit (AN 1) (OR
1) is input to the D input of the D flip 70 tube (DFl). Therefore, D flip-flop (DF
A reset pulse is output from 1>, the flip-flop (FFO) is reset, and the AND circuit (AN?) is output.
While (AN 2) closes, a shift pulse is subsequently generated from the D flip 70 knob (DF2). However, in this case, more time passes and the brightness monitor circuit (MC
) reaches 2.8■, the output ((3) of the brightness determination circuit (40) becomes '1'', which is determined in step #5, Terminal (T
From 19) onwards, “0” prohibits the generation of shift pulses.
g8 is output.

The shift pulse generated as described above is input to the terminal (T21) of the microcomputer (30), and is also input to the shift gate (SG) via the terminal (T7).
is input. This allows the image lenser array (
The accumulated charge in each photodiode in PA) is transferred to the corresponding cell in the COD shift register (SR>), and the accumulated charge in each cell in that register (SR) is sequentially transferred by transfer lock pulses (φ1) (φ2). The image signal output circuit (VS) outputs the image signal (VO31) from the output terminal (T3) of the image signal output circuit (VS).
) (VOS2) =-(Vos(i + 3)
) are sequentially output, and the amplifier (26) outputs yout=E
Signals represented by +(V1-V2)A are sequentially output. These signals are sequentially converted into digital signals by an A/D converter (ADC) and input to the microcomputer (30) via a data bus (DB1).

On the other hand, when the above-mentioned Shift Me pulse is input to the terminal (T21), the micro combi coater (30) outputs an integral clear pulse from the terminal (T17) in step #10. For this reason, the accumulated charge in each photodiode of the image sensor array (PA) is cleared, and charge accumulation in each photodiode is restarted at the same time as the integrated clear pulse disappears. Of course, the output of the brightness monitor circuit (MC) also begins to fall at a speed corresponding to the subject brightness detected by the monitor light receiving element (PM), as described above.

That is, the second charge accumulation cycle is started, but at the same time as the integral clear pulse disappears, the micro combicoater (30) changes the internal programmable preseller 1 to counter to the COD shift 1 register (SR) cell. Set it to count. This is step #11. The microcomputer (30) receives the digital signal corresponding to the accumulated charge of each cell from the A/D converter (ADC) and stores it in the internal random access memory (step #12), each time. The programmable preset counter 1 is decremented (step #13), and it is determined in step #14 whether the contents have become 0''.

When the content of the programmable preset counter set in step #11 becomes 0'', the process moves to the next step of =46-#15. In this step, the micro combi coater (30) performs the following calculation, for example. The focus adjustment state of the photographic lens (T L ), that is, the defocus amount and defocus direction with respect to the expected focal plane (F) are calculated.In other words, the F1 diode of the image sensor array (PA) is calculated. (P 1) (B
2) (P 3) -(Pn-2)(Pn-1) (P
n ) minus (Pl) to (Plo), those included in the area where the first image is formed in FIG. The photodiodes included in the reference part are the photodiodes of the reference part, and the photodiodes of the reference part and the reference part are respectively (A1
) (A 2) - (Am), (B 1) (B 2)
...(3m + -1), the charge accumulated on them corresponds to 1 node.DeCI from the A/D converter (ADC) = *l ai-bi l Deposit 1 C2-Σ1a+- bt+il λt- Ck-1=-Σ 1 ai-bi+ -2l-1 Ck -Σl ai -bil-k-1l Perform set operations on C1, C2...Ck-1, Ck Find the minimum value. For example, if the value of C2 is the minimum,
Photodiode in the reference section (Δ 1) (A 2)...
・The photodiode of the reference part (B 2 > (B 3)...(Bm ) (am
+ The image formed in 1) matches best. Therefore, in this case, the distance between the photodiodes (A1) and (B2) on the image sensor array (PA) is the distance between the first and second images described above, and this is determined by the focusing time determined by the focus detection optical system. By comparing with the predetermined interval between the first and second images in , it is possible to calculate the defocus amount and defocus direction of the photographing lens at that time. Note that the ml method described here is just an example, and in order to more accurately determine the defocus level, for example, the applicant has developed a special method. ! Showa 58-
It is sufficient to use the calculation method proposed in Japanese Patent Application No. 113936/1988 by the No. 2622 Bow.

When the above calculation in step #15 is completed, the micro combi coater (30) again calculates the voltage drop of the output (Vm) of the brightness monitor circuit (MC) based on the output (e) of the brightness determination circuit (40). Amount from step #11 to #15
It is determined in step #10 whether 2.8■ has been reached in the period. It is assumed that, for example, 50 m seconds are required to execute steps #11 to #15. If the output (e) is °゛1'' and the voltage drop of the output (Vm) has reached a!2.8V, then in step #17 output the integral clear pulse again from the terminal (T17) and #
While performing steps #12 to #15, the image sensor
Clears the charge accumulated in each photodiode 14 of the array (PA) and causes them to start accumulating charge again.

The reason for doing this is that if the output <e> is °1'' at the time of determination in step #16, the charge accumulation in each photodiode of the image lens array (PA) is already equal to 49
This is because there is a possibility that it is saturated with . In this case, the microcomputer (30) sets the internal programmable preset counter to count 100 msec at step #17 at the same time as the integral clear pulse disappears, and then from the terminal (T19) at step #18. A signal of "1" is output to permit generation of the shift pulse. After this, return to step #5 and repeat the above steps in sequence. On the other hand, in step #1G, output ( e) is °“o”, and if the voltage drop of the output (Vm) has not reached 2.8, the microcomputer (30) sets the programmable preset counter to 50Il for 1 second in step #19. Set it to 9 to count, then move to step # above.

At this point, the counter is set to count 50 msec. As mentioned above, the 84-minute clear pulse output in step #10 disappears, and the counter is set to count 50 msec.
0111 seconds is one elapsed time, and if the remaining 5ON1 seconds are counted by the counter, each Fol-diode of the image sensor array (PA) 50- will be allowed to accumulate charge for a total of 100 msec. It is. That is, in this case, the step cycle of #5, #7, and #8 is repeated 507'jS times. Of course, if the program counter cannot be used for other purposes and can be used exclusively, after completing step #10, the program counter can be used for 100 msec. Step #20 is not necessary.

Above, please refer to Figure 9. InoC Micro Combi Coater (30
) The operation of the entire circuit has been explained, but as can be understood from the above, in this embodiment, the image 1? The generation of new shift pulses is prohibited from the time the transfer of the accumulated charges of the photodiodes of the optical array (P', A) begins until the amount of defocus and the amount of defocus in the micro combi coater (30) are completed. In addition, each photodiode of the image lens array (PA) starts accumulating charges immediately after the previous shift pulse is generated, without waiting for the end of the performance. The reason for this is as follows.

In other words, the photographing lens is driven based on focus detection,
When performing the focus adjustment, the Kensho lens can be brought into focus in a short period of time since the number of focus detection operations performed within a certain period of time is large. Now, considering the time required for one focus detection operation, which is 1J, it is the time required for charge accumulation (photocurrent integration) in the image sensor array (PA) of the COD.
What, the accumulated charge of that image sensor is COD.
The image (8th output circuit (VS)) is transferred to the 8th output circuit (VS) via the shift 1 resistor (SR), and then the signal processing step 4
- Time Td required to calculate the amount of debris and defocus direction (for convenience, this is called data processing time) (D
sum (Ti −+−Td ) tear V), focus rm detection a
Sakuwoli! When repeating is performed continuously, the next detection operation is performed after the previous detection operation is completed. In this case, the time required to perform 0 detection operations is (Ti and Td).
×n. However, the image of COD is the charge storage f! The speed of (photocurrent integration) depends on the intensity of the light input to it. If the intensity of the incident light is low, the speed becomes slow and charge must be stored for a long time. For this reason, the time required for one focus detection operation becomes long, and the number of focus detection operations that can be performed within a certain period of time is restricted, making it impossible to bring the camera lens into focus in a short time. On the other hand, in the case of COD, from the shift 1 register (SR) to the image signal output circuit (VS)
(Transfer the accumulated charge to the image sensor)
There is no problem in allowing the array (PA) to accumulate charges. Therefore, the integral clear pulse can be generated immediately after the shift pulse is generated, and thus, if 13, then l2i! Since the image lens array (PA) accumulates new charges during the data processing time Td of i, the time required for one focus detection operation is short even when the incident light intensity is low. The number of focus detection operations performed increases, making it possible to focus the photographic lens in a short time.However, on the other hand, COD
While the accumulated vA charges in the shift register (SR) are being transferred to the image signal output circuit 53- (VS), new accumulated charges are transferred to CO.
When transferred to the D shift register (SR), this is possible due to the structure of the COD), and the old and new accumulated charges are mixed in the COD shift register (SR), resulting in an incorrect image. The @ signal is output.Also, even if d'3 is in the micro combi coater (30), the data in the random access memory must be held at 1 during the calculation in step #15, so a new signal is output. Therefore, the shift 1-pulse is prohibited during the data processing time Td described above.

FIGS. 10(A) and 10(B) illustrate how the focus detection operation is repeated in the above embodiment. is T1]
- This is the case of Td. In the same figure (Δ), the dotted line indicates the charge accumulation period after the integral clear pulse that occurs in step #10 is exhausted, but the charge accumulated during this period is generated in step #17 as described above. Cleared by integral clear pulse. In contrast, Fig. 11 (A) (B
) is 54- ; Assuming 1 and 2, the photo die A of the image sensor array (PA) is always
In the same figure (
Δ) is when Ji<Td, the same figure (B) is T1-T (+
If we compare Fig. 11 (B) with Fig. 10 (B), it is clear that the number of focus detection operations (-J) within a certain period of time is greater in the case of Example 1-1. It turns out that it will happen.

Although the present invention has been described with reference to one embodiment, the present invention is not limited to the above embodiment.

For example, in self-scanning image sensors and
Just D (, B B D (Bucket 3 r
igade[)evice), CI D(cha
rge InjectionDevice), MO
S (lvletal Oxide S emicond
For example, an image sensor of the type uctor) can be used. Furthermore, the focus detection type is not limited to the one using the focus detection optical system shown in FIG.
92! As shown in 'i9@ publication, Japanese Patent Application Laid-Open No. 57-70504, Japanese Patent Application Publication No. 57-455 October, etc., a lenslet is placed on the intended focal plane of a copying lens or a plane conjugate thereto. A method is proposed in which a self-scanning image sensor is placed behind the image sensor to exclude both the amount of defocus and the direction of defocus as the focus adjustment state of the photographic lens, or Japanese Patent Application Laid-Open No. 155308/1983,
JP-A-57-7211 (Publication No. 1, JP-A-57-884)
As shown in Publication No. 18, etc., self-scanning image sensors are arranged on the expected focal plane of the photographing lens or on a plane conjugate thereto, and in front and behind it, respectively, and the focus adjustment state of the photographing lens is The present invention can also be applied to a system in which only the differential direction is detected.

Furthermore, in the above-mentioned length m example (the transfer lock pulse generation circuit (10) generates two transfer lock pulses φ with different phases),
1. In the case of generating φ2, the image sensor
Depending on the configuration of the charge transfer section of the array, three or more 1C1 phases may be used for different transfers [one lock pulse may be generated, and in that case, the charge transfer section is activated at the falling edge of the transfer lock pulse of any one specific phase. It is sufficient to start the transfer of the accumulated charge to the image signal processing circuit, and to cause the transfer lock pulse of a specific phase to rise immediately when the transfer lock pulse generation circuit is reset by the reset pulse. .

As mentioned above in FJI Mei 1), according to the camera focus detection device of the present invention, a reset pulse is generated and transferred in response to a determination that the monitor circuit output has decreased to a predetermined level, and the lock pulse generation means is reset. At the same time, since the shift 1~ pulse is generated in response to the reset pulse, there is no delay between when it is determined that the monitor circuit output has dropped to a predetermined level and when the shift pulse is generated, unlike in the conventional system. Even when the subject is bright, the problem of saturation of accumulated charges in the charge accumulating section of the self-scanning image sensor array is eliminated, and the focus adjustment state of the photographic lens can be detected correctly based on reliable image signals. can.

[Brief explanation of drawings]

57- Fig. 1 is an overall circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram showing details of the photoelectric exchange block <1) in Fig. 1, and Fig. 3 is a diagram showing the configuration of each pixel of the image sensor to array. Zurufi i1-
An equivalent circuit diagram of a diode and an integral clear gate, FIG. 4 is a diagram showing the focus detection optical system in the above embodiment, FIG. 5 is a diagram showing temporal changes in the output of the monitor circuit, and FIG. 6 is a diagram similar to FIG. A circuit diagram showing a specific example of the luminance judgment circuit (40) and block (20), FIG. 7 and FIG. 8 are diagrams showing the 81 force waveforms in each part of the circuit of FIG. 10 (A>(8) is a time chart showing how the focus detection operation is repeated in the above embodiment, and FIG. 11 is a flowchart showing the operation of the micro combi coater in the example. Timer 1 shows how the focus detection operation is repeated when each photodiode that makes up the image sensor array of the sensor starts to accumulate charge. (PA) (ICG) (SG) (SR)...Self-running 58
- Scan type image sensor-1 (PΔ)...image sensor array (N load storage unit), (SR)...shift 1 register (transfer unit), <VS>...image signal output circuit, (
MC)...Monitor circuit, (MP)...Monitor light receiving means, (R8)...M1'l! Signal generation circuit, (
DFI)...Reset 1-pulse generating means, (30).
... Microcomputer (integral clear pulse generation means), (40) (AC4) ... Judgment means, (DF2)
. . . shift 1 to pulse generation means, (10) . . . transfer lock pulse generation means. Applicant: Minolta Camera Co., Ltd. 59--1 To 1 (cQ To 5 \-1) Procedural Amendment Commissioner Wakasugi Wainu, Commissioner of the Patent Office 1, Indication of the case 1982 Patent Application No. 230372 2, Title of the invention Self Relationship between camera focus detection device 3 using a scanning image sensor and the correction case Applicant Address Osaka Kokusai Building 4, 2-30 Azuchi-cho, Higashi-ku, Osaka
, Date of amendment order Voluntary amendment 5, Subject of amendment 7 ＼＼ 6. Contents of amendment (1) ``Figure 7'' on page 15, line 16 of the specification 1 5
Corrected to ``Figure''. (2) On page 22, line 3, ``After that, between 1 and ``on,'' ``or in synchronization with the shift pulse if it occurs before the predetermined time elapses.'' insert. (3) Last line of page 29, [After 1, [,
Or, if a shift pulse is generated before the predetermined period of time has elapsed, then in response to the generation of the shift pulse] is inserted. (4) Page 30, line 9, i(T 18)J is r(T
19) Make it J. Applicant: Minolta Camera Co., Ltd.

Claims (1)

[Claims] 1. Charge storage that makes up the image lens array! An image signal is obtained by the image signal output circuit based on the accumulated charge transferred from the self-scanning image sensor located on the right side of the i section and the transfer section for transferring the accumulated charge, and the image signal is sent to the 5F! In a camera focus detection device that detects the focus adjustment state of a prefecture lens by performing a mathematical calculation, the object Ili! an integral clear pulse generating means that generates an integral clear pulse that wipes out the accumulated charge in the charge accumulating section; A reference signal generation circuit that generates as output a reference signal with which the output of the monitor circuit is compared, such as a monitor circuit that reduces the output at a speed corresponding to the subject brightness detected by the light receiving means at the same time as the clear pulse disappears; means for determining that the output of the monitor circuit has decreased by a predetermined level with respect to the output of the reference signal generating circuit;
a shift pulse generating means for generating a shift pulse at a predetermined period for transferring the accumulated charge of the charge accumulation section after the integral clear pulse is exhausted to the transfer section; and accumulation from the transfer section to the image signal output circuit. Transfer pulse generation means for outputting a transfer pulse for transferring charge; and reset pulse generation means for resetting the transfer pulse generation means in response to a determination by the determination means of a decrease in the predetermined level of the output of the monitor circuit. A focus detection device for a camera, characterized in that the shift pulse generating means is connected to the reset pulse generating means to generate the shift pulse in response to the reset pulse.