JPS6011863B2 - signal detection circuit - Google Patents

Description

[Detailed Description of the Invention] In a signal transmission system where signal confusion occurs intermittently, data signals are transmitted repeatedly many times, and as a result, the receiving side receives diversity in the time axis direction. This reduces the error rate.

The present invention relates to this type of time diversity. Conventionally, a method of diversity reception when data signals are transmitted multiple times uses a method of taking a majority vote among received signals that represent the same information.

However, with this conventional method, if the number of repeated transmissions of the data signal is an even number, majority voting may not be possible, and even if the number of transmissions is an odd number, the level has already been determined to be high or low. In addition, since a majority vote is taken for data signals having a low received carrier level, the detection accuracy deteriorates when the data signal is finally detected by diversity. Since the present invention adds and compares signals representing the same information among received data signals in an analog manner, the detection accuracy is high, the yield rate is greatly reduced compared to the conventional method, and the number of times data signals are sent is reduced to 2. This makes it possible to accurately detect information signals even in the case of multiple times.

A detailed explanation will be given below with reference to the drawings.

FIG. 1 shows a specific example of a conventional data signal detection circuit.

Circuit 1 is a low-pass filter that removes noise from the demodulated signal. The output X of the filter 1 is compared in a voltage comparison circuit 3 and extracted in a circuit 4. Circuit 2 is a clock pulse regeneration circuit for regenerating clock pulse X2 from received demodulated signal Xo. Circuit 5 is a shift register for delaying the data signal extracted by circuit 4. In the specific example shown in FIG. 1, n pieces of information a,, a2, . . . , an are sent three times and are resolved. The circuit 6 is a circuit for taking a majority vote regarding the same delayed information signals.
In the case of FIG. 1, the first stage and the n11th stage of the shift register 5
This is a case where a majority vote is taken for the signal a representing the same information in the 2nth and 11th rows. Circuit 7 is a preliminary signal detection circuit for detecting a preliminary signal sent at the beginning of the data signal. When this output 8
is output through. In this conventional method, even if an error occurs in the first received information due to bad CN, for example, as long as an error does not occur in the second and third received information sent later, It is possible to normally detect data signals due to the majority voting effect.

However, if the C/N of both the first and second received information is poor, there is a strong possibility that both the first and second received information are incorrect.
Even if the C/N of the third received information is sufficiently good, confusion is likely to occur in the received information after the majority decision. FIG. 2 shows a first specific example of the data signal detection circuit of the present invention.

The demodulated signals X and o are input to an analog delay circuit 16 through an analog gate circuit 12. X2, is the delay circuit 16
The delay circuit 16 is a high-speed clock pulse for operating the CCD (Charge Coup), for example.
lingvice) or BBD(bagketBr)
igadeDevice) etc. are used. A circuit 11 is a circuit for detecting a carrier level, and rectifies and smoothes the received intermediate frequency using capacitors C, C2 and a resistor R, and removes high frequency components using circuits R2 and C3.
That is, when the carrier level of the signals X and 2 input to the delay circuit 16 is low, the analog gate circuit 12 reduces the amplitude. Amplitude suppression signals X, .
As a result, the noise of the demodulated output of the receiver may be used. In this case, when the noise level is low, X, . becomes high so that the amplitude of X,2 is not suppressed. It is known that in an FM receiver, as the carrier level increases, the noise in the demodulated output is suppressed and becomes smaller. In FIG. 2, information signals [a,,...... an] is sent three times each, then ana. The delay circuit 16 is arranged in two stages, and the first stage and nth stage are arranged so that the same information signals are output in the same phase.
Output is taken from the +1st and 11th stage terminals.
This circuit 16 includes a one-stage analog delay circuit and two n-stage analog delay circuits.
It is also possible to connect the stages of delay circuits in series and extract the same information from the output of each delay circuit. In this way, the circuit 17 adds and integrates the same signals extracted at the same phase (the figure shows the case where a is output). The circuit 14 is a circuit for regenerating the clock pulse, and the circuit 14 is a circuit that generates a reset pulse according to the rising or falling edge of the clock pulse.In other words, the integrated result in the circuit 17 is compared in the circuit 18, and the result is compared in the circuit 19. The information signal is extracted and detected. Immediately after the data is extracted in the circuit 19, the integrated value of the circuit 17 is reset to 0 level by a reset pulse output from the circuit turtle 4. This is a circuit that detects the preliminary signal sent to circuit 1.
When the preliminary signal is detected at 5 and the gate circuit 20 is opened, the detected data signal is sent to the signal processing side through the gate 20. In the case of FIG. 2 described above, received demodulated signals representing the same information are added and integrated at an analog level.

For example, assume that the high level of the demodulated signal is 11 (V) and the low level is -1 (V). Of the information signals sent three times, the C/N is bad for the first and second times, so delay circuit 1
If the output of circuit 6 is around the level of 0 (V), if the C/N of the signal sent for the third time is sufficiently good, the output of circuit 1
Since the signal detection is performed using the third information when the C/N is sufficiently good for the integration result of No. 7, the data signal can be detected without error.

In FIG. 2, weighting is performed by the circuit 12 so as to suppress low carrier levels.

When the carrier level is low and the levels of the demodulated signals X and o are also low, this circuit 12 is not necessary. FIG. 3 shows a second specific example of the present invention. The input signal X3o is a received demodulated signal or a demodulated signal whose amplitude is limited when the carrier level is low (for example, the output of the circuit 12 in FIG. 2 of the first embodiment of the present invention). Signal X3o is the delay circuit 31
delayed by X3o is a high-speed clock pulse for operating the delay circuit 31. In the case of Figure 3,
The same information signal, for example, waveform a, is stored in m delay elements from each output of the delay circuit, and the outputs of these delay elements are connected to resistors, . , R skin..., R skin R2.,
R22, ..., R2 skin RM, R fence ..., R3m are weighted and output. Each output is connected to circuit 38
The summed results are compared by a circuit 35, and data is extracted by a circuit 36. Circuit 32 is a clock pulse regeneration circuit. Circuit 33 is a preliminary signal detection circuit similar to circuit 15 in FIG. In the case of Fig. 3, for example, in the case of a received signal with a high level of 11 (V) and a low level of -1 (V), due to poor C/N, the first signal a
, and the second signal a, both reach the level of 0 (V), if there are not enough carriers to carry the third signal a, the adder circuit 38 sends the signal to the third signal a. Since the signal a, is outputted, the data signal can be detected without error. FIG. 4 shows a third specific example of the present invention.

The input signal Fo is the input signal X4o of the second specific example of the present invention in FIG. 3, and the input signal X4o of the second specific example of the present invention in FIG. 3 is the input signal X3 of the second specific example of the present invention in FIG.
This is a received demodulated signal, or a demodulated signal whose amplitude is limited when the carrier level is low. Signal X4o is delayed by analog delay circuit 41. X3o is a high speed clock pulse for operating the delay circuit 41. In the case of FIG. 4, as in the case of FIG. 2, the outputs of the analog delay circuits are output for signals representing the same information, and are added by the circuit 49. A filter 45 removes noise components from the addition results, a circuit 46 compares the results, and a circuit 47 extracts a data signal. Circuit 42 is a clock pulse regeneration circuit. Circuit 43 is a preliminary signal detection circuit similar to circuit 15 in FIG. In the case of Fig. 4, as in the case of Figs. 2 and 3, if the information signal is received three times, C
If /N is good, data signals can be received without error. In the above description, a similar detection method can be used when information signals are sent in a multiplexed manner as shown in FIG. 5. In the case of FIG. 5, among the signals entering the delay circuit, the first stage and
It is preferable to detect the data signal by adding up the 8th stage and the 1st stage. FIGS. 6 and 7 show a fourth specific example of the present invention.

FIG. 6 shows the transmitting side, where the same information signal Xo is delayed by delay circuits 61 and 62, and input X5 to the delay circuit 61.
and the respective outputs &,, 2 have different carrier frequencies ^. For Na2 and Na3, each amplitude modulator 63
, 64 and 65, and synthesized by a circuit 66.
The respective combined results are further combined with the carrier frequency “c
A circuit 67 performs frequency modulation for the signal. FIG. 7 shows a demodulation method when transmitting as shown in FIG. 6. In FIG. 7, a circuit 71 is a frequency discrimination circuit, to which the intermediate frequency of a frequency-modulated wave is input.
The circuit 71 calculates the sum of the amplitude-modulated waves,
10 na 2 10 3 are output. The circuit 85 has an intermediate frequency X7 similar to the circuit 11 in FIG. This circuit is for measuring the carrier level, and based on this result, when the carrier level of the output of the circuit 71 is low, the amplitude is suppressed. Circuit 86 is a suppression circuit for this purpose. circuit 86
The waves that have passed through are sent to the corresponding demodulators 72, 73,
The signal is demodulated by 74 and returned to a baseband signal, and the phases are matched by delay circuits 75 and 76. That is, each signal X75, X74 on the X side is the 6th
The red in the reproduced signal of signal The probability of that happening is very small. These baseband signals X75
, X? 6, X74 are added in a circuit 77, passed through a filter in a circuit 79, compared in a circuit 80, passed through a gate circuit 83, and extracted as data in a circuit 84. Circuits 81 and 82 are respectively exactly the same clock pulse regeneration circuit and preliminary signal detection circuit as circuits 42 and 43 in FIG. In this case, as in the case of FIGS. 2, 3, and 4, the signal sent three times, that is, the demodulated output
75. If either one of X76 and X74 is sent with a good C/N, it is possible to detect the information signal almost without compromise. In FIG. 7, if there is a filter on the output side of each demodulator, and if noise is removed from the respective inputs X74, X76, and X75 of the adder circuit 77, the filter 79 is not necessary.

Furthermore, if the same information is transmitted very many times, the carrier level measuring circuit 85 and the circuit 86 for suppressing the amplitude of the circuit 71 are not necessarily necessary.

This is because, in this case, when adding by turning wax 77,
This is because the added value for signals sent with poor C/N is concentrated at the average level (for example, the W level in the case of a Sat IV signal). As explained above, for example, if information signals were sent M times, in the conventional method, there was a possibility that the C/N was not good for more than M/2 pieces of information. In contrast, in the present invention, if any one of the M signals has a good C/N, the data signal detection result of the received information will hardly be erroneous.

Further, in the conventional majority voting method, it is impossible to obtain a majority vote when the number of times the information signal is sent is two, but with the present invention, it is possible to detect the data signal even in this case.

[Brief explanation of drawings]

FIG. 1 is a specific example of a conventional signal detection circuit, FIG. 2 is a first specific example of the signal detection circuit of the present invention, FIG. 3 is a second specific example of the signal detection circuit of the present invention, and FIG. is a third specific example of the signal detection circuit of the present invention, FIG. 5 is a specific example of an information signal that can be detected by the signal detection circuit of the present invention, and FIG. 6 is a fourth specific example of the signal detection circuit of the present invention. FIG. 7 shows a fourth specific example of the signal detection circuit of the present invention. 11, 85...Carrier detection circuit, 12, 86
...Analog gate circuit, 13, 32, 42,
82...Clock pulse regeneration circuit, 14...
・Reset pulse generation circuit, 15, 33, 43...
・Preliminary signal detection circuit, 16, 31, 41, 61, 62
, 75, 76...delay circuit, 17...addition and integration circuit, 18, 35, 46, 80...voltage comparison circuit, 19, 36, 47, 84...data extraction circuit,
20, 83...AND circuit, 38, 77...
・Additional times, 45,79...Fill evening, 63-65...
Amplitude modulator, 66...Synthesizing circuit, 67...
... Frequency modulator, 71 ... Frequency discrimination circuit,
T2-74...Demodulator. Next 'Mimi world - 2 9 Een J map Figure 4 Hunting box many map Cloth figure 7

Claims (1)

[Scope of Claims] 1. In a receiver used in a communication system that repeatedly transmits the same information signal many times, each of the same information signals transmitted repeatedly is received and these received signals have the same phase. 1. A signal detection circuit comprising means for extracting signals from different locations, and detecting an information signal by adding the extracted signals having the same phase. 2. In the receiver, the means for setting the received signals of the information signals repeatedly transmitted to be in the same phase includes a plurality of analog delay circuits connected in series, and a first one of the analog delay circuits. Claim 1, characterized in that it is means for inputting a demodulated signal of the information signal to the second stage and extracting the sent information signal from the input of the analog delay circuit or the output of each of the analog delay circuits. signal detection circuit. 3. The means for detecting an information signal by adding the extracted signals in the same phase, the means for integrating the addition result;
2. The signal detection circuit according to claim 1, further comprising means for comparing the output of said integrating means with a certain level. 4. In a receiver used in a communication system that repeatedly transmits the same information signal many times, a first receiver that receives the same information signal that has been repeatedly transmitted and extracts it from the point where these received signals have the same phase. a second means for detecting an information signal by adding the signals extracted in the same phase; a third means for detecting a carrier level from the received information signal; and a third means for detecting a carrier level from the received information signal. and fourth means for changing the amplitude of the received information signal by the output of the signal detection circuit. 5. Claim 4, characterized in that, as the third means, a means for rectifying and smoothing the intermediate frequency level of the receiver or a means for measuring the noise level in the demodulated output of the receiver is used. signal detection circuit.