JPH05244137A - Timing extraction method and circuit - Google Patents

Abstract

PURPOSE:To attain the integration by using a digital circuit to construct a timing extracting circuit which receives a burst signal and then demodulates it. CONSTITUTION:This circuit is constituted of a timing generating circuit 22 for outputting the timing signals in the same cycle as the clocks of the received signals, a signal detecting circuit 24 which detects the data signals out of the received signals by the timing signals of the circuit 22, an A/D converter 21 which samples the received signals in the different cycles from the clocks of these received signals and converts these signals into the digital ones, an envelope detection circuit 23 which applies the envelope detection to the received signals digitized by the converter 21 and acquires the envelope signal data, and a CPU 25 serving as a correction circuit which corrects the phase outputted from the circuit 22 based on the phase error produced between the proper signal detection timing information acquired from the envelope signal data given from the circuit 23 and the present signal detection timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing extraction method for extracting a timing for receiving and demodulating a burst signal transmitted by radio communication, and a timing extraction circuit using this method.

[0002]

2. Description of the Related Art For example, as a circuit for extracting a timing for receiving and demodulating a burst signal transmitted by radio communication, a circuit having a structure shown in FIG. 5 has been generally used conventionally. The received signal, which is a burst signal in the figure, is input to the envelope detection unit 11 and the data demodulation unit 12. The envelope detection unit 11 is for obtaining an envelope signal including timing information as a non-linear circuit for the input received signal,
The obtained envelope signal is input to a narrow band filter such as a PLL circuit 13 to extract timing information, and the data demodulation unit
Supplied to 12. Therefore, the data demodulation unit 12 uses the PLL
The data signal is demodulated from the received signal based on the timing information supplied from the circuit 13.

[0003]

However, according to the circuit configuration as described above, the envelope detection section 11 and the PLL circuit are provided.
Since all 13 are composed of analog circuits, there is a problem that integration is difficult.

The present invention has been made in view of the above situation, and an object of the present invention is to use a timing extraction method which can be constituted by a digital circuit in which circuits can be integrated and this method. It is to provide a timing extraction circuit.

[0005]

That is, according to the present invention, the wireless transmission rate used in a mobile communication system such as a second-generation cordless telephone or a digital car telephone is several tens.
Since the crystal oscillator has a stability of about 10 ⁻⁶ , the fluctuation of the clock frequency error occurring on the transmitting side becomes very slow at 1 Hz or less, and due to the terminal movement. The fluctuation of the generated clock phase is also considered in consideration of the fact that it becomes 0.1 ° / sec or less even when the moving speed is 100 km / sec. Envelope signal data is obtained by sampling at a different cycle from the clock, and the phase of signal detection timing is corrected based on the proper signal detection timing information obtained by analyzing this envelope signal data. Although the detection timing is corrected slowly, the timing is effective for communication systems in which the fluctuation of the clock phase error caused by signal transmission is very slow. It is possible to provide a grayed extraction method, also becomes possible to configure a digital circuit.

The present invention also provides a timing generation circuit for outputting a timing signal at the same cycle as a clock of a baseband received signal, and a signal for detecting a data signal in the received signal by the timing signal output from the timing generation circuit. A detection circuit, an A / D converter for sampling and digitizing the received signal at a cycle different from the clock of the received signal, and an envelope detection of the digitized received signal obtained by the A / D converter. Then, the phase of the timing signal output from the timing generation circuit is corrected based on the envelope detection circuit that obtains the envelope signal data and the proper signal detection timing information obtained from the envelope signal data from the envelope detection circuit. It is equipped with a correction circuit, and it becomes possible to integrate by configuring it with a digital circuit. Improved type of the reliability, it is possible to contribute to reduction of costs.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the principle of timing extraction. FIG. 1A shows a baseband signal as a received signal, and an envelope curve theoretically obtained from this baseband signal is the waveform shown in FIG. 1B. The signal detection timing Td having the same cycle as the clock of the baseband received signal for the envelope of such a waveform is as shown in FIG.

Based on this signal detection timing Td, the minimum sampling unit time Sd (provided that S
d is for setting the sampling timing Te for timing extraction as shown in FIG. 1D at a position deviated by an integer fraction of the period of the signal detection timing Td).
In this case, the sampling timing Te is expressed by the following equation. That is, Te = Td + N * Sd (1) (where N is a number that increases by 1 for each sample (modT
/ Sd). ). A signal sampled at the sampling timing Te for timing extraction obtained in this way is described by superimposing it around the signal detection time, that is, by superimposing signals having the same N in the equation (1). In the figure, the white circles are discrete samples when the comprehensive line was continuously at the high level during the sample period, but in reality, the comprehensive line changes so that the comprehensive line surely includes the comprehensive line. It becomes possible to obtain discrete samples representing a line waveform.

As can be seen from this figure, it is possible to obtain a comprehensive line signal waveform similar to that obtained by sampling with a clock having a frequency higher than the clock of the baseband received signal.

Further, since only the signal detection timing is corrected and the timing extraction sampling timing is not corrected, the envelope data can be continuously obtained. Therefore, the next signal detection timing can also be corrected based on the phase difference between the optimum signal detection timing obtained from the envelope data and the actual signal detection timing, so that the processing can be simplified.

In FIG. 1, the signal detection timing shown in FIG. 1B corresponds to 1: 1 as shown in FIG.
An example has been shown in which the timing extraction sampling timing is obtained at each signal detection timing, but the present invention is not limited to this, and as shown in FIG. 1E, the signal detection timing of FIG. Therefore, the sampling timing for timing extraction may be obtained once every two signal detection timings.

Next, the configuration of the circuit for performing the above-mentioned timing extraction will be described with reference to FIG. This figure shows the configuration of a receiving circuit for a two-phase PSK (phase shift keying) signal. A baseband signal as a received signal is first input to the A / D converter 21. The A / D converter 21 includes a first sampling clock having the same cycle as the clock of the reception signal output from the timing generation circuit 22 and a second sampling clock having a cycle longer than the cycle by the minimum sampling unit time Sd. Based on the above, the received signal is digitized at the timing shown in FIG. 1 (d) and sent to the envelope detection section 23 and the data demodulation section 24.

The envelope detection unit 23 takes in the digitized reception signal which is a discrete value from the A / D converter 21 by the second sampling clock from the timing generation circuit 22, obtains the envelope signal data and the CPU 25. Output to.

The CPU 25, based on the envelope signal data received from the envelope detector 23, has information which is the optimum signal detection timing when the data demodulator 24 demodulates the data, that is, the envelope waveform shown in FIG. In the timing generation circuit, a phase adjustment signal for correcting the phase of the first sampling clock output from the timing generation circuit 22 is obtained based on this time information (the value of N in the above formula (1)) serving as the center. Send to 22.

The timing generation circuit 22 adjusts the phase of the first sampling clock output to the A / D converter 21 and the data demodulation section 24 by the phase adjustment signal from the CPU 25. The output timing of one sampling clock is the center of the envelope.

The data demodulation section 24 is responsive to the first sampling clock from the timing generation circuit 22 for A / D conversion.
A data signal is demodulated from the digitized received signal output from the converter 21.

With such a circuit configuration, A
/ D converter 21, timing generator 22, envelope detector 2
3. Since the data demodulation unit 24 and the CPU 25 can all be configured by digital circuits, the entire circuit can be integrated, which contributes to downsizing of the circuit, improvement of reliability, reduction of cost, and the like.

Although FIG. 3 shows the configuration of the two-phase PSK signal receiving circuit, the four-phase or more-phase PSK signal receiving circuit is as follows. Fig. 4 shows PSK with 4 or more phases as an example.
This shows the configuration of a signal receiving circuit. The received input signal is first distributed by the distributor 31 to two paths. The signal input to the multiplier 32 side is mixed with the frequency signal supplied from the oscillator 34 to become an I component baseband signal, which is input to the A / D converter 35.

The signal input to the multiplier 33 side is 9
It is mixed with the frequency signal supplied from the oscillator 34 through the 0 ° phase shifter 36 to become a Q component baseband signal, and the A / D
Input to the converter 37.

The A / D converters 35 and 37 are respectively longer than the first sampling clock having the same period as the clock of the input signal output from the timing generating circuit 38 and a time which is an integral fraction of the period longer than the first sampling clock. Based on the second sampling clock of the period, the input I component baseband signal,
Envelope detection unit that digitizes the Q component baseband signal
39 and the data demodulation unit 40.

The envelope detection section 39 includes a timing generation circuit 38.
A / D converter by the second sampling clock from
Envelope detection is performed on the digitized I component sampling clock and Q component sampling clock, which are discrete values from 35 and 37, and envelope signal data including timing information is obtained and output to the CPU 41.

The CPU 41 obtains optimum signal detection timing information based on the received envelope signal data, and based on this, outputs a phase adjustment signal for correcting the phase of the first sampling clock output from the timing generation circuit 38 at the timing. It is sent to the generation circuit 38.

The timing generation circuit 38 corrects the phase of the first sampling clock by the phase adjustment signal from the CPU 41, and applies the phase-corrected first sampling clock to the A / D converters 35 and 37 and the data demodulation section 40. Also send.

The data demodulating section 40 operates on the basis of the first sampling clock from the timing generating circuit 38 to perform A / D conversion.
A data signal is demodulated from each of the digitized I component data and Q component data output from the converters 35 and 37.

As described above, even in the receiving circuit for PSK signals of four or more phases, all of them can be configured by digital circuits, so that the entire circuit can be integrated, and the circuit can be miniaturized.
It is possible to contribute to improvement of reliability, reduction of cost, and the like.

[0027]

As described above, according to the present invention, the wireless transmission rate used in the mobile communication system such as the second generation cordless telephone and the digital car telephone is about several tens of kb / sec to several hundreds of kb / sec and the crystal oscillation is performed. Stability of the child is 1
Since it is about 0 ^-6 , the fluctuation of the clock frequency error that occurs on the transmission side becomes 1 Hz or less, which is extremely low,
Further, the fluctuation of the clock phase caused by the movement of the terminal is 0.1 ° even when the movement speed is 100 km / sec.
/ Sec or less, the baseband received signal is sampled at a cycle different from the clock of the baseband received signal to obtain envelope signal data. Since the phase of the signal detection timing is corrected based on the proper signal detection timing information obtained by analyzing, the correction of the signal detection timing is slow, but the fluctuation of the clock phase error caused by the signal transmission is extremely small. It is possible to provide an effective timing extraction method for a low-speed communication system, and it is also possible to configure a digital circuit.

Further, according to the present invention, a timing generation circuit that outputs a timing signal at the same cycle as the clock of the baseband reception signal, and a data signal in the reception signal is detected by the timing signal output from the timing generation circuit. A signal detection circuit, an A / D converter for sampling and digitizing the received signal at a cycle different from the clock of the received signal, and an envelope for the digitized received signal obtained by the A / D converter Envelope detection circuit for detecting and obtaining envelope signal data, and correcting the phase of the timing signal output from the timing generation circuit based on proper signal detection timing information obtained from the envelope signal data from the envelope detection circuit. Since it is provided with a correction circuit that does, it becomes possible to integrate by configuring with a digital circuit, Improvement in miniaturization and reliability of the road, it is possible to contribute to reduction of costs.

[Brief description of drawings]

FIG. 1 is a timing chart showing the principle of timing extraction according to an embodiment of the present invention.

FIG. 2 is a diagram showing what is described by overlapping the signals sampled in FIG. 1 around a signal detection time.

FIG. 3 is a block diagram illustrating a configuration of a two-phase PSK (phase shift keying) signal receiving circuit according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating the configuration of a 4-phase PSK (phase shift keying) signal receiving circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional timing extraction circuit.

[Explanation of symbols]

11, 23, 39 ... Envelope detection unit, 12 ... Data demodulation unit, 13 ... P
LL circuit, 21, 35, 37 ... A / D converter, 22, 38 ... Timing generation circuit, 24 ... Data demodulation section, 25, 41 ... CPU, 31
… Distributor, 32, 33… Balanced demodulator, 34… Oscillator, 36… 90
° Phase shifter, 40 ... Data demodulator.

Claims (2)

[Claims] 1. A baseband received signal is sampled at a cycle different from the clock of the baseband received signal to obtain envelope signal data, and signal detection is performed based on proper signal detection timing information obtained from this envelope signal data. A timing extraction method characterized by correcting the timing phase. 2. A timing generation circuit that outputs a timing signal in the same cycle as a clock of a baseband received signal, and a signal detection circuit that detects a data signal in the received signal by the timing signal output from the timing generation circuit. , An A / D converter for sampling and digitizing the received signal at a cycle different from the clock of the received signal, and envelope detection by envelope detection of the digitized received signal obtained by the A / D converter An envelope detection circuit for obtaining line signal data, and a correction circuit for correcting the phase of a timing signal output from the timing generation circuit based on proper signal detection timing information obtained from the envelope signal data from the envelope detection circuit. A timing extraction circuit comprising: