JPS60117903A - Level shift circuit - Google Patents

Level shift circuit

Info

Publication number
JPS60117903A
JPS60117903A JP58224192A JP22419283A JPS60117903A JP S60117903 A JPS60117903 A JP S60117903A JP 58224192 A JP58224192 A JP 58224192A JP 22419283 A JP22419283 A JP 22419283A JP S60117903 A JPS60117903 A JP S60117903A
Authority
JP
Japan
Prior art keywords
circuit
voltage
level shift
resistance
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58224192A
Other languages
Japanese (ja)
Inventor
Kazuo Yamakido
一夫 山木戸
Katsuhiro Furukawa
且洋 古川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58224192A priority Critical patent/JPS60117903A/en
Publication of JPS60117903A publication Critical patent/JPS60117903A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To constitute easily a level shift circuit which converts the DC bias voltage into an optional level by using a semiconductor IC and adding a small number of resistances of small resistance value and a buffer amplifier. CONSTITUTION:A voltage attenuation circuit 10 consists of a ladder resistance circuit 11 and a buffer amplifier 12. Both the number of stages of ladder resistances and the combinations of resistance values forming said ladder resistances can be set optionally in order to obtain a desired attenuation factor. In this case, no current flows to a resistance 9 and the circuit 11 when the input signal impressed to a terminal 1 has the DC voltage since the circuit 11 is set between a signal output/input terminal 5 and a bias voltage source 8. Therefore the voltage of the terminal 5 is coincident with the source 8. In other words, the DC bias voltage value of the output voltage can be set optionally by the voltage of the source 8.

Description

【発明の詳細な説明】 〔発明の利用分野〕 を所望の値に変換するレベルシフト回路に係り、特に半
導体集積回路化に好適なレベルシフト回路を提供するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a level shift circuit that converts a value into a desired value, and provides a level shift circuit particularly suitable for semiconductor integrated circuit implementation.

〔発明の背景〕[Background of the invention]

信号処理回路の動作レベルと入力信号レベルとの整合を
とるためには信号処理回路の動作レベルを制御すること
が考えられるが、例えば半動体集積回路の如く、信号処
理回路の動作レベルが固定している場合には、入力信号
レベルをレベルシフト回路によって変える必要がある。
In order to match the operating level of the signal processing circuit with the input signal level, it is possible to control the operating level of the signal processing circuit, but for example, in semi-dynamic integrated circuits, the operating level of the signal processing circuit is fixed. In this case, it is necessary to change the input signal level using a level shift circuit.

レベルシフト回路、特にアナログ信号のレベルシフト回
路は種々の回路が知られているが、歪が少なく、半導体
制造波術で作りやすいものとしては第1図に示すような
演算幅器、キャパシタ、抵抗素子で構成されたレベルシ
フト回路が知られている。
Various types of level shift circuits, especially level shift circuits for analog signals, are known, but the ones that have low distortion and are easy to make using semiconductor wave generation technology are the arithmetic amplifiers, capacitors, and resistors shown in Figure 1. Level shift circuits made up of elements are known.

入力端子1およびキャパシタ6を経た入力信号およびバ
イアス電源8からのバイアス電圧はそれぞれ演算増幅器
の逆相及び正相入力端子に加えられる。演算出力の1部
はキャパシタ7を経て、上記逆相入力端子に加えられる
。原理的には以上の構成で、入力信号と逆相でかつ電源
8の電圧に一致したバイアス電圧を有するレベルシフト
した信号が得られるが、実用上は増幅器2の動作を安定
させるために、帰還抵抗9が絶対不可欠である。ところ
がこの場合、抵抗9によってキャパシタ7の電荷が放電
されてしまうので、印加電圧信号として低周波成分を取
扱う場合には、キャパシタ6゜7の容量値及び抵抗9の
抵抗値とを極めて大きくしなければならなくなり、従っ
て、経済化を目的とをする半導体集積回路でレベルシフ
タを実現することができない。
The input signal via the input terminal 1 and the capacitor 6 and the bias voltage from the bias power supply 8 are applied to the negative phase and positive phase input terminals of the operational amplifier, respectively. A part of the calculation output is applied to the negative phase input terminal via the capacitor 7. In principle, with the above configuration, it is possible to obtain a level-shifted signal that is in reverse phase with the input signal and has a bias voltage that matches the voltage of the power supply 8, but in practice, in order to stabilize the operation of the amplifier 2, feedback is required. Resistor 9 is absolutely essential. However, in this case, the charge in the capacitor 7 is discharged by the resistor 9, so when handling low frequency components as an applied voltage signal, the capacitance value of the capacitor 6.7 and the resistance value of the resistor 9 must be extremely large. Therefore, it is impossible to realize a level shifter in a semiconductor integrated circuit that is intended to be economical.

〔発明の目的〕[Purpose of the invention]

したがって、本発明の目的は、半導体集積回路で実現で
きるレベルシフト回路を実現すること、更に具体的に言
えば、第1図のようなレベルシフト回路において、抵抗
9の抵抗値が小さいにもかかわらず、放電に対する抵抗
値が等価的に大きい抵抗値として動作するように回路を
構成することである。
Therefore, an object of the present invention is to realize a level shift circuit that can be realized with a semiconductor integrated circuit, and more specifically, in a level shift circuit as shown in FIG. First, the circuit is configured so that the resistance value against discharge operates as an equivalently large resistance value.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するため、第2図に示す如く、
帰還抵抗9と直列に電圧減衰回路10を付加し、帰還キ
ャパシタ7に並列に接続したものである。この構成によ
り、電圧減衰回路が出力信号振幅の1/に倍(Kは任意
の数)を出力させることにより、等価的な帰還抵抗値は
抵抗9の値のに倍にすることができる。すなわち、第1
図の抵抗9の抵抗値が小さいにもかかわらず、等価的に
大きい抵抗として動作させることができる。
In order to achieve the above object, the present invention has the following features as shown in FIG.
A voltage attenuation circuit 10 is added in series with the feedback resistor 9 and connected in parallel to the feedback capacitor 7. With this configuration, the equivalent feedback resistance value can be doubled as the value of the resistor 9 by causing the voltage attenuation circuit to output 1/2 times the output signal amplitude (K is an arbitrary number). That is, the first
Although the resistance value of the resistor 9 shown in the figure is small, it can be operated as an equivalently large resistor.

〔発明の実施例〕[Embodiments of the invention]

以下、実施例によって、本発明の構成動作を詳細に説明
する。
Hereinafter, the configuration and operation of the present invention will be explained in detail using examples.

第3図は本発明によるレベルシフト回路の一実施例の回
路図を示す。
FIG. 3 shows a circuit diagram of an embodiment of a level shift circuit according to the present invention.

同図において電圧減衰回路10はラダー抵抗同図11と
緩衝増幅器12で構成されており、ラダー抵抗の段数及
びそれを構成する抵抗値の組合せは、所望とする減衰率
が得られるように任意に設定できる。この場合、ラダー
抵抗回路11が信号出力端子5とバイアス電圧源8との
間に設置されているので、端子1に印加される入力信号
が直流電圧のときは、抵抗9及びラダー抵抗回路には電
流が流れず、従がって、端子5の電圧はバイアス電源8
の電圧に一致する。すなわち、換言すれば、出力電圧の
直流バイアス電圧値は8の電圧によって任意に設定でき
る。
In the figure, a voltage attenuation circuit 10 is composed of a ladder resistor 11 and a buffer amplifier 12, and the number of stages of the ladder resistor and the combination of the resistance values composing them are arbitrarily determined so as to obtain a desired attenuation factor. Can be set. In this case, since the ladder resistance circuit 11 is installed between the signal output terminal 5 and the bias voltage source 8, when the input signal applied to the terminal 1 is a DC voltage, the resistance 9 and the ladder resistance circuit are No current flows and therefore the voltage at terminal 5 is biased from bias power supply 8.
Matches the voltage of That is, in other words, the DC bias voltage value of the output voltage can be arbitrarily set using the voltages of 8.

次に、人力信号の交流電圧成分は、キャパシタ6に交流
電流を生じさせるので、その電流が抵抗9及びキャパシ
タに分流し、従がって出力電圧が変化する。
Next, the alternating current voltage component of the human power signal causes an alternating current to be generated in the capacitor 6, so that the current is shunted to the resistor 9 and the capacitor, and the output voltage accordingly changes.

いま、キャパシタ6.7の容量値をそれぞれれた電圧が
そのばま抵抗9に印加されるので、入力交流電圧■iと
出力交流電圧V、との間に、本実施例回路の動作を表わ
す次式が成立する。
Now, since voltages corresponding to the capacitance values of the capacitors 6 and 7 are applied to the bulk resistor 9, there is a voltage between the input AC voltage i and the output AC voltage V, which represents the operation of the circuit of this embodiment. The following formula holds true.

すなわち ただし、Sはラプラス変数である。i.e. However, S is a Laplace variable.

したがって、−例として、カットオフ周波数をIH2,
すなわち、IH2以上の周波数成分は出力させるような
抵抗値の条件をめると − 2πC2K が成立するから、ここでc2=109F’、に=10’
を選べば、Rは約16にΩとなる。この場合のに−10
’は、例えばIOKΩと0. I KΩの抵抗を第3図
の如く3段ラダー状に用いて実現できる。
Therefore, - for example, if the cutoff frequency is set to IH2,
In other words, if we set the resistance value condition such that frequency components higher than IH2 are output, -2πC2K holds true, so here c2=109F', and =10'
If you choose , R will be approximately 16Ω. In this case -10
' is, for example, IOKΩ and 0. This can be realized by using resistors of I KΩ in a three-stage ladder configuration as shown in FIG.

本実施例に対し、第1図の従来例ではに=1に相当する
ため、上記条件を満すための抵抗は約16GΩとなり、
半導体集積化には全く適しないことが分る。
In contrast to this embodiment, in the conventional example shown in FIG.
It turns out that it is completely unsuitable for semiconductor integration.

〔発明の効果〕〔Effect of the invention〕

以上、説明した如く、本発明によれば、少数かつ小抵抗
値の抵抗と一つの緩衝増幅器を追加するのみで、直流バ
イアス電圧を任意の値に変換するレベルシフト回路が半
導体集積回路で容易かつ経済的に実現できる。
As explained above, according to the present invention, a level shift circuit that converts a DC bias voltage to an arbitrary value can be easily and easily created using a semiconductor integrated circuit by simply adding a small number of resistors with small resistance values and one buffer amplifier. It is economically feasible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の回路図、第2図は本発明の原埋的回路
図、第3図は本発明の一実施例の回路図である。
FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is an original circuit diagram of the present invention, and FIG. 3 is a circuit diagram of an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 演算増幅期の正相入力端に直流バイアス電位が与えられ
、同増幅器の逆相入力端と信号入力端との間に第1のキ
ャパシタ、同増幅器の逆相入力端と出力端との間に第2
のキャパシタが接続された増幅回路において、上記演算
増幅器の出力信号振幅の分割電圧を発生させる減衰回路
と、これに直列接続された抵抗とが、上記第2のキャパ
シタと並列接続された構成を特徴とするレベルシフト回
路。
A DC bias potential is applied to the positive phase input terminal of the operational amplification stage, a first capacitor is connected between the negative phase input terminal and the signal input terminal of the amplifier, and a first capacitor is connected between the negative phase input terminal and the output terminal of the amplifier. Second
In the amplifier circuit connected to the capacitor, an attenuation circuit that generates a divided voltage of the output signal amplitude of the operational amplifier and a resistor connected in series with the attenuation circuit are connected in parallel to the second capacitor. level shift circuit.
JP58224192A 1983-11-30 1983-11-30 Level shift circuit Pending JPS60117903A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58224192A JPS60117903A (en) 1983-11-30 1983-11-30 Level shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58224192A JPS60117903A (en) 1983-11-30 1983-11-30 Level shift circuit

Publications (1)

Publication Number Publication Date
JPS60117903A true JPS60117903A (en) 1985-06-25

Family

ID=16809958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58224192A Pending JPS60117903A (en) 1983-11-30 1983-11-30 Level shift circuit

Country Status (1)

Country Link
JP (1) JPS60117903A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696877B2 (en) 2001-05-15 2004-02-24 Yamaha Corporation Level shift circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696877B2 (en) 2001-05-15 2004-02-24 Yamaha Corporation Level shift circuit

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