JPS60117783A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To make it possible to rewrite electrically and selectively and to improve reliability, by setting the magnitudes of capacity couplings, so that 0.8 <=C2/C1<=1.2 is satisfied, when the coupling capacities between the first and second control gates and a floating gate are C1 and C2, respectively. CONSTITUTION:When the coupling capacities between the first and second control gates and a floating gate are C1 and C2, the value of C2/C1 is set so that the facing area of the first control gate CG1 and the floating gate FG is made to be constant 30mum<2> and the facing area of the second control gate CG2 and the floating gate FG is changed. It is a matter of course that the coupling capacity between the side wall part of the floating gate and each control gate should be considered, when the side of each control gate of an element is determined in order to set the value of C2/C1. When the element is miniaturized, the rate of the coupling capacity between the side wall part of the floating gate and each control gate in the capacities of C1 and C2 becomes large. Therefore, it is possible to form C1 and C2 only by the coupling capacity between the side wall part and each control gate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a non-volatile semiconductor memory device which has a floating memory and can be electrically rewritten using two control memory 1 parts and a rewritable light bulb.

[Technical background of the invention and its problems]

2. Description of the Related Art Hitherto, a memory cell of a non-volatile semiconductor memory which is electrically rewritable is known as a memory cell of a non-volatile semiconductor memory.

P-type S1 substrate II = high concentration N layers 3 and 4 which become sources and drains are formed, and floating dirt 6 is formed thereon via a dirt insulating film. 2 is a field insulating film.

On top of the floating c-t s, a first sum IJ control dart 6 and a second control f-) 7 which are capacitively coupled with the floating f-) 5 via a dirt insulating film are laminated. A high-concentration N layer that serves as a rewriting electrode is formed continuously with the eight layers 3 that serve as the source, and the floating gate 5 faces the eight layers 8 through a dirt insulating film that is thin enough to cause a tunnel effect. ing.

The operation of this memory cell is as follows. Book N118.
That is, the N layer 3, which is the source, is set to the ground potential. As a result, electrons float from the 8th layer 8 due to the tunnel effect.
is injected into. Erasing is performed by the first and second control gates 6.
7 is set to the ground potential, and a high potential is applied to the 8 layer 8 to cause the electrons in the floating gate 5 to be released to the N layer B.

Further, reading is performed by applying appropriate potentials to the first control dart 6 and the drain 4, and determining whether or not a current flows through the channel depending on whether or not electrons are injected into the floating gate.

The operation of this memory cell can be explained as follows. A drain voltage VD is applied to the memory cell from the outside.

Source voltage Vs, substrate voltage Vsub, first control dart voltage V a o 0. Second control gate voltage woo
.

is applied. Also, this memory cell is isometrically shown in Figure 2 (
, ), and the electrical equivalent circuit is shown as shown in (b) of the same figure, so the potential of the floating dart V'
lPG is expressed by the following formula.

Here, C, C2 are coupling capacitances between the first and second control darts CG1, CG, and the floating dart FG, respectively. Further, Cg and C5ub are coupling capacitances between the source S, the substrate and the floating gate FG, respectively. From equation (1), when the substrate potential Vsub and the source potential Vs are fixed, the following three states can be created for the potential level of the floating dirt FG using the control dirt CG described in 1 and the second control dirt CG. I can use it. That is, (1) the first control dart CG, and the second control dart C
When G2 are both at high potential, (11) j-th control gate CO, and second control gate C
When one of G is at a high potential and the other is at a low potential, the first control dart CG and the second control dart CG,
When both are low potentials, then . Therefore, by selecting the oxide film thickness of the thin oxide film region on the N layer 8 in FIG. It becomes possible to selectively write and erase. In reality, the memory cells shown in FIG. 1 are arranged in a matrix on a board. For example, as shown in FIG. 3, consider a 4-bit memory cell matrix in which the memory cells are arranged in 14 rows from M. The source S is common to all. The first control gates CGII, CGI are commonly connected in the row direction, and the second control gates CG21 . The CGs 22 are commonly connected in different directions.

Assuming that there is no charge accumulated in the floating gate of each memory cell in the initial state, for example, when data is injected into memory cell M (electrons are injected into the floating gate), the source S is set to 0. ■.

In addition, the first and second control groups F CGII + CGII
+2 (IV) is applied to M, and the control dart of the remaining part is set to 0. In this way, the floating dirt of M is at a high potential, and the electrons are transferred to the floating dirt by the tunnel current through the thin oxide film. is injected into the bud-like pl (this is defined as '0').Memory cells M, , Ms ,
To write to M4 at the same time, each 1ltll
ll141 dart CG,.

+20v may also be applied to CG and 2. Next, eight,
~ With 0'' written in all cells of M4, M
Consider the case where only the contents of l are deleted. In this case,
+20V to source S, 1st S 2nd control dart CG, 1
．． Apply 0■ to CG2I and set the remaining control point to +2.
When kept at 0V, the floating dart only at M has a low potential, and electrons are emitted to the source by a tunnel current, resulting in an erased state (this is assumed to be 61'').

However, in this case, if the values of CI+C2 of each memory cell are unbalanced, for example, C0zO, 5C, as the erasure of only memory cells 1-8 is repeated, the half-selected state The storage contents of the memory cell M out of the cells Mm1Ms change greatly by M, and eventually it becomes impossible to determine whether it is in a written state or an erased state. FIG. 4 shows this situation. At first, M, , M2, M3, and M4 were all in the write state of "0", but while erasing M, it becomes difficult to determine whether they are "0" or "1" after repeating the process, for example, about 100 times. Here, we are considering a 4-bit cell, but if we consider an actual memory cell matrix, only one of the control darts will be selected to have a high potential or a low potential. There are consecutive half-selected cases without any burn marks.In this case, C
If 1 and 02 are unbalanced, variations will occur in the changes in the storage contents of the memory cells, causing a very serious problem in terms of reliability in that the storage contents of a certain memory cell will change significantly.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a highly reliable nonvolatile semiconductor memory that is electrically and selectively rewritable.

[Summary of the invention]

The present invention provides a rewritable non-volatile semiconductor memory having floating darts and having first and second control gates and rewriting electrodes capacitively coupled with the floating darts, as described above. When the coupling capacitance between the control dart and the floating dart is ClIC2, 0.8≦”t/C+≦1
．． It is characterized in that the magnitude of capacitive coupling is set so that it becomes 2.

〔Effect of the invention〕

In the present invention, by setting the coupling capacitance between the two control darts and the floating darts of each cell as described above, a highly reliable nonvolatile semiconductor memory device can be provided. That is, C1, C! By setting as described above, there will be no variation between each element in the deterioration of memory contents in a half-selected state, and the limit value of the number of rewrites that was determined by the most deteriorated element will be significantly improved, which will cause no practical problems. It is possible to provide a non-volatile storage device without

[Embodiments of the invention]

The present invention will be explained in detail below. Note 1: The configuration of the cell and the configuration of the cell array are basically the same as those explained in Figs.
The second flt control diagram and FIG. 5 show the selection characteristics of two 4-bit memory cells in the nonvolatile memory according to this embodiment. This first consists of four cells M
8. Write M 2 , M B , M4 to state ″'0
”; 2nd, then the same as in Figure 4; 2nd, M,
As shown in Figure 5, the memory contents of half-selected memory cells M, , and M3 change all at the same time. However, even if it is repeated for about 10 seconds, the memory content remains ``0''.
no change occurs. In this way, the values of C1 and C8 are tl
It is important in a type of memory cell (2) that uses two control darts to perform selective programming and erasing. After writing ('0'') to the memory cell of M so that the threshold voltage becomes approximately 5V.

When only - is deleted (1”), half-selected state: 2 M
, , M, the threshold difference 1Δvtl after 103 half-selections is plotted using Ct/Cl as a meter. The value of Ct/C0 is the first
Control 'r') CG+ floating goo) Opposing area with FG is 30 μm! It was set by changing the opposing area of the second control goo (CG) and the floating goo (FG). The oxide film thickness is constant at 1000X. As is clear from the figure, even after repeating half-selection 10" times, C,/
Set C, in the range of 0.8 to 1.2 (2yoj)
The variation in ,M,,M, is reduced, and the margin for the half-selection frequency is improved to a practically sufficient size.

When determining the dimensions of each control dart of the element in order to set the value of Ct/C1, as is clear from Fig. 1(C), the distance between the side wall of the floating dart and each control case is It goes without saying that the coupling capacity must also be taken into account. As the device becomes finer, the side wall of the floating dart and each control r-1
The coupling capacitance between C and C2 occupies a large proportion of the capacitance at C2. From this, it is also possible to form C, , C2 only by the coupling capacitance between the side wall portion and each control dart.

As described above, according to the present invention, it is possible to realize a nonvolatile semiconductor memory in which the memory contents can be electrically and selectively rewritten, and the reliability of the element characteristics during selective rewriting is significantly improved. I was able to do that.

[Brief explanation of the drawing]

Figures 1 (a) to (c) are diagrams showing the configuration of an example of a nonvolatile semiconductor memory cell, Figure 2 (-) is its Schindel diagram, Figure 3 (b) is an equivalent circuit diagram, and Figure 3 is A diagram showing the configuration of a 4-bit memory cell array. FIG. 4 is a diagram showing characteristic changes due to half selection in a conventional cell. FIGS. 5 and 6 are diagrams showing characteristics due to half selection in a cell according to an embodiment of the present invention. It is a figure showing a change. 1... S+ substrate, 3, 4... Highly doped N layer (source, drain), 8... Highly doped N layer (rewriting electrode), 5...
...Floating dart, 6... Between the first control darts 7...
``Second Control Dirt. Applicant's Representative Patent Attorney Takehiko Suzue Figure 4 Night 5 Figure + 'Nectarium Circulation Figure 6 Combined Capacity Ratio 0/.

Claims (1)

[Claims] A semiconductor substrate has a floating dirt electrically insulated therein, and a first dirt that is capacitively coupled to the floating dirt. a second control dart;
Memory cells each having a rewrite electrode that transfers charge to and from the floating ff-) by a tunnel effect are arranged in a matrix, and the first and second controls r-1 are common in mutually orthogonal directions. At the same time, the rewriting electrodes are connected in common, and writing is performed by applying a high potential to the first and second control darts of the selected cell, a low potential to the control darts of the remaining cells, and a low potential to the rewriting electrode. , a low potential to the first and second control points of the selected cell, a high potential to the remaining control points,
In a nonvolatile semiconductor memory device in which erasing is performed by applying a high potential to a rewrite electrode, the coupling capacitance between the first and second control dirts and the floating dirt is expressed as C1.
-tC! When closed, 0.8≦ctl Ct≦1.2
What is claimed is: 1. A nonvolatile semiconductor memory device characterized in that it is configured to satisfy the following conditions.