JPS5827370A - Non-volatile semiconductor memory - Google Patents
Non-volatile semiconductor memoryInfo
- Publication number
- JPS5827370A JPS5827370A JP56124725A JP12472581A JPS5827370A JP S5827370 A JPS5827370 A JP S5827370A JP 56124725 A JP56124725 A JP 56124725A JP 12472581 A JP12472581 A JP 12472581A JP S5827370 A JPS5827370 A JP S5827370A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- floating gate
- electrodes
- potential
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015654 memory Effects 0.000 claims abstract description 27
- 239000007769 metal material Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 241000894006 Bacteria Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000003967 crop rotation Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は，浮遊ゲートを有する不揮発性半導体メモリに
係抄、特に電気的に選択的に消去可能な不揮発性半導体
メモリに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory having a floating gate, and more particularly to an electrically selectively erasable nonvolatile semiconductor memory.
従来、浮遊ゲートを有する半導体不揮発性配憶素子は電
気的に外部と絶縁された浮遊ゲートと、その上部に制御
ゲートを有するｌＳ型電界効果トランジスタによって形
成されてお抄、複数の記憶容量を有する配憶装置は、記
憶素子を２次元的に配置し、各行に共通して制御ゲート
（ワードｔＳ＞が、各列に共通してドレイン配線（ビッ
ト線）カ設けられ、書き込みは、各々の行と列を選択し
その交点に存在する記憶素子のみが選択的に書き込み状
態に変化する。Conventionally, a semiconductor non-volatile storage element with a floating gate is formed by an IS type field effect transistor having a floating gate electrically insulated from the outside and a control gate above the floating gate, and has a plurality of storage capacities. The storage device has memory elements arranged two-dimensionally, a control gate (word tS>) common to each row, and a drain wiring (bit line) common to each column. and columns are selected, and only the memory elements present at the intersections are selectively changed to the write state.
第１図は、従来用匹られている浮遊ゲートを有する不揮
発性記憶素子の構造を示している。第１図ｆａ）は素子
の平面ｉＭ、（ｂ）はＡ−Ａ’断画、（Ｃ）はＢ−Ｂ′
断面を示している。ｆＦ本的には絶縁された浮遊ゲート
（１）及び制御ゲート（２）をもつＭＯ８Ｉｌ電界効果
トランジスターである。その書き込みは制御ゲート（２
）とドレイン（３）に高電圧を印加しドレイン近傍で発
生したホットエレクトロンを浮遊ゲート（４）に注入す
る事によって行なわれる。また、読み出しけ制御ゲート
（２）と、ドレイン（３）に適当な電位を印加し電荷の
注入の有無によってチャネルに電流が流れるか否かによ
って記憶内容をよみ出す。FIG. 1 shows the structure of a conventional non-volatile memory element having a floating gate. Fig. 1 fa) is the plane iM of the device, (b) is a section taken along A-A', and (C) is taken along B-B'.
A cross section is shown. fF is essentially a MO8Il field effect transistor with an isolated floating gate (1) and a control gate (2). The write is performed by the control gate (2
) and the drain (3), and hot electrons generated near the drain are injected into the floating gate (4). Further, by applying an appropriate potential to the readout control gate (2) and the drain (3), the stored contents are read out depending on whether or not a current flows through the channel depending on whether charge is injected or not.
一方、消去は例えば紫外線などを照射する事により、浮
遊ゲート中Ｋｌｌ積された電荷を放出する事によって行
う、従って全ての記憶素子が消去状態に変化してしまう
。On the other hand, erasing is performed by emitting the charges accumulated in the floating gate by irradiating it with ultraviolet rays, for example, and therefore all the memory elements change to the erased state.
本発明は、上鮎の点に鑑みて為され丸もので、電気的か
つ選択的に書き換え可能な不揮発性半導体メモリを提供
する事を目的としている。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory that is round and electrically and selectively rewritable.
即ち、本発明は、浮遊ゲートと容量結合する第１乃至第
３の電極を具備し、内１つの電極は全メモリセルで同電
位であり、＄１乃至第３の電極の内、制御電極である２
つの電極に高（低）電位、書き換え電極である他の電極
に低（高）電位が与えられたセルのみその浮遊ゲートが
高（低）電位となり前記他の電極との間で電荷の授受が
為されることで、電気的かつ選択的に記憶内容の書き換
えが行なわれるようにした不揮発性半導体メモリを提供
するものである。That is, the present invention includes first to third electrodes that are capacitively coupled to the floating gate, one of which has the same potential in all memory cells, and one of the control electrodes of $1 to the third electrode. There are 2
Only in a cell where one electrode is given a high (low) potential and the other electrode, which is the rewriting electrode, is given a low (high) potential, its floating gate becomes a high (low) potential and no charge is transferred between it and the other electrode. By doing so, it is possible to provide a nonvolatile semiconductor memory in which stored contents can be electrically and selectively rewritten.
以下、本発明の実施例を図面を参照して祥述する。Embodiments of the present invention will be described below with reference to the drawings.
第２図は、本発明による不揮発性半導体メモリの一実施
例についてそのメモリセル構造を示すもので、第２図（
ａ）は素子即ちセルの平面図、（ｂ）はＡ−Ａ’ 断Ｌ
（Ｃ）ハ８−Ｂ’断ｉ ｒｄ）＋４０− Ｃ” 断ｍ
ｔ示す、メモリセルは絶縁された浮遊ゲート（１）と。FIG. 2 shows the memory cell structure of an embodiment of the nonvolatile semiconductor memory according to the present invention.
a) is a plan view of the element or cell, (b) is A-A' section L
(C) C8-B'cutird)+40-C"cut
t, the memory cell is shown with an isolated floating gate (1).
第１の電極即ち第１の制御グー）＋２１、第２の電極即
ち第２の制御ゲート（５）を有する事を４Ｉ微としてい
る。 １３）はＮ型ドレイン（４）は炉−型ノース（＠
３の電極）で、１６）はＰ型８４基板、（７）はフィー
Ｒンド噴化膜、（８ａ）〜（８Ｃ）は熱酸化嗅である。The first electrode, that is, the first control gate (5), and the second electrode, that is, the second control gate (5) are defined as 4I micro. 13) is the N-type drain (4) is the furnace-type north (@
3), 16) is a P-type 84 substrate, (7) is a field bombardment membrane, and (8a) to (8C) are thermal oxidation electrodes.
浮遊グー）ｆｉｌ、第１の制御ゲート（２）は夫々Ｎ”
型多結晶ケイ素で、膜厚は夫ｈ ４ｏｏｏＫであ抄、第
２の制御ゲート（５）は配線用金属材料（ＡＩ）である
。floating goo) fil, the first control gate (2) are each N”
The second control gate (5) is made of a metal material (AI) for wiring.
又、熱酸化ｆｉｌ （８ａ） 〜（８ｃ）の膜厚は夫ｋ
ｇｍ、６ｂ、ｇｃｉｓｏｏｕ、 ｓｃ・・・２００＾
である。浮遊ゲート１１）と第２の制御ゲートである配
線用金属材料（Ａ／）との容量結合部の形成け、第１の
制御ゲート（２）を多結晶ケイ素で＠成後、素子保饅用
の絶縁膜゛９）を堆積し、公知の方法により容量形成部
（６）の絶縁膜を除去し。In addition, the film thickness of thermal oxidation films (8a) to (8c) is
gm, 6b, gcisou, sc...200^
It is. After forming the first control gate (2) with polycrystalline silicon to form a capacitive coupling part between the floating gate 11) and the wiring metal material (A/) which is the second control gate, An insulating film (9) is deposited, and the insulating film in the capacitor forming portion (6) is removed by a known method.
浮遊ゲート（１）を熱酸化し、容量部の絶縁膜（８ｄ）
を形成する。あるいは、第２図（ｅ）に示す如く、浮遊
ゲート１１）上に保膜用絶縁ＩＩ ＋９）と異なる絶縁
１１（１・（例えば窒化シリコン）を堆積し、同様に容
量部１６）の絶縁膜、９）を除去し、第２の制御ゲート
（５）である金属配線材料（Ａ／）を堆積する事によっ
て形成する事が可能である。基板は接地される。その電
気的等価１０１′＠を第３図に示す、浮遊ゲートの電位
ｖヒＧは等価回路を用いて、次の様に表わされる。The floating gate (1) is thermally oxidized, and the insulating film (8d) of the capacitor part is
form. Alternatively, as shown in FIG. 2(e), an insulating film 11 (for example, silicon nitride) different from the film-holding insulator II +9) is deposited on the floating gate 11), and the insulating film of the capacitive part 16 is similarly deposited. , 9) and depositing a metal wiring material (A/) which is the second control gate (5). The board is grounded. The electrical equivalent 101'@ is shown in FIG. 3, and the floating gate potential vhiG is expressed as follows using an equivalent circuit.
ここでＶＣＧＩ 、ＶＣＧ２は夫々制御ゲート＋２）
＋５）１７）電位。Here, VCGI and VCG2 are control gates +2 respectively)
+5) 17) Potential.
ｖｌｌはソース電位、ｖｓは基板電位、Ｃｃ’ １ ｓ
ＣＣＦ ２は夫々制御グー） ＋２）（５）と浮遊ゲ
ート（１）間の結合容量、ＣＩＩは制御ゲート＋２）
（５）交差部のソース（４）と浮遊ゲート（１）間の結
合容量、 Ｃｒ８はトランジスタ領域の基板と浮遊ゲー
ト（１）間の結合容量である。vll is the source potential, vs is the substrate potential, Cc' 1 s
CCF 2 is the coupling capacitance between control gate (5) and floating gate (1), CII is control gate +2)
(5) Coupling capacitance between the source (4) and floating gate (1) at the intersection, Cr8 is the coupling capacitance between the substrate of the transistor region and the floating gate (1).
ＶＦＧ＝＝ （ＣｃＦｌ −ｖｃａ’ ＋Ｃｃｖ２・Ｖ
ｃａ２ ＋ＣＩＶ（３＋ＣＰ８ｖｌ） ／（Ｃｒｓ ＋
Ｃｃｔｒ１ ＋ＣＣＦ２ ＋（４） 従ッテ、７−Ｘ電
ＦＥＶｍｔ固定すると、第１の制御ゲート（２）と、第
２の制御ゲート（３）を用い、て浮遊ゲートの電位レベ
ルに対して、３つの状態をとりつる。即ち１）第１の制
御ゲートと第２の制御ゲートが共に高電位の場合（■）
第１の制御ゲート（２）と第２の制御ゲート（３）のど
ちらかが高電位で、他が低電位の場合（ｉｌｌ）第１の
制御グー） ＋２）と、第２の制御ゲート（３）が共に
低電位の場合である。VFG== (CcFl −vca' +Ccv2・V
ca2 +CIV(3+CP8vl)/(Crs+
Cctr1 +CCF2 + (4) If the 7-X voltage FEVmt is fixed, the first control gate (2) and the second control gate (3) are used to control the potential level of the floating gate by 3. Take control of two states. That is, 1) When the first control gate and the second control gate are both at high potential (■)
If either the first control gate (2) or the second control gate (3) is at a high potential and the other is at a low potential (ill), the first control gate (2) and the second control gate (3) 3) are both cases where the potential is low.
従って、第２図に示す如く、浮遊ゲート下の絶縁領域の
一部に、トンネル電流が（１）の場合（ｖｌが低電位）
、あるいは（ｉｌｌ）の場合（Ｖ、け高電位）Ｋのみ、
流れ他の状態では、流れないような傾蛾を杉成する事に
より、選択的に書き込みあるいは、消去を行う事が可能
となる。Therefore, as shown in Figure 2, when the tunnel current is (1) in a part of the insulating region under the floating gate (vl is a low potential)
, or in the case of (ill) (V, high potential) only K,
In other states, it is possible to selectively write or erase by creating a tilt that does not flow.
実際には第２図のメモリセルが基板上にマトリクス状に
配置されている０例えば第４図に示す様に上記のメモリ
セルＭがＭｌからＭ４まで配置されたメモリセルのマト
リクスを考える。In reality, the memory cells shown in FIG. 2 are arranged in a matrix on a substrate. For example, consider a matrix of memory cells in which the above-mentioned memory cells M are arranged from M1 to M4 as shown in FIG.
・〜ｆ、とＭ２のソース（４）は共通で１Ｍ３とＭ４の
ノース（４）′も共通である。同様に１＠１の制御グー
）＋２１２と＠２０制８ ’ｒ’ −） ＋５）１５）
’ ４ 夫＃ ｖｉｔＭｚ、ＭｓＭ４Ｋｌｌ Ｌテ共通
である。-The source (4) of ~f and M2 is common, and the north (4)' of 1M3 and M4 is also common. Similarly, 1@1 control goo) +212 and @20 system 8 'r' -) +5) 15)
'4 Husband #vitMz, MsM4Kll Lte is common.
初期状態では各メモリセルの浮遊ゲートに電荷の蓄積が
ないとすると、メモリセルＭｌにデータを書き込む場合
（ではドレイン１３） ＋３）’と第３の電極であゆ全
メモリセルで同電位が与えられるノース＋４）１４）’
ヲｏｖ （！： ＋ ”ｙ −又＊ 第１− Ｎｇ
２ ’） ［極テ４る制御デー） １２）（５）に＋２
０Ｖを印加する。そして制御ゲート・２ど＋５）′は０
■とする。このようにするとＭｌの浮遊ダート（１）は
高電位となり、２つの制御ゲート（２）・５）が交差す
る領域の熱酸化膜（８Ｃ）を通してトンネル璽、流によ
ってエレクトロンが浮遊ゲート（１）に注入され書き込
み状＠ ”１’となる。メモリセルＭ２も同時に書き込
む場合【はＭ２の制御ゲート（５どにも＋２０Ｖを印加
すれば良い。Assuming that there is no charge accumulated in the floating gate of each memory cell in the initial state, when writing data to the memory cell Ml (in this case, the drain 13) +3)' and the third electrode, the same potential is applied to all memory cells. North+4)14)'
Oov (!: + ”y -again* 1st- Ng
2') [Extreme control data) 12) +2 to (5)
Apply 0V. And the control gate 2+5)' is 0
■Let it be. In this way, the Ml floating dart (1) becomes high potential, and electrons flow through the thermal oxide film (8C) in the area where the two control gates (2) and 5) intersect, and the electrons flow to the floating gate (1). When the memory cell M2 is also written at the same time, +20V can be applied to the control gate (5) of M2.
次に、Ｍｌの内容を消去する場合には、Ｍｌのドレイン
（３）と（３Ｙをフロート（開放）にしておき、 ソー
−、Ｘｆ４） ４Ｙ Ｋ＋２０Ｖ、 ｉＥ １ 、 第
２ （ＤｆＷＪｌａケ） ＋２）（５）はＯｖを印加ｊ
、、（２）’ｆ５）’ ハ＋２０Ｖ Ｋ ｌ’１ツトＭ
、 ＋７）み浮遊ゲート（１）は低電位となりトンネル
電流によりソース（４）にエレクトロンが放出され＠Ｏ
”状態になる。Next, when erasing the contents of Ml, drain (3) of Ml and (3Y are floated (open), So-, Xf4) 4Y K+20V, iE 1, 2nd (DfWJlake) +2) (5) applies Ovj
,,(2)'f5)' C+20V K l'1t M
, +7), the floating gate (1) becomes low potential and electrons are emitted to the source (4) due to the tunnel current, @O
“Become a state.
ここでは、上述して来九様にノースと電気的に接続され
ているソースと同導電型領斌を書き換え電極である第３
の電極としているが、＠２図で（３）の領域をノースと
し、（４）の領域をドレインとしてもよい。その時は上
述書き込み、消去の電圧・印加はソースとドレインを読
み替えるこ）−になる。Here, we rewrite the source electrically connected to the north and the third electrode which is the same conductivity type as described above.
However, in Figure 2, the region (3) may be the north and the region (4) may be the drain. In that case, the above-mentioned writing and erasing voltages and applications should be read as source and drain).
以上の結果を下表に示す、高電位をＨ１低電位をＬで示
す。The above results are shown in the table below, where high potential is indicated by H and low potential is indicated by L.
以下余白
表 １
纜み川しは、ドレイン共通信号線（３） （３）’と、
それに矯直な制御ゲート信号４１ｔ２）又は（２どに読
み出し用の電位例えば＋５ｖを印加して、選ばれたメモ
リセルの記憶内容をよみ出す事ができる０以上を記憶装
置上のブロック配置で言えば、第５図の如く。Margin table below 1. The drain common signal line (3) (3)'
A direct control gate signal 41t2) or a read potential of, for example, +5V is applied to (2) to read out the memory contents of the selected memory cell. For example, as shown in Figure 5.
メモリセルマトリクスａ１）に対し制御’ｙ’−ト−ｙ
−ｓ −ダ１１１３を用いて、読み出しを行い、制御ゲ
ートデコーダ１１３と制御ゲートデコーダ２ａ３を用い
て、書き込みちるいは消去を行う事になる。を走読み出
しの際選択されていない素子のチャネルに電流が流れろ
つを防ぐ九め（使用していない制御ゲートデコーダ＋１
１は選択した素子のよみ出しの丸めに制御グーＦデコー
ダ０１により与えられる制御ゲート電位よ抄も低電位に
保つ必要がある。を九、配線用金属材料（Ａ／）で杉成
した制御電極をよみ出し用に用い−る事により、よシ高
運のよみ出しが可能である。Control 'y'-to-y for memory cell matrix a1)
-s-der 1113 is used for reading, and control gate decoder 113 and control gate decoder 2a3 are used for writing or erasing. The 9th point (unused control gate decoder + 1
1, it is necessary to keep the control gate potential given by the control gate F decoder 01 at a low potential to round off the readout of the selected element. (9) By using a control electrode made of a metal material for wiring (A/) for reading, it is possible to read with high luck.
尚、書き込みＩ（ついては、従来と同様に、ドレイン共
通信号線とそれに垂直な制御ゲート信号線を用いて、ト
ランジスタ領域からホットエレクトロンによる注入を行
う事も可能である。Note that for write I (for write I), it is also possible to inject hot electrons from the transistor region using a common drain signal line and a control gate signal line perpendicular thereto, as in the conventional case.
即ち、その場合には第２．＠３の電極を用いて書き込み
、第１乃至第３の電極を用いて１消去”という書き換え
を行なうことになる。That is, in that case, the second. Writing is performed using the @3 electrode, and 1 erasing is performed using the first to third electrodes.
以上の実施例ではＰＷ基板を用い九が、Ｎｕｌｌ基板を
用いる場合にはソース、ドレインの導電型は逆になり、
電荷の授受は正孔のトンネル電流で行なわれる。In the above embodiment, a PW substrate is used, but when a Null substrate is used, the conductivity types of the source and drain are reversed.
Charge transfer is performed by hole tunneling current.
以上述べた如く１本発明によれば電気的かつ選択的に記
憶内容の書き換えが可能な不揮発性半導体メモリを実現
する事ができる。従来の不揮発性メモリでは、電荷の注
入のみが選択的に行なわれ。As described above, according to the present invention, it is possible to realize a nonvolatile semiconductor memory whose stored contents can be electrically and selectively rewritten. In conventional nonvolatile memory, only charge injection is performed selectively.
電荷の放出に対しては、選択性はなかったＪ全ビット消
去）、これに対し１本発明の如く、電荷の注入と放出の
モードを選択し泰っ選択的に書き込み、あるいは、消去
という書き換えを行うためには、書き換えのモード及び
ビットの選択性を得るために少なくとも３本が必要で、
しかも制御ゲートを２つ設けて浮遊ゲートと容量結合す
るソースを含め何れ奉を全メモリセルで共通電位にしな
ければならない。For charge release, there was no selectivity (all bits erased), but as in the present invention, the mode of charge injection and release is selected and selectively written or erased. In order to perform this, at least three wires are required to obtain the rewriting mode and bit selectivity.
In addition, two control gates must be provided so that all memory cells, including the source capacitively coupled to the floating gate, have a common potential.
尚、＄２図で示したメモリセルは第１及び第２の電極の
浮遊ゲートとの結合容量叶はぼ等しく。Incidentally, in the memory cell shown in figure $2, the coupling capacitances between the first and second electrodes and the floating gate are approximately equal.
同電位が与えられる第３の電極の浮遊ゲートとの結合等
量はこれより小となる様構成されている。The third electrode to which the same potential is applied is configured to have a smaller coupling equivalent with the floating gate.
これにより高い輪作マージンが得られる。即ち第１、第
２の制御ゲートと５浮遊ゲートの結合容せのばらつきが
大きいと０Ｎ１０ Ｆ’ Ｆ’比が小さくな抄、又。This results in a high crop rotation margin. That is, if the variation in the coupling capacitance between the first and second control gates and the fifth floating gate is large, the 0N10 F'F' ratio will be small.
第３の電極と浮遊ゲートの結合容量が大きくなるとこれ
も０Ｎ１０ Ｐ Ｐ比を下げることになる。又、第１の
制御ゲート下の絶縁膜と第２の制御ゲート下の絶縁膜の
鍔電車を異ならせても良い、ｔた、本実施例では、＃ｃ
１の制御ゲートを多結晶ケイ素、第２の制御ゲートを配
線用金属材料で形成したが、第１の制御ゲートを配線用
金属材料で、第２の制御ゲートを多結晶ケイ素で形成し
てもよい。If the coupling capacitance between the third electrode and the floating gate increases, this will also lower the 0N10 P P ratio. In addition, the collars of the insulating film under the first control gate and the insulating film under the second control gate may be different. In this embodiment, #c
Although the first control gate is formed of polycrystalline silicon and the second control gate is formed of a metal material for wiring, it is also possible to form the first control gate of a metal material for wiring and the second control gate of polycrystalline silicon. good.
その他１本発明の主旨を逸脱しない範囲で種々変形する
ことが出来る。Other than that, various modifications can be made without departing from the spirit of the present invention.
第１１菌ｒ５１）〜（ｃ）は従来例を説明する図、＠２
図（ａ）〜ｒｅ）は本発明による一実施例を説明する図
、第３図は本発明による一実施例の等価回路を説明する
図、ｖ、４図は本発明による一実施例のメモリセルマト
リクスを説明する図、第５図はデ１−ダを備えた記憶装
置の構成を示す図で、？）る。図に於いて、（１）・・
・浮遊ゲート、
＋２１・・・第１の制御ゲート（第１の電極）、（４）
・・・ソース（第３の電極）、
（５）・・・第２の制御ゲート（第２の電極）。
代理人 弁理士 則 近 憲 佑
（ほか１名）
第 １ 図 第 ２ 園側）
（０Ｌン
第 ２ 図 第 ４ 図第３図
第５図The 11th bacterium r51) to (c) are diagrams explaining the conventional example, @2
Figures (a) to (re) are diagrams for explaining one embodiment of the present invention, Figure 3 is a diagram for explaining an equivalent circuit of one embodiment of the present invention, and Figures v and 4 are memories for one embodiment of the present invention. FIG. 5 is a diagram explaining the cell matrix, and is a diagram showing the configuration of a storage device equipped with a data reader. ). In the figure, (1)...
・Floating gate, +21...first control gate (first electrode), (4)
...source (third electrode), (5)...second control gate (second electrode). Agent: Patent attorney Noriyuki Chika (and 1 other person) (Figure 1, Figure 2)
(0Ln Figure 2 Figure 4 Figure 3 Figure 5
Claims (1)
が同一基板にマトリクス状に配置され、各メモリセルは
、前記浮遊ゲートと容量結合すると共に何れか１つの電
極が全メモリセルで同電位が与えられる＠１乃至第３の
電極を備え、この第１乃至第３の電極の内、制御電極で
ある２つの電極に高電位、書き換え電極である他の電極
に低電位が与えられたメモリセルのみ浮遊ゲートが高電
位となるか又は制御電極である２つの電極に低電位、書
き換え電極でちる他の電極に高電位が与えられたメモリ
セルのみ浮遊ゲートが低電位となりその浮遊ゲートと前
記他の電極との間で電荷の授受が為されて配憶内容の電
気的書き換えが行なわれる不揮発性半導体メモリにおい
て、＃Ｈの電極が多結晶ケイ素で形成され、第２の電極
が金属材料で形幌され、第３の電極はドレインあるいは
ソースと電気的に接続されているドレイン、ノースと同
伝導形領域である事を特徴とする不揮発性半導体メモリ
。 ＋２３＠１及び第２の電極の浮遊ゲートとの結合容址は
ほぼ等しく、第３の電極の浮遊ゲートとの結合容置はこ
れより小である事を特徴とする特許杵晴求の範ＦＭ＠１
項記載の不揮発性半導体メモリ。[Scope of Claims] (Memory cells having electrically insulated floating gates are arranged in a matrix on the same substrate, each memory cell is capacitively coupled to the floating gate, and any one electrode is fully connected to the floating gate. The memory cell has @1 to 3rd electrodes that are given the same potential, and among these 1st to 3rd electrodes, two electrodes that are control electrodes are given a high potential, and the other electrode that is a rewriting electrode is given a low potential. The floating gate will be at a high potential only in memory cells that are given a high potential, or the floating gate will be at a low potential only in memory cells where two electrodes that are control electrodes are given a low potential and the other electrodes that are rewrite electrodes are given a high potential. In a nonvolatile semiconductor memory in which the storage contents are electrically rewritten by transferring charge between the floating gate and the other electrode, the #H electrode is formed of polycrystalline silicon; A nonvolatile semiconductor memory characterized in that the electrode is formed of a metal material, and the third electrode is a region of the same conductivity type as the drain and the north, which are electrically connected to the drain or the source. Patent Haruyuki Ki's range FM@1 characterized in that the coupling capacity of the second electrode with the floating gate is approximately equal, and the coupling capacity of the third electrode with the floating gate is smaller.
Non-volatile semiconductor memory as described in Section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56124725A JPS5827370A (en) | 1981-08-11 | 1981-08-11 | Non-volatile semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56124725A JPS5827370A (en) | 1981-08-11 | 1981-08-11 | Non-volatile semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5827370A true JPS5827370A (en) | 1983-02-18 |
Family
ID=14892554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56124725A Pending JPS5827370A (en) | 1981-08-11 | 1981-08-11 | Non-volatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827370A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS614242A (en) * | 1984-06-19 | 1986-01-10 | Seiko Epson Corp | Semiconductor integrated circuit device |
| JPH0646092U (en) * | 1992-11-30 | 1994-06-24 | 前田建設工業株式会社 | Cutting device for rod |
-
1981
- 1981-08-11 JP JP56124725A patent/JPS5827370A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS614242A (en) * | 1984-06-19 | 1986-01-10 | Seiko Epson Corp | Semiconductor integrated circuit device |
| JPH0646092U (en) * | 1992-11-30 | 1994-06-24 | 前田建設工業株式会社 | Cutting device for rod |
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