JPS60117769A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS60117769A
JPS60117769A JP58227258A JP22725883A JPS60117769A JP S60117769 A JPS60117769 A JP S60117769A JP 58227258 A JP58227258 A JP 58227258A JP 22725883 A JP22725883 A JP 22725883A JP S60117769 A JPS60117769 A JP S60117769A
Authority
JP
Japan
Prior art keywords
laser
substrate
contact regions
type
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58227258A
Other languages
Japanese (ja)
Inventor
Nobuo Sasaki
伸夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58227258A priority Critical patent/JPS60117769A/en
Publication of JPS60117769A publication Critical patent/JPS60117769A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a PROM, which is made conductive or non-conductive only by the radiation of laser after the completion of the device so as to form a program, has a simple structure, and can accomplish high integration, by using the shift of a flat band voltage into the negative direction due to the radiation of the laser, and inverting the interface between the semiconductor and an oxide film. CONSTITUTION:A pair of N<+> type contact regions, i.e., the first contact region 4 and the second contact region 5, having the reverse conductive type with respect to a substrate 1, is formed in a P type silicon substrate, with an interval being provided. An oxide film 2, which strides on the part between the contact regions, is formed on the surface of the substrate 1. Electrode wirings 6 and 7 comprising Al are formed on the contact regions 4 and 5, respectively. At first, the part between the electrode wirings 6 and 7 is not conducted. Then, laser 3 is projected through a PSG8. The substrate is P type, but Qss is moved to the positive side by the radiation of the laser. As a result, the surface of the substrate is inverted to (n). Thus, the part between the contact regions 4 and 5 is conducted. In this way, the P-ROM is made conductive by projecting the laser, and writing is performed.

Description

【発明の詳細な説明】 技術分野 本発明はレーザ照射によるフラットバンドポルテツジV
FRの負方向・\のシフトを用いて、 5i−sto。
[Detailed Description of the Invention] Technical Field The present invention relates to flat band portage V by laser irradiation.
5i-sto using negative direction/\ shift of FR.

界面を反転させ、導通をとる事により、プログラムする
プログラマブルROM (FROM)に関する。
It relates to a programmable ROM (FROM) that is programmed by inverting the interface and establishing conduction.

技術の背景 本発明者は酸化膜をつけたStにArレーザ照射を行な
ったところ、第1図に示すように5t−8in。
BACKGROUND OF THE INVENTION The present inventor irradiated St with an oxide film on it using an Ar laser, and the result was 5t-8in as shown in FIG.

界面の電荷であるQssが変化することを見い出した。It was found that Qss, which is the charge at the interface, changes.

第1図はそれをMOSダイオードのフラットバンドボル
テツジVF’Bで表わしたもので、横軸にレーザパワー
、縦軸にフラツ斗バンドボルテツジのシフトΔVvBを
とっている。図示のごと(,8’w位からΔv?Bはレ
ーザパワーに対して単調に増加している。すなわちレー
ザパワーを増すとvynがマイナスの方向にずれる。つ
まりQssは普通圧だがそれがプラスの方向に大きくな
っていく。これはnチャネルMO8)ランジスタではデ
ィプレッションモード側・\、PチャネルMOSトラン
ジスタではエンハンスメントモード側・\それぞれシフ
トすることを示す。本発明は、このレーザ照射によるS
t −sto2界面の反転を利用し、FROM ’に得
るものである。
FIG. 1 shows this in terms of the flat band voltage VF'B of the MOS diode, with the horizontal axis representing the laser power and the vertical axis representing the flat band voltage shift ΔVvB. As shown in the figure (from about 8'w), Δv?B increases monotonically with respect to the laser power.In other words, as the laser power increases, vyn shifts in the negative direction.In other words, Qss is normal pressure, but it becomes positive. This indicates that the n-channel MO8) transistor shifts to the depletion mode side, and the P-channel MOS transistor shifts to the enhancement mode side. The present invention provides S
This is obtained from FROM' by using the inversion of the t-sto2 interface.

従来技術 従来、FROMにはフユーズ型やダイオード対型などが
ある。フユーズ型は電流によってフユーズを溶断させ、
ダイオード対型は一方のダイオードを逆電圧で破壊、導
通させる。このような従来のFROMはデバイスにフユ
ーズやダイオード対を形成するためその構造が複雑にな
り、集積度を上げる上で離点があった。
BACKGROUND TECHNOLOGY Conventionally, FROMs include fuse type and diode pair type. The fuse type uses an electric current to blow out the fuse.
In the diode pair type, reverse voltage destroys one diode and causes it to conduct. In such a conventional FROM, the structure is complicated because fuses and diode pairs are formed in the device, and there is a problem in increasing the degree of integration.

発明の目的 本発明は、構造が簡単で、高集積化が可能なプログラマ
ブルROM(PROM) ’&レーザ照射による半導体
−酸化膜界面の反転を利用して得ることをその目的とす
る。
OBJECTS OF THE INVENTION An object of the present invention is to obtain a programmable ROM (PROM) which has a simple structure and can be highly integrated by utilizing the inversion of the semiconductor-oxide film interface by laser irradiation.

発明の構成及び作用 まず、本発明において、利用するところの本発明者が発
見した先に技術の背景で概説したレーザ照射の効果を詳
述する。第2図において、1はシリコンの基板であり、
表面に膜厚が420 XのSt (h2が形成されてい
る。今、基板1を!100 ℃&こ加熱しておいて、図
Aの酸化膜2上ににレーザのスポット3を5 cfn/
sの速さで図Bのようにスキャンする。そのピッチは6
0μ/ステツプとした。以上の条件で第1図に示すよう
なArレーザパワーとΔV7B(フラットバンドボルテ
ッジのシフト)との関係が生じ、Arレーザパワーが8
w以上でΔVFBが単調に負の方向に増加する現象がみ
もれる。なお、゛第1図では8wのレーザパワーで△v
ynの変化が始まっているが、これは酸化膜厚やレーザ
のしぼりのフォーカスで変化し、ある場合には4wで立
上ることもあるが、いずれ(Cせよレーザパワーを増す
とΔvPBは単調に負の方向に増加する。つまりSl 
−810!界面の電荷であるQoは普通正だがそれカフ
ラスの方向・\大きくなっていく。
Structure and operation of the invention First, the effects of laser irradiation, which are utilized in the present invention and which were discovered by the present inventor and outlined in the technical background section above, will be described in detail. In FIG. 2, 1 is a silicon substrate;
A St (h2) film with a thickness of 420× is formed on the surface. Now, heat the substrate 1 to 100° C. and place the laser spot 3 on the oxide film 2 shown in Figure A at 5 cfn/
Scan as shown in Figure B at a speed of s. Its pitch is 6
It was set to 0μ/step. Under the above conditions, a relationship between Ar laser power and ΔV7B (shift of flat band voltage) as shown in Fig. 1 occurs, and Ar laser power is 8
A phenomenon in which ΔVFB monotonically increases in the negative direction above w is observed. In addition, in Figure 1, △v with a laser power of 8W
yn has started to change, but this changes depending on the oxide film thickness and the focus of the laser throttle, and in some cases it may rise at 4W, but eventually (C) When the laser power is increased, ΔvPB becomes monotonous. increases in the negative direction, that is, Sl
-810! Qo, which is the charge on the interface, is normally positive, but it increases in the direction of the cuff.

本発明はこれを利用するもので、以下実施例により本発
明の詳細な説明する。第3図に本発明の一実施例を示し
ており、p型のシリコン基板1に相隔てて基板1と反対
導電型のn+型の1対のコンタクト領域すなわち第1の
コンタクト領域4と第2のコンタクト領域5が形成され
、各部のコンタクト領域間を跨ぐ酸化膜(SiO,、)
2が基板10表面に形成されている。そしてそれぞれの
コンタクト領域4,5にはAtからなる電離配線6.7
が形成されている。図への各部の寸法を例示すると、コ
X9表面保護膜8 (PSG)の厚さ4が1μm、コン
タクト領域の深さt!+が3000 Xである。初め、
第6図Aの電極配線6,7間は非導通である。次に図B
のごと(、P8G8Y通して、レーザ3を照射す果、コ
ンタクト領域4.5間が導通する。このように、第6図
A、Bに示したのは、V−ザな照射することで導通状態
にして書込むP−ROMであり、その上面図を第4図A
、Bに示す。簡単のため、コンタクト領域4.5とレー
ザスポット9の関係のみ示す。実際をこはデバイスが出
来上ってから晋込むのでAt電極配珠6,7、全表面を
覆う保護層のPSG Bがあるが、前記のとと< PS
G8は1μm程度であり、 PSG自体可視光に対して
透明だから、これすJIJ1シてSi −5lot構造
にレーザを照射することができる。図Bのように実際は
多数の素子が基板1上に形成されており、レーザスポッ
トは他の素子にかふらないようにしばる必要があるが、
レーザビームはtopmφ以下(15μmも可)に容易
にしばり込めるため、十分に高集積化をすることが可能
となる。
The present invention makes use of this, and the present invention will be described in detail below with reference to Examples. FIG. 3 shows an embodiment of the present invention, in which a pair of n+ type contact regions, a first contact region 4 and a second contact region, which are of the opposite conductivity type to the substrate 1, are spaced apart from each other on a p-type silicon substrate 1. A contact region 5 is formed, and an oxide film (SiO, . . . ) spanning between the contact regions of each part is formed.
2 is formed on the surface of the substrate 10. In each contact region 4, 5, ionized wiring 6.7 made of At
is formed. To illustrate the dimensions of each part in the figure, the thickness 4 of the surface protection film 8 (PSG) is 1 μm, the depth t of the contact region! + is 3000X. beginning,
There is no conduction between the electrode wirings 6 and 7 in FIG. 6A. Next, Figure B
As a result of irradiating the laser 3 through P8G8Y, conduction occurs between the contact regions 4.5. In this way, as shown in FIGS. This is a P-ROM that is written in the state, and its top view is shown in Figure 4A.
, shown in B. For simplicity, only the relationship between the contact area 4.5 and the laser spot 9 is shown. In reality, the details are worked on after the device is completed, so there are At electrode beads 6 and 7 and a protective layer PSG B that covers the entire surface.
G8 is about 1 μm, and since PSG itself is transparent to visible light, it is possible to irradiate a laser onto the Si-5 lot structure using JIJ1. As shown in Figure B, a large number of elements are actually formed on the substrate 1, and the laser spot needs to be tied so that it does not cover other elements.
Since the laser beam can be easily confined within topmφ (15 μm or less), it is possible to achieve a sufficiently high degree of integration.

以上p型基板を用いた場合を示したが、基板上の各コン
タクト領域4.5間はまわりがすべて初め非導通であり
、これなレーザで導通に変えるので素子間を分離する必
要はない。ところがn型基板を用いるときは周辺が導通
状態となっているのでレーザで一部だけチャンネルを切
って非導通にしても意味がない。そこで第5図に示すよ
うに各素子を分離してやる必要がある。10が分離領域
であり、内部に形成される素子は第3図Aと同様な構成
であるが、基板1がn型でコンタクト領域4゜5がp+
型の領域(コンタクト領域4’、5’と示す)である点
が相違する。函初、コンタクト領域4′。
Although the case in which a p-type substrate is used has been described above, the surrounding areas between each contact region 4.5 on the substrate are initially non-conducting, and are made conductive by this laser, so there is no need to isolate the elements. However, when using an n-type substrate, the periphery is in a conductive state, so there is no point in cutting only part of the channel with a laser to make it non-conductive. Therefore, it is necessary to separate each element as shown in FIG. 10 is an isolation region, and the elements formed therein have the same structure as in FIG. 3A, except that the substrate 1 is of n type and the contact region 4.
The difference is that they are mold regions (denoted as contact regions 4', 5'). First contact area 4'.

5′間は周囲にチャネルが出来て等通状態にあるが、レ
ーザスポット9を第5図のように照射すると、コンタク
ト領域a1 、51間が非導通に変化する。
A channel is formed around the contact area 5' and the contact area is in a constant state of electrical conductivity, but when the laser spot 9 is irradiated as shown in FIG. 5, the contact area between the contact areas a1 and 51 becomes non-conductive.

発明の詳細 な説明のごとく、本発明によれば、デバイスの完成の後
でレーザ照射のみで素子な導通又は非導通にしてプログ
ラムができるという効果がある。
As described in the detailed description of the invention, the present invention has the advantage that after the device is completed, it is possible to program the device by making it conductive or non-conductive using only laser irradiation.

また構造が簡単で、しかもレーザビームは0.5〜1μ
m位にしばり込めるので本発明によれば高集積化が容易
である。
In addition, the structure is simple, and the laser beam is 0.5 to 1μ.
According to the present invention, it is easy to achieve a high degree of integration because the device can be packed into the m order.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の前提となる81−5lotにレーザ照
射した時の△VFBの変化を示すグラフ、第2図A、B
はそれぞれSt −5l(hに対するレーザ照射状態の
説明図、 第6図A、Bはそれぞれ本発明の実施例のレーザ照射前
の構成及びレーザ照射後の構成の説明図、第4図は本発
明の実施例のAは1箇の素子についてのレーザ照射状態
、Bは多欽の素子が形成された基板でのレーザ照射状態
のそれぞれ説明図、第5図は本発明の他の実施例の上面
図。 1・・・シリコン基板、2 ・= 5lot、4 、5
 ・=コンタクト領域、6,7・・・電極配線、8・・
・PEG、9・・・し−ザスポット 特許出願人 富士通株式会社 代理人 弁理士玉蟲久五部 (外1名) 第1図 第2図 第3図 第 4 図 A 第5図
Figure 1 is a graph showing the change in ΔVFB when 81-5 lot, which is the premise of the present invention, is irradiated with laser, Figure 2 A, B
are explanatory diagrams of the laser irradiation state for St -5l (h, respectively. Figures 6A and B are explanatory diagrams of the configuration before and after laser irradiation of the embodiment of the present invention, respectively. Figure 4 is an explanatory diagram of the configuration of the embodiment of the present invention. In this embodiment, A is an explanatory diagram of the laser irradiation state for one element, B is an explanatory diagram of the laser irradiation state for a substrate on which multiple elements are formed, and FIG. 5 is a top view of another embodiment of the present invention. Figure. 1... Silicon substrate, 2 ・= 5 lots, 4, 5
・=Contact area, 6, 7... Electrode wiring, 8...
・PEG, 9...shi-TheSpot Patent Applicant Fujitsu Limited Agent Patent Attorney Gobe Tamamushi (one other person) Figure 1 Figure 2 Figure 3 Figure 4 Figure A Figure 5

Claims (1)

【特許請求の範囲】[Claims] pまたはn型の半導体基板に相隔てて形成された基板と
反対導電型の1対のコンタクト領域と、該コンタクト領
域間の半導体基板の表面に形成された酸化膜と、前記1
対のコンタクト領域にそれぞれ形成された電極配線とか
ら構成され、レーザ照射によるフラットバンドボルテツ
ジの負方向・\のシフトを用いて半部体−酸化膜界面が
反転されて前記1対のコンタクト領域間が導通または非
導通となされることを特徴とするプログラム可能な読出
し専用半纏体メモリ装置。
a pair of contact regions of conductivity type opposite to that of the substrate formed on a p- or n-type semiconductor substrate at a distance; an oxide film formed on the surface of the semiconductor substrate between the contact regions;
and electrode wiring formed in each of the pair of contact regions, and the half-body-oxide film interface is reversed by shifting the flat band voltage in the negative direction/\ by laser irradiation to connect the pair of contact regions. What is claimed is: 1. A programmable read-only semi-integrated memory device, characterized in that the space between the two is electrically conductive or non-conductive.
JP58227258A 1983-11-30 1983-11-30 Semiconductor memory device Pending JPS60117769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58227258A JPS60117769A (en) 1983-11-30 1983-11-30 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58227258A JPS60117769A (en) 1983-11-30 1983-11-30 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS60117769A true JPS60117769A (en) 1985-06-25

Family

ID=16857999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58227258A Pending JPS60117769A (en) 1983-11-30 1983-11-30 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS60117769A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002023553A1 (en) * 2000-09-13 2002-03-21 Siemens Aktiengesellschaft Organic memory, identification marker (rfid-tag) with organic memory and uses of an organic memory
US6960489B2 (en) 2000-09-01 2005-11-01 Siemens Aktiengesellschaft Method for structuring an OFET
US7064345B2 (en) 2001-12-11 2006-06-20 Siemens Aktiengesellschaft Organic field effect transistor with off-set threshold voltage and the use thereof
US7223995B2 (en) 2002-03-21 2007-05-29 Polyic Gmbh & Co. Kg Logic components comprising organic field effect transistors
US7229868B2 (en) 2000-12-08 2007-06-12 Polyic Gmbh & Co. Kg Organic field-effect transistor, method for structuring an OFET and integrated circuit
US7238961B2 (en) 2001-02-09 2007-07-03 Polyic Gmbh & Co. Kg Organic field effect transistor with a photostructured gate dielectric, method for the production and use thereof in organic electronics
US7298023B2 (en) 2001-10-16 2007-11-20 Polyic Gmbh & Co. Kg Electronic device with organic insulator
US7414513B2 (en) 2002-08-23 2008-08-19 Polyic Gmbh & Co. Kg Organic component for overvoltage protection and associated circuit
US7483275B2 (en) 2001-10-18 2009-01-27 Polyic Gmbh & Co. Kg Electronic unit, circuit design for the same, and production method
US7709865B2 (en) 2002-06-13 2010-05-04 Polyic Gmbh & Co. Kg Substrate for an organic field effect transistor, use of said substrate, method of increasing the charge carrier mobility, and organic field effect transistor (OFET)
US7786818B2 (en) 2004-12-10 2010-08-31 Polyic Gmbh & Co. Kg Electronic component comprising a modulator
US8044517B2 (en) 2002-07-29 2011-10-25 Polyic Gmbh & Co. Kg Electronic component comprising predominantly organic functional materials and a method for the production thereof
US8144495B2 (en) 2006-03-22 2012-03-27 Polyic Gmbh & Co. Kg Method for programming an electronic circuit and electronic circuit
CN111693850A (en) * 2020-06-17 2020-09-22 西安微电子技术研究所 Monitoring method for anti-irradiation performance of chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694669A (en) * 1979-12-27 1981-07-31 Toshiba Corp Manufacture of mos-type integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694669A (en) * 1979-12-27 1981-07-31 Toshiba Corp Manufacture of mos-type integrated circuit

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6960489B2 (en) 2000-09-01 2005-11-01 Siemens Aktiengesellschaft Method for structuring an OFET
JP2004509458A (en) * 2000-09-13 2004-03-25 シーメンス アクチエンゲゼルシヤフト Organic data memory, ID tag (RFID tag) with organic data memory, and use of organic data memory
US6903958B2 (en) 2000-09-13 2005-06-07 Siemens Aktiengesellschaft Method of writing to an organic memory
WO2002023553A1 (en) * 2000-09-13 2002-03-21 Siemens Aktiengesellschaft Organic memory, identification marker (rfid-tag) with organic memory and uses of an organic memory
US7229868B2 (en) 2000-12-08 2007-06-12 Polyic Gmbh & Co. Kg Organic field-effect transistor, method for structuring an OFET and integrated circuit
US7238961B2 (en) 2001-02-09 2007-07-03 Polyic Gmbh & Co. Kg Organic field effect transistor with a photostructured gate dielectric, method for the production and use thereof in organic electronics
US7298023B2 (en) 2001-10-16 2007-11-20 Polyic Gmbh & Co. Kg Electronic device with organic insulator
US7483275B2 (en) 2001-10-18 2009-01-27 Polyic Gmbh & Co. Kg Electronic unit, circuit design for the same, and production method
US7064345B2 (en) 2001-12-11 2006-06-20 Siemens Aktiengesellschaft Organic field effect transistor with off-set threshold voltage and the use thereof
US7223995B2 (en) 2002-03-21 2007-05-29 Polyic Gmbh & Co. Kg Logic components comprising organic field effect transistors
US7709865B2 (en) 2002-06-13 2010-05-04 Polyic Gmbh & Co. Kg Substrate for an organic field effect transistor, use of said substrate, method of increasing the charge carrier mobility, and organic field effect transistor (OFET)
US8044517B2 (en) 2002-07-29 2011-10-25 Polyic Gmbh & Co. Kg Electronic component comprising predominantly organic functional materials and a method for the production thereof
US7414513B2 (en) 2002-08-23 2008-08-19 Polyic Gmbh & Co. Kg Organic component for overvoltage protection and associated circuit
US7786818B2 (en) 2004-12-10 2010-08-31 Polyic Gmbh & Co. Kg Electronic component comprising a modulator
US8144495B2 (en) 2006-03-22 2012-03-27 Polyic Gmbh & Co. Kg Method for programming an electronic circuit and electronic circuit
CN111693850A (en) * 2020-06-17 2020-09-22 西安微电子技术研究所 Monitoring method for anti-irradiation performance of chip
CN111693850B (en) * 2020-06-17 2023-03-28 西安微电子技术研究所 Monitoring method for anti-irradiation performance of chip

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