JPS60112326A - Analog/digital converter - Google Patents

Analog/digital converter

Info

Publication number
JPS60112326A
JPS60112326A JP21946283A JP21946283A JPS60112326A JP S60112326 A JPS60112326 A JP S60112326A JP 21946283 A JP21946283 A JP 21946283A JP 21946283 A JP21946283 A JP 21946283A JP S60112326 A JPS60112326 A JP S60112326A
Authority
JP
Japan
Prior art keywords
lamp voltage
switch
accuracy
voltage
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21946283A
Other languages
Japanese (ja)
Inventor
Shinichi Hayashi
林 晋一
Kenji Maio
健二 麻殖生
Atsushi Moriya
淳 森谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Healthcare Manufacturing Ltd
Original Assignee
Hitachi Ltd
Hitachi Medical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Medical Corp filed Critical Hitachi Ltd
Priority to JP21946283A priority Critical patent/JPS60112326A/en
Publication of JPS60112326A publication Critical patent/JPS60112326A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/1205Multiplexed conversion systems
    • H03M1/123Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/50Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56Input signal compared with linear ramp

Abstract

PURPOSE:To attain effectively the desired accuracy for a current source of a lamp voltage generator by comparing the input voltage with the lamp voltage given from the generator for broken line-shaped lamp voltage which contains switch groups and an integrator and extracting the digital output corresponding to each input voltage with the accuracy necessary for each register. CONSTITUTION:A switch S0 is opened at a time point t0 and a switch S1 is closed for a section of t1. The lamp voltage (y) rises up with a slope proportional to the courrent value I1 by an integration circuit (OP and C). A counter K1 starts counting with a clock CLK and produces the digital value corresponding to the lamp voltage value. the contents of a counter K are set to register groups L1-Ln when coincidence is obtained between the input voltages V1-Vn and the lamp voltage respectively. The switch S1 is opened at a time point (t0+t1) and the switch S2 is closed for a section of t2. The voltage (y) rises up in proportion to the value I2, and the counter K1 is shifted down by a shift signal SFT by an amount equivalent to the difference of weight between current values I1 and I2.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、X線eT装置等のように多数の検出器出力デ
ータを収集する必要のある装置に好適なアナログディジ
タル変換器(以下、ADi換器と呼ぶ。)に関する。
Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to an analog-to-digital converter (hereinafter referred to as an ADi converter) suitable for a device such as an X-ray eT device that needs to collect a large number of detector output data. ).

〔発明の背景〕[Background of the invention]

X線CT装置等の多チャン坏ルデータ収集回路として、
積分方式AD変換器を使用する方法がある。1つのラン
プ電圧発生器を全テヤンイ・ルが共有し、各チャンネル
の入力電圧と比較を行なうことにより、計数を行ないデ
ィジタル出力として取出す。このランプ電圧発生器とし
て、直線や折線を用いる方法である。特に、変換精度を
上げるために(ダイナミックレンジを上げるために)折
線が使われた場合、ランプ電圧発生器内の電流源の精度
を良くする必要があり、このための手段が複雑になると
いう問題点があった。
As a multi-channel data acquisition circuit for X-ray CT equipment, etc.
There is a method using an integral type AD converter. All units share one ramp voltage generator, and by comparing the input voltage of each channel, counting is performed and output as a digital output. This method uses a straight line or a broken line as the lamp voltage generator. In particular, when a broken line is used to improve conversion accuracy (increase dynamic range), the accuracy of the current source in the lamp voltage generator must be improved, and the means for achieving this become complex. There was a point.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、折線を用いたランプ電圧発生器による
積分方式ADf換器において、ランプ電圧発生器内の゛
電流源の必要精度を効率良く維持するためのアナログ・
ディジタル変換器全提供することにある。
An object of the present invention is to provide an analog ADf converter using a broken line lamp voltage generator to efficiently maintain the required accuracy of the current source in the lamp voltage generator.
There is a full range of digital converters to offer.

〔発明の概要〕[Summary of the invention]

本発明は、多チヤンネルデータ収集回路用の積分方式A
Di換器において、全チャンネル共通で。
The present invention provides an integral method A for multi-channel data acquisition circuits.
Common to all channels in the Di converter.

基準となるランプ電圧の精度を理論的に解析し、ランプ
電圧発生器の電流源の必要精度全効率よく実現している
ことに特徴がある。
It is characterized by theoretically analyzing the accuracy of the reference lamp voltage and efficiently achieving the required accuracy of the current source of the lamp voltage generator.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例全第1図と第2図によシ説明す
る。第1図は、本発明による回路ブロック図、第2図は
各部の信号波形である。スイッチSOを閉じると、ラン
プ電圧■。は、0■にリセットされる。時刻t。で、ス
イッチSO會開き、スイッチ5litlの区間だけ閉じ
る。ランプ電圧yは、積分回路(OFとC)により、電
流値■1に比例した勾配で上昇する。このとき、同時に
ゲート信号(G)は u1″レベルになるので、カウン
タKtは、クロック(CLK)によ逆計数を8始する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be explained below with reference to FIGS. 1 and 2. FIG. 1 is a circuit block diagram according to the present invention, and FIG. 2 is a signal waveform of each part. When switch SO is closed, lamp voltage ■. is reset to 0■. Time t. Then, switch SO is opened and only the section of switch 5 litl is closed. The lamp voltage y rises at a slope proportional to the current value 1 by the integrating circuit (OF and C). At this time, since the gate signal (G) becomes the u1'' level at the same time, the counter Kt starts inverse counting from 8 based on the clock (CLK).

カウンタKlの出力は、ランプ電圧の値に対応したディ
ジタル値を発生する。各チャン坏ルの入力電圧V11V
2.・・・・・・ y、とランプ電圧が一致した時点で
、カウンタにの内容が、レジフタ群Lx 、 L2 、
・・・・・・、Lmにセットきれるようになっている。
The output of counter Kl generates a digital value corresponding to the value of the lamp voltage. Input voltage of each channel V11V
2. ...... When the lamp voltage matches y, the contents of the counter are changed to register groups Lx, L2,
......, it can be set to Lm.

時刻to+t1で、スイッチ81を開き、スイッチ52
it2の区間だけ閉じる。ランプ電圧yは、電流値■2
に比例した勾配で上昇する。このとき、シフト信号(S
FT)によ9%電流源1.と工2の重みの違いだけ、カ
ウンタに1全シフトダウンでせる。例えば、Ilが1/
218の重みを持ち、■2が17216の重みを持つと
@、カウンタには両者の比である1/22、即ち2ビツ
トだけシフトダウンさせる。時刻t(1+ tl + 
j2で、スイッチ82全開き、スイッチ53it3の区
間だけ閉じる。ランプ電圧yは、電流源工3に比例した
勾配で上昇する。このとき、シフト信号(S F T 
)によシ、電流源■2と■3の重みの違いだけ、カウン
タKlkシフトダウンさせる。
At time to+t1, switch 81 is opened and switch 52 is opened.
Close only the it2 section. The lamp voltage y is the current value ■2
rises at a slope proportional to At this time, the shift signal (S
FT) 9% current source1. The difference in weight between and 2 is the same as the one full shift down on the counter. For example, Il is 1/
If 2 has a weight of 218 and 2 has a weight of 17216, the counter is shifted down by 1/22, which is the ratio of the two, or 2 bits. Time t(1+ tl +
At j2, the switch 82 is fully opened and only the section of the switch 53 it3 is closed. The lamp voltage y rises at a slope proportional to the current source 3. At this time, the shift signal (S F T
), the counter Klk is shifted down by the difference in weight between current sources (2) and (3).

これらの電流源の精度の解析を第3図および第4図によ
り行なう。第3図は、第1図のランプ電圧発生器の部分
を抜き出したものである。第4図は、ランプ電圧発生器
の出力yを示したものである。スンプ電圧発生器の出力
yは、分割てれた時間t1 + tz r t3の各時
刻で、ランプ電圧はそれぞれΔyl、ΔV21 ly3
 だけバラツキを持っているものとする。各折線電圧の
精度は、それぞyyBは誤差のないフルスクール値であ
る。また、各電流源は1l=i+Δiで表わされるもの
とし、で表わすことができる。各折線の精度は各電流源
のバラツキにより決定さ扛る。各区間の折線は、各々次
のように表わすことができる。
The accuracy of these current sources will be analyzed with reference to FIGS. 3 and 4. FIG. 3 shows a portion of the lamp voltage generator of FIG. 1 extracted. FIG. 4 shows the output y of the lamp voltage generator. The output y of the dump voltage generator is at each divided time t1 + tz r t3, and the ramp voltage is Δyl, ΔV21 ly3, respectively.
It is assumed that there is a variation in As for the accuracy of each broken line voltage, yyB is a full school value without error. Further, each current source is represented by 1l=i+Δi, and can be represented by 1l=i+Δi. The accuracy of each broken line is determined by the variation in each current source. The broken lines of each section can be expressed as follows.

0 (t (t ly = i 1 t (1)tl 
(t≦tl +tz ’ Y=mli1t+YL (2
)tl+t2(t≦t1+ tz + t3 y=m2
 t1t+ )’2 (3)ただし、(1)、(2)、
(3)式は谷折線ごとに時間軸の原点をずらしていった
。また、ml 、m2は各折線の勾配の比率全示し、第
3図の電流源のブロックの個数を示す。すなわち、B1
=1個のとき、B2=m11固、B 3 = m 2 
1固でめる。
0 (t (t ly = i 1 t (1) tl
(t≦tl +tz ' Y=mli1t+YL (2
) tl+t2 (t≦t1+ tz + t3 y=m2
t1t+ )'2 (3) However, (1), (2),
In equation (3), the origin of the time axis was shifted for each valley fold line. Further, ml and m2 indicate the total ratio of the slope of each broken line, and indicate the number of blocks of the current source in FIG. 3. That is, B1
= 1, B2 = m11, B 3 = m 2
Get 1 hard.

(1)、 (2)、 (3)式よシ’/1 + y2 
+ 73をめる。
(1), (2), (3) Equation s'/1 + y2
Add +73.

Yt−い+Δi ) tl :i t1+Δitly2
=ml(i+Δi ) tz +y1= (mlt2 
+ 11 ) i+Δi(mt h + tl)y3=
 m2 (1+Δ1)t3+y2= (m213十m1
t2+tll i+Δi (m2 t3+m1t2+t
)各折線のバラツキ金求めると Δyl=Δitl Δy2 =Δi (mlt2+tt) ΔYs”Δi ([2t、、 −1−ml t2+ t
l )とな9.各折w電圧のKIjKは次のように表わ
さ扛る。
Yt-i+Δi) tl :i t1+Δitly2
=ml(i+Δi) tz +y1= (mlt2
+ 11) i+Δi(mth+tl)y3=
m2 (1+Δ1)t3+y2= (m2130m1
t2+tll i+Δi (m2 t3+m1t2+t
) To calculate the variation of each broken line, Δyl=Δitl Δy2 =Δi (mlt2+tt) ΔYs”Δi ([2t,, -1−ml t2+ t
l ) Tona 9. KIjK of the voltage w at each time is expressed as follows.

(4)、 (5)、(6)式を整理すると度となる。Rearranging equations (4), (5), and (6) gives degrees.

n2 ヒツト精度、nエ ヒツト精度たけ向上ぢせよう
とすると、 とおくことかでさ、t3=α2”l * t2−αlt
lとおくと、 α =主−v′(9) 1mIX2’1 2+11十n3 2m9 α −(10) m2×21′1 それぞれ112 ビット精[%nl ビット精度だけち
=1/16.1/2”l=1/4となる。m1=4.m
2=16として(9)、(10)式を解けば、α1=−
−改善すべき梢就17′2町、 1/2”lをH1″算
し、その後(9)、[10)式を解く回路によシ、α五
とα2すなわち% tl + t2 Htlの各時間全
計算する。この回路は、従来技術により構成することが
できる。
If we try to improve the n2 hit accuracy and the n hit accuracy, we can put it as follows, t3=α2”l * t2−αlt
Letting l, α = main - v' (9) 1mIX2'1 2 + 11 ten n3 2m9 α - (10) m2 x 21'1 each 112 bit precision [%nl bit precision only = 1/16.1/2 "l=1/4.m1=4.m
If we solve equations (9) and (10) with 2=16, we get α1=-
- 17'2 town to be improved, Calculate 1/2"l by H1", then use the circuit to solve equations (9) and [10), α5 and α2, that is, % tl + t2 Htl. Calculate the entire time. This circuit can be constructed using conventional techniques.

また、この回路の出力は%第1図のスイッチ群81、S
2.S3へ接続てれる。
Also, the output of this circuit is %Switch group 81 in FIG.
2. You can connect to S3.

〔発明の効果〕〔Effect of the invention〕

本兆明によ7しば、折線を用いたランプ電圧発生器の電
流源の必要精度全効率よく実現でき、多チャンネルデー
タ収実用の積分方式ADi換器が高速にかつ高精度に実
行できる。
According to the present invention, the required accuracy of the current source of the lamp voltage generator using a broken line can be realized with full efficiency, and the integral type ADi converter for multi-channel data collection can be implemented at high speed and with high accuracy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は不発明による多チャン坏ルデータ収集用の積分
方式AD変換器の一笑施・しUの構成図、第2図は各部
の信号波形図、第3図はランプ電圧発生器の構成図%第
4図はランプ電圧の形状図、第5図は各折線の必要精度
を得るために時間を配分する制御回路金示す図である。 代理人 弁理士 高橋明夫 第 1 図 ・りθ 不Z図 fρ 慕 3 図
Fig. 1 is a block diagram of an integral type AD converter for multi-channel data collection according to the invention, Fig. 2 is a signal waveform diagram of each part, and Fig. 3 is a block diagram of a lamp voltage generator. Figure 4 is a diagram showing the shape of the lamp voltage, and Figure 5 is a diagram showing the control circuit that allocates time to obtain the required accuracy for each broken line. Agent Patent Attorney Akio Takahashi No. 1 Fig. ri θ Fu Z Fig. fρ 3 Fig.

Claims (1)

【特許請求の範囲】 1、各チャンネルごとに並列的にデータを収集する積分
方式アナログディジタル変換器において、一定の精度に
押えら扛た複数個の定電流源とそれを順次切替えるスイ
ッチ群及び積分器とを備えた折線状のランプ電圧発生器
と、該ランプ電圧発生器からのランプ電圧と入力電圧を
比較する比較器群と、折線電圧の切替シ毎に計数の内容
を該定電流源群の重みに基づいてシフトダウンさせ、一
定のクロックで計数を行なう組数器と、該比較器群の出
力に伴なって、入力電圧に対応した時点で、計数器の内
容全セットするレジスタ群と、上記折線電圧の各折線の
必要精度に基づいて、スイッチ群の開閉時間を発生する
時間発生回路とから成シ、各入力電圧に対応したディジ
タル出力全容レジスタに必要な精度で取出すこと全特徴
とするアナログディジタル変換器。 2、特許請求の範囲第1項記載のアナログディジタル変
換器において、3本の折線の精度として、1つの折線の
精度に対し、他の2つの折線の精度k n 1 ビット
、n2 ピット精度だけ改善したいとき、スイッチ群の
開閉時間の閉時間を順次行なう時間発生回路金持ったこ
とを特徴とするアナログディジタル変換器。
[Claims] 1. In an integral type analog-to-digital converter that collects data in parallel for each channel, a plurality of constant current sources maintained at a certain precision, a group of switches for sequentially switching them, and an integral a linear lamp voltage generator having a linear lamp voltage generator, a comparator group that compares the lamp voltage from the lamp voltage generator with the input voltage, and a comparator group that compares the input voltage with the lamp voltage from the lamp voltage generator, and a comparator group that compares the input voltage with the lamp voltage from the linear lamp voltage generator, and a set of counters that shift down based on the weights of and count at a constant clock, and a set of registers that sets the entire contents of the counter at a time corresponding to the input voltage according to the output of the comparator group. It consists of a time generating circuit that generates the opening and closing times of the switch group based on the required accuracy of each broken line of the above-mentioned broken line voltage, and a digital output complete register corresponding to each input voltage is extracted with the necessary accuracy. analog-to-digital converter. 2. In the analog-to-digital converter according to claim 1, the accuracy of the three broken lines is improved by the accuracy of one broken line by k n 1 bits and n2 pits of the other two broken lines. An analog-to-digital converter characterized in that it has a time generating circuit that sequentially changes the opening and closing times of a group of switches when desired.
JP21946283A 1983-11-24 1983-11-24 Analog/digital converter Pending JPS60112326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21946283A JPS60112326A (en) 1983-11-24 1983-11-24 Analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21946283A JPS60112326A (en) 1983-11-24 1983-11-24 Analog/digital converter

Publications (1)

Publication Number Publication Date
JPS60112326A true JPS60112326A (en) 1985-06-18

Family

ID=16735803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21946283A Pending JPS60112326A (en) 1983-11-24 1983-11-24 Analog/digital converter

Country Status (1)

Country Link
JP (1) JPS60112326A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1460763A1 (en) * 2001-12-28 2004-09-22 Neuro Solution Corp. Analog-digital conversion apparatus
JP2008136043A (en) * 2006-11-29 2008-06-12 Sony Corp Solid-state imaging device and imaging device
WO2009158506A1 (en) * 2008-06-26 2009-12-30 University Of Idaho Analog-to-digital converter for image sensors
JP2011015294A (en) * 2009-07-03 2011-01-20 Nippon Telegr & Teleph Corp <Ntt> Voltage controlled delay generator cell, voltage controlled delay generator and analog/digital converter

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1460763A1 (en) * 2001-12-28 2004-09-22 Neuro Solution Corp. Analog-digital conversion apparatus
EP1460763A4 (en) * 2001-12-28 2005-04-20 Neuro Solution Corp Analog-digital conversion apparatus
JP2008136043A (en) * 2006-11-29 2008-06-12 Sony Corp Solid-state imaging device and imaging device
WO2009158506A1 (en) * 2008-06-26 2009-12-30 University Of Idaho Analog-to-digital converter for image sensors
US8724001B2 (en) 2008-06-26 2014-05-13 University Of Idaho Analog-to-digital converter using a ramp generator
JP2011015294A (en) * 2009-07-03 2011-01-20 Nippon Telegr & Teleph Corp <Ntt> Voltage controlled delay generator cell, voltage controlled delay generator and analog/digital converter

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