JP2011015294A - Voltage controlled delay generator cell, voltage controlled delay generator and analog/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog/digital (A/D) converter that achieves wideband and high-speed sampling rate while fixing an input analog voltage range.SOLUTION: Each of voltage controlled delay generator cells VCDG_0 to 3 outputs, as a stop pulse signal "stop", a result of comparing an input analog voltage with a ramp voltage generated by a capacitor with a current supplied from a plurality of (e.g., four) constant current sources via a current switch. The voltage controlled delay generator cells VCDG_0 to 3 are disposed in parallel as many as the number of the constant current sources. After discharging ramp voltage under control of a control circuit CTL, first of all, the different number of current switches are turned on by the VCDG_0 to 3, and further, all current switches of the VCDG_0 to 3 are turned on when a start pulse signal "start" rises, thereby generating the ramp voltage in each of capacitors. Output delay times of stop pulse signals "stop" 0 to "stop" 3 of the VCDG_0 to 3 are converted into digital data by temporal digital converter TDC_0 to 3 and converted into a predetermined code by an encoder ENC.

Description

  The present invention relates to a voltage-controlled delay generator cell, a voltage-controlled delay generator, and an analog / digital converter, and in particular, by arbitrarily changing the delay time of an input pulse signal according to the voltage value of the input analog voltage. The present invention relates to a voltage-controlled delay generator cell for output, a voltage-controlled delay generator having the voltage-controlled delay generator cell as a component, and an analog / digital converter using the voltage-controlled delay generator. In particular, according to the present invention, an analog-to-digital converter having a low power and a high sampling rate can be obtained as an analog-to-digital converter for converting a transmitted analog voltage signal into a digital signal in an optical communication transceiver.

  Conventionally, analog-to-digital converter ADCs that have been miniaturized and improved in performance by applying miniaturized processes have been realized. However, with further miniaturization of processes, the withstand voltage has decreased in recent years. It has become difficult to ensure the resolution in the voltage direction. For this reason, information related to the input analog voltage is once converted into time information by a voltage controlled delay generator VCDG (Voltage Controlled Delay Generator), and then the time information is converted into a digital signal by a time digital converter TDC (Time to Digital Converter). A method of converting to is proposed. Since the subsequent time digital converter TDC for converting time information into digital data can be realized by a digital circuit, the use of a miniaturized process is advantageous in reducing power consumption.

FIG. 17 is a circuit diagram showing a circuit configuration of a conventional voltage controlled delay generator VCDG described in “A 9b 14 μW 0.06 mm ² PPM ADC in 90 nm Digital CMOS” (ISSCC 2009) by Shahrzad Naraghi et al. is there. The voltage controlled delay generator VCDG of FIG. 17 is connected in series with a current source I (constant current source) for supplying a current having a predetermined current value, and the current source I is turned on. The current switch S that is turned off, the capacitor C that is connected in series with the current switch S and generates a ramp voltage (capacitance voltage) corresponding to the current value of the current from the current source I, and leaks the charge accumulated in the capacitor C Then, the leak switch LS for discharging the generated ramp voltage ramp and the ramp voltage ramp generated by the capacitor C and the analog voltage Vin input from the outside are compared, and the former ramp voltage exceeds the analog voltage Vin. The voltage comparator CMP outputs a time point as a delay time signal (digital signal) indicating a delay time.

  FIG. 18 is a waveform diagram showing the operation of the conventional voltage controlled delay generator VCDG of FIG. As described above, the voltage controlled delay generator VCDG has a function of generating a pulse (stop pulse signal stop) that rises after an arbitrary delay time Tout from the rising point of the input pulse (start pulse signal start). In addition, the delay time Tout has a function that can be changed by an analog voltage Vin input from the outside.

First, in the initial state, the current switch S is turned off and the leak switch LS is turned on to leak the charge in the capacitor C. Next, in synchronization with the rising edge of the start pulse signal start, the current switch S is turned on and the leak switch LS is turned off, whereby the charge from the current source I begins to be charged into the capacitor C, and the ramp voltage ramp, that is, the capacitance voltage ramp Occurs. When the constant current value of the current source I is I, the capacitance of the capacitor C is C, and the rising time of the start pulse signal start is t ₀ , the capacitance voltage ramp of the capacitor C at time t is
ramp = I · (t−t ₀ ) / C
It is expressed as The voltage comparator CMP compares the magnitude of the capacitance voltage ramp, that is, the ramp voltage ramp, with the analog voltage Vin input from the outside. When the capacitance voltage ramp exceeds the analog voltage Vin, the voltage comparator ramp rises (stop pulse signal). stop).

The delay time Tout from the rise of the start pulse signal start to the rise of the stop pulse signal stop is
Tout = t−t ₀ = Vin · C / I
Therefore, it can be seen that this circuit functions as a voltage controlled delay generator VCDG that outputs a digital signal (delay time signal, that is, stop pulse signal stop) having a delay time Tout proportional to the input analog voltage Vin. .

Here, the full scale FS (Full Scale) that the capacitance voltage ramp can take is limited by the power supply voltage and the voltage drop of the current source. Further, the maximum value tmax of the delay time Tout that can be generated is:
tmax = FS · C / I
It is represented by

  In actual implementation, since the operation delay time and wiring delay time of the current switch S, the leak switch LS, and the voltage comparator CMP are further added to the maximum delay time value tmax, the maximum delay time value tmax is Therefore, a certain error is included in the above formula. However, in the case of application to a general delay generator including application to an analog / digital converter ADC, the accuracy of the relative delay time when the analog voltage Vin is changed is required. Information about absolute delay times is rarely required.

  FIG. 19 is a block configuration diagram showing a block configuration of an analog / digital converter ADC using a conventional voltage controlled delay generator VCDG. In the block configuration of FIG. 19, the input analog voltage Vin is converted into a signal on the time axis (time interval from the rising point of the start pulse signal start to the rising point of the stop pulse signal stop), and further on the time axis. The signal is digitized. A circuit for digitizing a signal on the time axis is realized by a time digital converter TDC. If necessary, encode the digitized signal as described in Haruo Kobayashi of Non-Patent Document 2, “New Trends in Analog Technology, Time Resolution Circuits and TDC (Part 1)” (Nikkei Electronics, 2009.4.6). An output circuit for performing digital signal processing is added.

  FIG. 20 is a circuit diagram showing a circuit configuration of a conventional time digital converter TDC. The time digital converter TDC shown in FIG. 20 has a delay buffer string composed of a plurality of delay buffers td to which a start pulse signal start is input, and outputs of the delay buffers td are input to respective D inputs, and each delay buffer td A D flip-flop D-FF sequence composed of a plurality of D flip-flops D-FF triggered by a stop pulse signal stop from and a digital data sequence output from each D flip-flop D-FF into digital data of a predetermined code And an encoder ENC for conversion.

  FIG. 21 is a waveform diagram showing the operation of the conventional time digital converter TDC of FIG. The start pulse signal start is input to the delay buffer td train with high time resolution, and the D flip-flop D-FF train latches the output of each delay buffer td at the rising edge of the stop pulse signal stop. The latched data becomes a thermometer code proportional to the time difference from the rising point of the start pulse signal start to the rising point of the stop pulse signal stop. The encoder ENC converts the thermometer code into, for example, binary code digital data and outputs it as digital data Dout.

  Since the time digital converter TDC is configured based on a digital circuit, it is possible to reduce power consumption and area by using a miniaturized process. Further, if the power supply voltage is lowered due to the progress of miniaturization, it becomes difficult to ensure the resolution in the voltage axis direction. However, the analog / digital converter ADC using the voltage control delay generator VCDG and the time digital converter TDC is used. Is advantageous in that it is easy to ensure the resolution by replacing the processing in the voltage axis direction with the processing in the time axis direction.

Shahrzad Naraghi et al., “A 9b 14μW 0.06mm2 PPM ADC in 90nm Digital CMOS” ISSCC 2009, p.168 Haruo Kobayashi, “New trends in analog technology, Time-resolution circuit and TDC (Part 1)” Nikkei Electronics, 2009.4.6, p. 88

  As described above, the conventional voltage controlled delay generator VCDG includes a current source I, a capacitor C that is charged by the current source I to generate a ramp voltage (capacitance voltage), and a start pulse signal start that is input from the outside. A current switch S for connecting the current source I and the capacitor C, a leak switch LS for leaking the charge of the capacitor C by a leak signal inputted from the outside and discharging a ramp voltage (capacitance voltage), and time information on the time axis The analog voltage signal Vin to be converted is compared with the ramp voltage (capacitance voltage) generated by the capacitor C, and when the latter ramp voltage exceeds the voltage value of the former analog voltage signal Vin, the delay time indicating the delay time A voltage comparator CMP that outputs a stop pulse signal stop as a signal is provided.

  At this time, the time width of the delay time from when the start pulse signal start rises until the stop pulse signal stop is output corresponds to the magnitude of the voltage value of the analog voltage signal Vin to be converted into time information on the time axis. However, in the case of application to the analog / digital converter ADC, if the possible time width is large, a sampling error is caused.

  That is, in the conventional voltage controlled delay generator VCDG, the capacitance voltage ramp changes over the voltage range FS that the input analog voltage Vin can take, and the comparison result between the analog voltage Vin and the ramp voltage ramp, that is, the capacitance voltage ramp. There is a possibility that the stop pulse signal stop is generated over the time width of the maximum value tmax of the delay time Tout obtained as follows. On the other hand, when the conventional voltage controlled delay generator VCDG is applied to the analog / digital converter ADC, the input analog voltage Vin changes with time within the voltage range FS, so that the time at which the stop pulse signal stop is generated. Changes over the maximum value tmax of the delay time Tout by the analog voltage Vin. As a result, the sampling time becomes an unequal time interval (an unequal interval having a deviation of the maximum value tmax of the delay time Tout), which causes a sampling error.

  In order to reduce the sampling error, processing such as re-sampling or complementation at equal time intervals is required, resulting in an increase in the amount of calculation and generation of an error. The phenomenon that the sampling times become unequal intervals becomes more prominent as the input analog voltage Vin becomes higher.

  The present invention has been made in view of such circumstances, and an object of the present invention is to make the voltage control delay generator VCDG in a voltage interleave configuration or to make the voltage control delay generator VCDG in the time axis direction. With the folded configuration, the voltage controlled delay generator cell and the voltage controlled delay generator VCDG in which the maximum value tmax of the delay time is reduced while keeping the voltage range FS that the input analog voltage Vin can take are constant. Is to provide. It is another object of the present invention to provide an analog / digital converter that reduces the sampling time shift, thereby increasing the sampling rate and increasing the bandwidth of the analog input signal.

  The present invention comprises the following technical means in order to solve the above-mentioned problems.

  A first technical means includes: a current source that supplies a current of a predetermined current value in a voltage controlled delay generator cell that generates a digital signal having a delay time corresponding to a voltage value of an input analog voltage signal; A current switch connected in series to the current source to turn on and off current from the current source, and a lamp voltage connected to the current switch in series to generate a lamp voltage corresponding to the current value of the current from the current source A capacitor, a voltage comparator for outputting a result of comparing the voltage value of the ramp voltage generated by the capacitor and the analog voltage signal as a delay time signal indicating the delay time, and the lamp charged in the capacitor A voltage controlled delay generator cell comprising at least a leakage switch for discharging a voltage, wherein the current source and the current switch connected in series And pitch, characterized by comprising connecting a plurality parallel.

  A second technical means includes the same number of voltage controlled delay generator cells as the number of the current sources in parallel with the number of voltage control delay generator cells described in the first technical means, and each voltage control based on a clock signal supplied from the outside. A voltage control delay generator having a voltage interleave configuration including a control circuit for outputting a control signal for controlling a delay generator cell, wherein the voltage control is performed by a leak signal output from the control circuit as one of the control signals. After the discharge of the ramp voltage charged in the capacitor of each delay generator cell, a different number of voltage control delay generator cells depending on the control signal output as one of the control signals from the control circuit The current switch is turned on, and the voltage controlled delay generator cell is turned on according to the current from a different number of current sources in each of the voltage controlled delay generator cells. The capacitor of each voltage controlled delay generator cell is charged with a ramp voltage, and then the control signal is changed at the rising edge of the start pulse signal output as one of the control signals from the control circuit, For all voltage controlled delay generator cells, turn on all the current switches to charge the capacitors of each of the voltage controlled delay generator cells with the ramp voltage according to the current from all the current sources, The delay time signal, which is a comparison result between the ramp voltage generated by the capacitor and the voltage value of the analog voltage signal, is output as a stop pulse signal from the voltage comparator of each voltage controlled delay generator cell. And

  According to a third technical means, in the voltage controlled delay generator according to the second technical means, when the number of the voltage controlled delay generator cells is N, the capacitors of the respective voltage controlled delay generator cells After the discharge of the lamp voltage charged in the control circuit, the number of the current switches of the voltage control delay generator cells to be turned on by the control signal output from the control circuit is 0, 1, 2, ..., (N-1).

  According to a fourth technical means, in the voltage controlled delay generator according to the second or third technical means, the voltage constituting the voltage controlled delay generator after the start pulse signal is output from the control circuit. The maximum current delay time required until the stop pulse signal is output from each control delay generator cell, and the current having one clock period in parallel in the voltage control delay generator cell It is characterized by being controlled to a value divided by the number of sources.

  According to a fifth technical means, in the voltage controlled delay generator according to any one of the second to fourth technical means, after the start pulse signal is output from the control circuit, each voltage controlled delay generator cell A rise detection circuit that detects that the stop pulse signal is output from any one of the voltage controlled delay generator cells and outputs the stop pulse signal as a stop holding pulse signal. It is characterized by comprising.

  According to a sixth technical means, in the voltage controlled delay generator according to the fifth technical means, the rising edge detection circuit performs an exclusive OR of the stop pulse signals output from the respective voltage controlled delay generator cells. A first exclusive OR gate that outputs the operation result as a parity signal; a D flip-flop that holds the value of the parity signal at the rising edge of the start pulse signal and outputs a negative logic signal as a parity start signal; A second exclusive OR gate that performs an exclusive OR operation on the parity signal output from the first exclusive OR gate and the parity start signal output from the D flip-flop. It is characterized by including.

  A seventh technical means comprises the voltage controlled delay generator according to any one of the second to fourth technical means in a plurality of stages in parallel, and each of the voltage controlled delay generators at each stage is set in a predetermined time. It is characterized by being operated by being shifted by an interval.

  According to an eighth technical means, in the voltage controlled delay generator according to the seventh technical means, the time interval for operating each of the voltage controlled delay generators at each stage is calculated, and the start pulse signal is received from the control circuit. After the output, the maximum delay time required until the stop pulse signal is output from the voltage controlled delay generator cell is set.

  According to a ninth technical means, in the voltage controlled delay generator according to the eighth technical means, the number of the current sources in the voltage controlled delay generator cell constituting each of the voltage controlled delay generators in each stage. The number of stages of the voltage controlled delay generators arranged in parallel is a value obtained by dividing the time of two periods of the clock signal by the maximum value of the delay time.

  According to a tenth technical means, in the analog-digital converter for converting to digital data corresponding to the voltage value of the inputted analog voltage signal and outputting the digital data, the voltage according to any one of the second to fourth technical means. Output delay until the stop pulse signal is output from each of the voltage control delay generator cells constituting the voltage control delay generator after the start pulse signal is output from the control delay generator and the control circuit A time digital converter for converting each time into digital data and outputting; and an encoder for converting the digital data output from each time digital converter into digital data of a predetermined code and outputting the digital data. It is characterized by being.

  The eleventh technical means is the analog-digital converter for converting to digital data corresponding to the voltage value of the input analog voltage signal and outputting the digital data, and generating the voltage control delay according to the fifth or sixth technical means. And after the start pulse signal is output from the control circuit, the output delay time until the stop holding pulse signal is output from the rising detection circuit constituting the voltage controlled delay generator is converted into digital data. A time digital converter that outputs the digital data, and an encoder that converts the digital data output from the time digital converter into digital data of a predetermined code and outputs the digital data.

  According to a twelfth technical means, in the analog-digital converter according to the eleventh technical means, the analog voltage signal is inputted, and the voltage value of the analog voltage signal is set to a predetermined number of upper bit positions. The encoder further comprises a coarse analog-to-digital converter for converting into digital data, and the encoder converts the lower-bit digital data of the remaining number of digits excluding the digital data at the upper bit position to be converted by the coarse analog-to-digital converter. The digital data of the same code as the digital data of the upper bit position output from the coarse analog-to-digital converter is converted and output.

  A thirteenth technical means is the analog-to-digital converter according to the twelfth technical means, wherein the coarse analog-to-digital converter outputs the digital data at the upper bit position as a gray code or a binary code. It is characterized by.

  Fourteenth technical means is the analog / digital converter according to the eleventh technical means, wherein the start pulse signal output from the control circuit and each voltage control delay generator constituting the voltage control delay generator are provided. The stop pulse signal output from the measuring cell is input, the digital data of the upper bit position having a predetermined number of digits with respect to the voltage value of the analog voltage signal is extracted, and the digital data of the predetermined code The encoder further comprises a second encoder for converting the digital data of the lower bits of the remaining number of digits excluding the digital data of the upper bit positions converted by the second encoder to the second encoder. Output to the digital data of the same code as the digital data of the upper bit position And outputs to conversion.

  According to a fifteenth technical means, in the analog-digital converter for converting to digital data corresponding to the voltage value of the input analog voltage signal and outputting the digital data, the voltage according to any one of the seventh to ninth technical means. After the control pulse generator outputs the start pulse signal from the control circuit by shifting the time interval by a predetermined time interval for each of the control delay generator and each voltage control delay generator of each stage, the voltage control delay generation of each stage A time digital converter for each stage for converting each output delay time of the stop pulse signal output from each of the voltage controlled delay generator cells constituting the converter into digital data and outputting the digital data, and the time for each stage Of the digital converters, each of the time digital converters at the stage where the start pulse signal is output from the control circuit. Characterized in that it comprises an encoder for digital data are converted into predetermined codes digital data output to be al output, the.

  The sixteenth technical means is an analog-digital converter for converting to digital data corresponding to the voltage value of the input analog voltage signal and outputting the digital data, and the analog means according to any one of the eleventh to fourteenth technical means. A digital converter is provided in parallel in a plurality of stages, and after outputting the start pulse signal from the control circuit, the stop pulse signal from the voltage controlled delay generator cell constituting each of the analog / digital converters in each stage The time interval for inputting the start pulse signal to the analog-to-digital converter in each stage is shifted by the maximum value of the delay time required until the signal is output, and the encoder The digital data output from the analog / digital converter at the stage input from the control circuit. And outputs converted into digital data of a predetermined encoding data.

  The seventeenth technical means is the analog-digital converter according to any one of the tenth to sixteenth technical means, wherein the encoder and / or the second encoder respectively receives input digital data, A thermometer code is converted into gray code or binary code digital data and output.

  An eighteenth technical means further comprises a sample and hold circuit for sampling and holding an input analog voltage signal in the analog-digital converter according to any one of the tenth to seventeenth technical means, The hold circuit samples and holds the analog voltage signal at a timing when the start pulse signal rises.

  According to the voltage controlled delay generator cell, voltage controlled delay generator, and analog / digital converter according to the present invention, the following effects can be obtained.

  The voltage controlled delay generator cell and the voltage controlled delay generator according to the present invention comprise a plurality of voltage controlled delay generator cells each having a plurality of current sources (constant current sources) and a plurality of current switches, and voltage interleaving. By adopting a configuration, or by using a time folding configuration, the delay time can be reduced as compared with the conventional technology while keeping the voltage range (full scale) that can be taken by an analog voltage input from the outside constant. The maximum value can be greatly reduced.

  Further, in the analog / digital converter according to the present invention, it is possible to reduce the difference in sampling time, and it is possible to increase the sampling rate and to widen the analog input signal.

It is a block block diagram which shows an example of the block configuration of the voltage control delay generator which concerns on this invention. FIG. 2 is a circuit diagram showing an implementation example of a basic cell constituting the voltage controlled delay generator cell of FIG. 1, that is, the voltage controlled delay generator. 3 is a time chart showing an example of the operation of the voltage controlled delay generator having the voltage interleave configuration shown in FIG. 1. 3 is a table showing a setting example of a control signal which is one of control signals to the voltage controlled delay generator of FIG. 1. FIG. 2 is a characteristic diagram showing voltage-time conversion characteristics of the voltage controlled delay generator having the voltage interleave configuration of FIG. 1. It is a block block diagram which shows an example of the block configuration of the analog / digital converter using the voltage control delay generator which concerns on this invention. It is a block block diagram which shows the other example different from FIG. 1 of the block configuration of the voltage control delay generator which concerns on this invention. It is a time chart which shows an example of operation | movement of the voltage control delay generator of the time folding structure shown in FIG. FIG. 8 is a circuit diagram showing an example of a circuit configuration of a rising edge detection circuit in the voltage-controlled delay generator having the time folding configuration of FIG. 7. FIG. 8 is a characteristic diagram illustrating a voltage-time conversion characteristic of the voltage-controlled delay generator having the time folding configuration of FIG. 7. It is a block block diagram which shows the example different from FIG. 6 of the block structure of the analog / digital converter using the voltage control delay generator based on this invention. FIG. 12 is a block configuration diagram showing an example different from FIGS. 6 and 11 of the block configuration of the analog / digital converter using the voltage controlled delay generator according to the present invention. It is a block block diagram which shows the other example different from FIG. 1, FIG. 7 of the block configuration of the voltage control delay generator which concerns on this invention. It is a time chart which shows an example of operation | movement of the voltage control delay generator which made the voltage interleave structure (x4) shown in FIG. 13 the time interleave structure (x8). It is a block block diagram which shows the example different from FIG.6, FIG.11, FIG.12 of the block structure of the analog / digital converter using the voltage control delay generator based on this invention. FIG. 16 is a block configuration diagram showing an example different from FIGS. 6, 11, 12, and 15 of a block configuration of an analog / digital converter using a voltage controlled delay generator according to the present invention. It is a circuit diagram which shows the circuit structure of the conventional voltage control delay generator. FIG. 18 is a waveform diagram showing an operation of the conventional voltage controlled delay generator of FIG. 17. It is a block block diagram which shows the block structure of the analog / digital converter using the conventional voltage control delay generator. It is a circuit diagram which shows the circuit structure of the conventional time digital converter. It is a wave form diagram which shows the operation | movement of the conventional time digital converter of FIG.

  Hereinafter, preferred embodiments of a voltage controlled delay generator cell, a voltage controlled delay generator, and an analog / digital converter according to the present invention will be described in detail with reference to the drawings.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention relates to a time-resolved circuit. In particular, the configuration of a voltage-controlled delay generator VCDG for converting a change in the voltage axis into a change in the time axis is applied to an analog / digital converter ADC. The main feature is the configuration of the voltage controlled delay generator VCDG that can reduce the sampling error.

  The voltage controlled delay generator VCDG according to the present invention includes a basic cell (voltage controlled delay generator) of a voltage controlled delay generator VCDG that includes a plurality of current sources I (constant current sources) and a plurality of current switches S. Voltage VCDG_i (i: any integer)), and a voltage controlled delay generator VCDG having a voltage interleaved configuration or a voltage having a time folding configuration using a plurality of such basic cells (voltage controlled delay generator cells VCDG_i) A control delay generator VCDG is realized.

  In the voltage controlled delay generator VCDG according to the present invention, first, for each voltage controlled delay generator cell VCDG_i, an initialization leak signal leak is inputted and the ramp voltage ramp (capacitance voltage ramp) of each capacitor C is inputted. After the discharge, each voltage controlled delay generator cell VCDG_i is supplied with a current having a different current value to each capacitor C such that the number of current switches S which are turned on by the control signal ctrl from the control circuit CTL is different. By doing so, the precharge of each capacitor C is started.

  Thereafter, when the start pulse signal start is output from the control circuit CTL, the control signal ctrl is changed to turn on all the current switches S in each voltage controlled delay generator cell VCDG_i, and The charge current is increased at the same rate so that the ramp voltage ramp (capacitance voltage ramp) generated at each capacitor C increases rapidly according to the number of current sources I provided.

  Here, the analog voltage signal Vin input from the outside is compared with the ramp voltage ramp (capacitance voltage ramp) generated by the capacitor C, and the latter ramp voltage ramp (capacitance voltage ramp) is compared to the former analog voltage signal Vin. When the voltage value exceeds a stop pulse signal stop from the corresponding voltage comparator CMP.

  Thus, by using a plurality of voltage controlled delay generator cells VCDG_i having a plurality of current sources I (constant current sources), the delay time required until the stop pulse signal stop is output is generated in the capacitor C. Delay time from the time when the start pulse signal start is output to the time when the stop pulse signal stop is output is shortened from the voltage control delay generator VCDG according to the prior art by the amount that the ramp voltage ramp increases. The time width of is reduced. This makes it possible to prevent sampling errors when applied to the analog / digital converter ADC.

  Further, the voltage control delay generator VCDG having the voltage interleave configuration as described above or the voltage control delay generator VCDG having the time folding configuration is arranged in parallel in multiple stages, and the operation is continuously repeated at different times. Configuration is also possible.

  Further, in the present invention, by using the voltage-controlled delay generator VCDG having a shortened time width and the time digital converter TDC that converts information on the time axis into digital data as described above, the deviation of the sampling time is reduced. Thus, an analog / digital converter ADC that can increase the sampling rate is realized.

  Furthermore, in the present invention, the voltage control delay generator VCDG having a voltage interleave configuration or the voltage control delay generator VCDG having a time folding configuration is arranged in parallel in multiple stages, so that each capacitor C is pre-configured. A configuration of the analog / digital converter ADC that can improve the decrease in the sampling rate of the analog / digital converter ADC by the time required for charging is also possible.

  By applying the above technique, the delay time from the output of the start pulse signal start to the output of the stop pulse signal stop while keeping the voltage range FS that the input analog voltage Vin can take is constant. A voltage controlled delay generator VCDG in which the maximum value tmax is reduced can be realized. Further, by reducing the sampling time shift, it is possible to realize an analog-to-digital converter ADC in which the sampling rate is increased and the analog input signal is widened.

  Hereinafter, embodiments of the voltage controlled delay generator cell VCDG_i, the voltage controlled delay generator VCDG, and the analog / digital converter ADC according to the present invention will be described in detail.

(First embodiment)
First, a voltage-controlled delay generator VCDG having a voltage interleave configuration will be described as a first embodiment of the voltage-controlled delay generator cell VCDG_i, the voltage-controlled delay generator VCDG, and the analog / digital converter ADC according to the present invention.

  FIG. 1 is a block diagram showing an example of a block configuration of a voltage controlled delay generator VCDG according to the present invention, showing a configuration example of a voltage controlled delay generator VCDG having a voltage interleave configuration. The voltage control delay generator VCDG shown in FIG. 1 is a circuit for generating a digital signal having a delay time corresponding to the voltage value of an input analog voltage signal, and a plurality of (four in the case of FIG. 1) voltage control. The operation of each voltage controlled delay generator cell VCDG_i based on the delay generator cell VCDG_i (i: any integer, i = 0, 1, 2, 3 in the case of FIG. 1) and the clock signal clk supplied from the outside. And a control circuit CTL that outputs a control signal for controlling the voltage control delay generator cells VCDG_i, which are connected in parallel.

  FIG. 2 is a circuit diagram showing an implementation example of the basic cell constituting the voltage controlled delay generator cell VCDG_i, that is, the voltage controlled delay generator VCDG of FIG. The voltage controlled delay generator cell VCDG_i, that is, the basic cell of the voltage controlled delay generator VCDG has a plurality (four in FIG. 2) of current sources I (constant current sources) each supplying a current of a predetermined current value, A plurality of (four in FIG. 2) current switches S that are connected in series with each of the current sources I and turn on / off the current from each current source I, and a plurality of current switches S connected in parallel. Capacitor voltage ramp corresponding to the current value of the current from the current source I, that is, a capacitor C that generates a ramp voltage ramp, a leak switch that leaks the charge accumulated in the capacitor C and discharges the generated ramp voltage ramp The comparison result of the voltage value between the ramp voltage ramp generated by LS and the capacitor C and the analog voltage Vin input from the outside is expressed as a voltage value of the analog voltage Vin. Delay time signal indicating a delay time corresponding and a voltage comparator CMP outputs a (digital signal).

  Here, the number of installed voltage controlled delay generator cells VCDG_i is the same as the number of installed current sources I and current switches S in each voltage controlled delay generator cell VCDG_i.

FIG. 3 is a time chart showing an example of the operation of the voltage controlled delay generator VCDG having the voltage interleave configuration shown in FIG. As shown in the time chart of FIG. 3, the voltage-controlled delay generator VCDG having the voltage interleave configuration of FIG. 1 has a pulse (stop pulse signal stop) that rises after an arbitrary delay time Tout from the input pulse (start pulse signal start). ) And the delay time Tout can be changed by an analog voltage Vin input from the outside. FIG. 3 shows a pulse waveform of the stop pulse signal stop2 output from the third voltage controlled delay generator cell VCDG_2 constituting the voltage controlled delay generator VCDG of FIG. In the initial state (before time t ₀ ), for the four voltage controlled delay generator cells VCDG_ 0 to VCDG_ 3 in FIG. 1, first, a control signal ctrl, which is one of the control signals from the control circuit CTL, In response to the leak signal leak, the current switch S is turned off and the leak switch LS is turned on to leak the charge in the capacitor C and discharge the ramp voltage ramp.

FIG. 4 is a table showing a setting example of the control signal ctrl which is one of the control signals to the voltage controlled delay generator VCDG of FIG. 1, and each voltage controlled delay generator is set according to the elapsed time from the initial state. An example of how each control signal ctrl input to the cell VCDG_i (i = 0, 1, 2, 3) is changed is shown. In FIG. 4, until the control is started (t <t ₀ ), the control signals ctrl output to each voltage controlled delay generator cell VCDG_i are all “0”. Thereafter, at the time t ₀ when the control is started in synchronization with the rising edge of the clock signal clk, the leak switch LS is turned off, and each control signal ctrl output to each voltage controlled delay generator cell VCDG_i is sent to the first voltage controlled delay. The generator cell VCDG_0 is set to “0”, the second voltage controlled delay generator cell VCDG_1 is set to “1”, the third voltage controlled delay generator cell VCDG_2 is set to “2”, and the fourth voltage controlled. The delay generator cell VCDG_3 is set to “3”, and each voltage control delay generator cell VCDG_i (i = 0, 1, 2, 3) is turned on by turning on a different number of current switches S. Currents from different numbers of current sources I are caused to flow through the capacitors C in each of the delay generator cells VCDG_i.

  That is, for example, when there are N (N: integer) voltage controlled delay generator cells VCDG_i (i = 0, 1, 2,..., (N−1)), each voltage controlled delay generator cell VCDG_i The number of current switches I and current switches S is N, and the number of current switches S in each voltage controlled delay generator cell VCDG_i that is turned on by the control signal ctrl is 0, 1, 2,. (N-1). In the case of FIG. 1 with four voltage controlled delay generator cells VCDG_i (N = 4), the first voltage controlled delay generator cell VCDG_0 turns off all four current switches S and the second voltage controlled delay The generator cell VCDG_1 turns on one of the four current switches S and turns off the remaining three current switches S. The third voltage controlled delay generator cell VCDG_2 turns on two of the four current switches, turns off the remaining two current switches, and the fourth voltage controlled delay generator cell VCDG_3 Three of the four current switches are turned on, and the remaining one current switch is turned off.

As a result, the capacitors C of the voltage controlled delay generator cells VCDG_0 to VCDG_3 are charged with electric charges from the current sources I except for the first voltage controlled delay generator cell VCDG_0 in which all the current switches S are off. As shown in FIG. 3, the ramp voltage ramp generated by the capacitor C, that is, the capacitance voltage ramp, becomes ramp waves having different slopes at t ₀ ≦ t <t ₂ . Assuming that the constant current value of the current source I is I and the capacitance of the capacitor C is C, the capacitance voltage ramp at the time t at t ₀ ≦ t <t ₂ is as follows in each of the voltage controlled delay generator cells VCDG_0 to VCDG_3. Can be expressed as:

That is,
In the first voltage controlled delay generator cell VCDG_0,
ramp_0 = 0
In the second voltage controlled delay generator cell VCDG_1,
ramp_1 = I · (t−t ₀ ) / C
In the third voltage controlled delay generator cell VCDG_2,
ramp_2 = 2 · I · (t−t ₀ ) / C
In the fourth voltage controlled delay generator cell VCDG_3,
ramp — 3 = 3 · I · (t−t ₀ ) / C
In FIG. 3, it is assumed that there is a fifth voltage controlled delay generator cell VCDG_4 that does not actually exist, but for reference, the control signal ctrl is set to “4” to turn on all four current switches S. In this case, the capacitance voltage ramp is indicated by a broken line.

When the time interval from time t ₀ to time t ₂ (that is, the period of the clock signal clk) is T (clock period), the capacitance voltage ramp at time t = t ₂ is the voltage controlled delay generator cells VCDG_0 to VCDG_3. Can be expressed as: Here, time t = t ₂ is the time when the start pulse signal start, which is the start point for converting the voltage value of the analog voltage Vin into time information on the time axis, rises.

In the first voltage controlled delay generator cell VCDG_0,
ramp_0 = 0
In the second voltage controlled delay generator cell VCDG_1,
ramp_1 = IT / T / C
In the third voltage controlled delay generator cell VCDG_2,
ramp_2 = 2 · I · T / C
In the fourth voltage controlled delay generator cell VCDG_3,
ramp_3 = 3 · I · T / C
Next, as shown in FIG. 4, at time _{t 2} is the rise time of the start pulse signal start, all the control signals ctrl for the voltage controlled delay generator cell VCDG_0~VCDG_3 "4" is set to. That is, all four current switches S are turned on for all four voltage controlled delay generator cells VCDG_i (i = 0, 1, 2, 3) of the voltage controlled delay generator cells VCDG_0 to VCDG_3.

As a result, the capacitor C of each voltage controlled delay generator cell VCDG_0 to VCDG_3 starts to be charged from the four current sources I at the same rate, and the ramp voltage ramp, that is, the capacitance voltage ramp generated by the capacitor C is When t ₂ ≦ t <t ₃ , as shown in FIG. 3, the ramp wave has a steep slope with the same slope according to the current values of the currents from all four current sources I. . That is, the capacitance voltage ramp at the time t in the range of t ₂ ≦ t <t ₃ can be expressed as follows in each of the voltage controlled delay generator cells VCDG_0 to VCDG_3.

That is,
In the first voltage controlled delay generator cell VCDG_0,
ramp — 0 = 4 · I · (t−t ₂ ) / C
In the second voltage controlled delay generator cell VCDG_1,
ramp_1 = 4 · I · (t−t ₂ ) / C + I · T / C
In the third voltage controlled delay generator cell VCDG_2,
ramp_2 = 4 · I · (t−t ₂ ) / C + 2 · I · T / C
In the fourth voltage controlled delay generator cell VCDG_3,
ramp_3 = 4 · I · (t−t ₂ ) / C + 3 · I · T / C
Although not actually shown in FIG. 3, for reference, a fifth voltage control delay that turns on all four current switches S by setting the control signal ctrl to “4” at t ₀ ≦ t <t ₂ . The capacity voltage ramp at t ₂ ≦ t <t ₃ when it is assumed that the generator cell VCDG — 4 exists is also indicated by a broken line.

  The voltage comparator CMP in each of the voltage controlled delay generator cells VCDG_0 to VCDG_3 includes a ramp voltage ramp_0 to ramp_3 of each voltage controlled delay generator cell VCDG_0 to VCDG_3, that is, a capacitance voltage ramp_0 to ramp_3, and an analog voltage input from the outside. When the magnitude of the voltage value with Vin (common to each voltage controlled delay generator cell VCDG_0 to VCDG_3) is compared and the capacitance voltage ramp exceeds the voltage value of the analog voltage Vin, the delay time according to the voltage value of the analog voltage Vin A pulse (stop pulse signal stop) rises as a delay time signal (that is, a digital signal indicating voltage information as time information on the time axis).

The delay time Tout from the rise of the start pulse signal start at time t = t ₂ to the rise of the stop pulse signals stop0 to stop3 in each of the voltage controlled delay generator cells VCDG_0 to VCDG_3 is the analog voltage Vin. The delay time according to the voltage value is expressed by the following equations (1) to (4).

The delay time Tout_0 until the stop pulse signal stop0 rises in the first voltage controlled delay generator cell VCDG_0 is:
Tout — 0 = t−t ₂ = Vin · C / (4 · I) (1)
The delay time Tout_1 until the stop pulse signal stop1 rises in the second voltage controlled delay generator cell VCDG_1 is:
Tout_1 = t−t ₂ = (Vin−I · T / C) · C / (4 · I) (2)
The delay time Tout_2 until the stop pulse signal stop2 rises in the third voltage controlled delay generator cell VCDG_2 is:
Tout_2 = t−t ₂ = (Vin−2 · I · T / C) · C / (4 · I) (3)
The delay time Tout_3 until the stop pulse signal stop3 rises in the fourth voltage controlled delay generator cell VCDG_3 is:
Tout — 3 = t−t ₂ = (Vin−3 · I · T / C) · C / (4 · I) (4)
FIG. 5 is a characteristic diagram showing the voltage-time conversion characteristics of the voltage controlled delay generator VCDG having the voltage interleave configuration shown in FIG. 1. The horizontal axis represents the voltage value of the analog voltage Vin, and the vertical axis represents the start pulse signal start. Is a delay time Tout from the time when the signal rises to the time when the stop pulse signal stop rises. In FIG. 5, the four straight lines from the stop pulse signal stop0 to the stop pulse signal stop3 are respectively represented by the fourth voltage controlled delay generator cell from the equation (1) related to the first voltage controlled delay generator cell VCDG_0. FIG. 9 illustrates up to equation (4) for VCDG_3.

  In the case of the voltage-controlled delay generator VCDG having the voltage interleave configuration shown in FIG. 1, the analog voltage Vin is in the range of 0 to (4 · I · T / C) and the delay time Tout is 0 to 0, as shown in FIG. Within the range of T / 4, when the analog voltage Vin is applied, the delay time Tout from the rise of the start pulse signal start to the rise of the stop pulse signal stop is uniquely determined.

That is, the maximum value tmax of the delay time Tout is, for example, a case where Vin = I · (T / C) in Equation (1),
tmax = {I · (T / C)} · C / (4 · I) = T / 4
Given in. Here, in the case of the conventional voltage controlled delay generator VCDG shown in FIG. 17, the maximum value of the delay time Tout is given by tmax = T (clock cycle) as shown in FIG. In the case of the voltage controlled delay generator VCDG of the present embodiment shown in FIG. 4, the maximum value tmax of the delay time Tout can be compressed to (1/4) as compared with the conventional voltage controlled delay generator VCDG.

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at the timing when the start pulse signal start rises, the sampling time can be matched with the rise timing of the start pulse signal start. As a result, the sampling time shift can be eliminated, and the characteristics can be further improved.

(Second Embodiment)
Next, as a second embodiment of the voltage controlled delay generator cell VCDG_i, the voltage controlled delay generator VCDG and the analog / digital converter ADC according to the present invention, an analog using a voltage controlled delay generator VCDG having a voltage interleave configuration is used. A digital converter ADC will be described.

  FIG. 6 is a block diagram showing an example of a block configuration of an analog / digital converter ADC using the voltage controlled delay generator VCDG according to the present invention. As shown in FIG. 1, the voltage controlled delay generator VCDG is illustrated. A configuration example in the case of using a voltage controlled delay generator VCDG having a voltage interleave configuration is shown. The analog-to-digital converter ADC in the present embodiment is a voltage control delay having a voltage interleave configuration comprising a plurality (four in the case of FIG. 1) of voltage control delay generator cells VCDG_i and the control circuit CTL shown in FIG. The generator VCDG includes a plurality of (four in the case of FIG. 6) time digital converters TDC (TDC_0, TDC_1, TDC_2, TDC_3) and an encoder ENC. Here, the number of time-digital converters TDC is the same as the number of voltage-controlled delay generator cells VCDG_i constituting the previous-stage voltage-controlled delay generator VCDG.

  As described above in the first embodiment, the voltage-controlled delay generator VCDG having the voltage interleave configuration has the delay times Tout determined by the equations (1) to (4) according to the analog voltage Vin given from the outside. The stop pulse signal stop3 is generated from the stop pulse signal stop0 that rises in step S2. A stop pulse signal stop0 that is the output of the first voltage controlled delay generator cell VCDG_0, a stop pulse signal stop1 that is the output of the second voltage controlled delay generator cell VCDG_1, and an output of the third voltage controlled delay generator cell VCDG_2. The stop pulse signal stop2 and the stop pulse signal stop3 which is the output of the fourth voltage controlled delay generator cell VCDG_3 respectively correspond to a plurality of (four in the case of FIG. 6) time digital converters TDC. To the time digital converter TDC (TDC_0, TDC_1, TDC_2, TDC_3).

  Each of the time digital converters TDC (TDC_0, TDC_1, TDC_2, TDC_3) has a delay time Tout from the rising point of the start pulse signal start to the rising point of the stop pulse signals stop0, stop1, stop2, stop3 respectively input thereto. Is detected and converted into digital data Dout0, Dout1, Dout2, Dout3.

  Here, one or more of the stop pulse signals stop0, stop1, stop2 and stop3 rise within the time tmax = T / 4 of the delay time Tout after the start pulse signal start rises. ing. For example, in the case of 2 · I · T / C <Vin <3 · I · T / C, as shown in FIG. 3, the stop pulse signal stop3 is already at the high level when the start pulse signal start rises. The stop pulse signals stop0, stop1, and stop2 are at a low level.

  Thereafter, the stop pulse signal stop2 rises to a high level when the capacitance voltage ramp of the third voltage controlled delay generator cell VCDG_2 exceeds the analog voltage Vin. Thereafter, in the example shown in FIG. 3, the stop pulse signals stop0 and stop1 remain at the low level and the stop pulse signals stop2 and stop3 maintain the high level within the time of the maximum value tmax = T / 4.

  The encoder ENC in FIG. 6 inputs digital data Dout0 to Dout3 that are outputs of the respective time digital converters TDC_0 to TDC_3, and from which data of the digital data Dout0 to Dout3 the delay time Tout is detected. The stop pulse signal stop is high among the voltage controlled delay generator cells VCDG_0 to VCDG_3 from one or both of the information and the level information of the stop pulse signals stop0 to stop3 when the start pulse signal start rises. The voltage controlled delay generator cell VCDG_k (k: any integer of 0 to 3) rising to the level is specified.

  By specifying this voltage controlled delay generator cell VCDG_k, it is possible to detect the coarse voltage level of the analog voltage Vin, and this is detected by the upper bits (four time digital signals as shown in FIG. 6) of the analog / digital converter ADC output. In the case of the converter TDC, the higher 2 bits are output.

  Also, the obtained digital data Dout is converted from a thermometer code into digital data such as a predetermined code such as a binary code, and output as the remaining lower bits excluding the upper bits of the analog / digital converter ADC output. .

  This analog / digital converter ADC determines the maximum value tmax of the delay time Tout from the maximum delay time T (period of the clock signal clk) of the conventional analog / digital converter ADC shown in FIG. ) Can be reduced. Therefore, the deviation of the sampling time can be reduced, and the sampling rate can be increased and the analog input signal can be widened.

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at the timing when the start pulse signal start rises, the sampling time can be matched with the rise timing of the start pulse signal start. As a result, the sampling time shift can be eliminated, and the sampling rate can be further increased and the analog input signal can be widened.

(Third embodiment)
Next, as a third embodiment of the voltage controlled delay generator cell VCDG_i, the voltage controlled delay generator VCDG, and the analog / digital converter ADC according to the present invention, a voltage controlled delay generator VCDG having a time folding configuration will be described.

  FIG. 7 is a block diagram showing another example of the block configuration of the voltage controlled delay generator VCDG according to the present invention, which is different from that shown in FIG. 1, and shows a configuration example of the voltage controlled delay generator VCDG having a time folding configuration. Yes. The voltage controlled delay generator VCDG shown in FIG. 7 is a circuit that generates a digital signal having a delay time corresponding to the voltage value of the input analog voltage signal, as in the case of the voltage controlled delay generator VCDG of FIG. , A plurality (four in the case of FIG. 7) of voltage controlled delay generator cells VCDG_i (i: any integer, i = 0, 1, 2, 3 in the case of FIG. 7) and a clock supplied from the outside And a control circuit CTL that outputs a control signal for controlling the operation of each voltage controlled delay generator cell VCDG_i based on the signal clk. The voltage controlled delay generator VCDG shown in FIG. The circuit DET is added, and each voltage control delay generator cell VCDG_i is connected in parallel, and each output is connected to the subsequent rise detection circuit DET.

  That is, the voltage controlled delay generator VCDG of FIG. 7 is configured such that a rising detection circuit DET is further added to the voltage controlled delay generator VCDG shown in FIG. 1 in the first embodiment. After the control circuit CTL outputs the start pulse signal start, the detection circuit DET controls the voltage of one of the voltage controlled delay generator cells VCDG_i (i = 0, 1, 2, 3 in the case of FIG. 7). A voltage control with a time-folding configuration is to detect that the stop pulse signal stop is output from the delay generator cell VCDG_j (j: in the case of FIG. 7, an integer from 0 to 3) and output it as a stop holding pulse signal. It is a circuit for configuring the delay generator VCDG.

  The voltage controlled delay generator cell VCDG_i of FIG. 7, that is, the basic cell of the voltage controlled delay generator VCDG is exactly the same as FIG. 2 shown as the first embodiment, and each supplies a current of a predetermined current value. A plurality (four in FIG. 2) of current sources I (constant current sources) and a plurality of (four in FIG. 2) which are connected in series with each of the current sources I and turn on / off the current from each current source I. ), A capacitor C that is connected in series with a plurality of current switches S connected in parallel and generates a capacitance voltage ramp corresponding to the current value of the current from the current source I, that is, a ramp voltage ramp, and the capacitor C A leak switch LS that leaks the charge accumulated in the capacitor and discharges the generated ramp voltage ramp, the ramp voltage ramp generated by the capacitor C, and the analog voltage V input from the outside. The comparison result of the voltage value of the n, and a voltage comparator CMP outputs the delay time signal indicating a delay time corresponding to the voltage value of the analog voltage Vin (digital signal).

  Here, the number of installed voltage controlled delay generator cells VCDG_i is the same as the number of installed current sources I and current switches S in each voltage controlled delay generator cell VCDG_i.

FIG. 8 is a time chart showing an example of the operation of the voltage controlled delay generator VCDG having the time folding configuration shown in FIG. As shown in the time chart of FIG. 8, the voltage-controlled delay generator VCDG having the time folding configuration shown in FIG. 7 is supplied with a pulse (start pulse) as in the case of the voltage-controlled delay generator VCDG having the voltage interleave configuration shown in FIG. A function of generating a pulse (stop pulse signal stop) that rises after an arbitrary delay time Tout from the signal start), and a function that the delay time Tout can be changed by an analog voltage Vin input from the outside. is doing. FIG. 8 shows a stop holding pulse signal stop_folding output from the rising edge detection circuit DET by a stop pulse signal stop2 output from the third voltage controlled delay generator cell VCDG_2 constituting the voltage controlled delay generator VCDG of FIG. The pulse waveform is shown. In the initial state (before time t ₀ ), first, with respect to the four voltage controlled delay generator cells VCDG_0 to VCDG_3 in FIG. 7, the control signal ctrl, which is one of the control signals from the control circuit CTL, In response to the leak signal leak, the current switch S is turned off and the leak switch LS is turned on to leak the charge in the capacitor C and discharge the ramp voltage ramp.

The setting example of the control signal ctrl which is one of the control signals to the voltage controlled delay generator VCDG in FIG. 7 is exactly the same as the setting table in FIG. 4 of the first embodiment, and the elapsed time from the initial state is In response, each control signal ctrl input to each voltage controlled delay generator cell VCDG_i (i = 0, 1, 2, 3) is changed. That is, as described with reference to FIG. 4, the control signals ctrl to each voltage controlled delay generator cell VCDG_i are all “0” before the control is started (t <t ₀ ). Thereafter, at the time t ₀ when the control is started in synchronization with the rise of the clock signal clk, the leak switch LS is turned off, and each control signal ctrl to each voltage control delay generator cell VCDG_i is generated by the first voltage control delay. "0" for the second cell VCDG_0, "1" for the second voltage controlled delay generator cell VCDG_1, "2" for the third voltage controlled delay generator cell VCDG_2, and the fourth voltage controlled delay. The generator cell VCDG_3 is set to “3”, and each voltage control delay generator cell VCDG_i (i = 0, 1, 2, 3) is turned on by turning on a different number of current switches S. A current from a different number of current sources I is caused to flow to each capacitor C in each generator cell VCDG_i.

  That is, for example, when there are N (N: integer) voltage controlled delay generator cells VCDG_i (i = 0, 1, 2,..., (N−1)), each voltage controlled delay generator cell VCDG_i The number of current switches I and current switches S is N, and the number of current switches S in each voltage controlled delay generator cell VCDG_i that is turned on by the control signal ctrl is 0, 1, 2,. (N-1). In the case of FIG. 7 with four voltage controlled delay generator cells VCDG_i (N = 4), the first voltage controlled delay generator cell VCDG_0 turns off all four current switches S and the second voltage controlled delay The generator cell VCDG_1 turns on one of the four current switches S and turns off the remaining three current switches S. The third voltage controlled delay generator cell VCDG_2 turns on two of the four current switches, turns off the remaining two current switches, and the fourth voltage controlled delay generator cell VCDG_3 Three of the four current switches are turned on, and the remaining one current switch is turned off.

As a result, the capacitors C of the voltage controlled delay generator cells VCDG_0 to VCDG_3 are charged with electric charges from the current sources I except for the first voltage controlled delay generator cell VCDG_0 in which all the current switches S are off. As shown in FIG. 8, the ramp voltage ramp generated by the capacitor C, that is, the capacitance voltage ramp, becomes ramp waves having different slopes at t ₀ ≦ t <t ₂ . Assuming that the constant current value of the current source I is I and the capacitance of the capacitor C is C, the capacitance voltage ramp at time t at t ₀ ≦ t <t ₂ is the same as in the case of the first embodiment. Each of the generator cells VCDG_0 to VCDG_3 can be expressed as follows.

That is,
In the first voltage controlled delay generator cell VCDG_0,
ramp_0 = 0
In the second voltage controlled delay generator cell VCDG_1,
ramp_1 = I · (t−t ₀ ) / C
In the third voltage controlled delay generator cell VCDG_2,
ramp_2 = 2 · I · (t−t ₀ ) / C
In the fourth voltage controlled delay generator cell VCDG_3,
ramp — 3 = 3 · I · (t−t ₀ ) / C
In FIG. 3, it is assumed that there is a fifth voltage controlled delay generator cell VCDG_4 that does not actually exist, but for reference, the control signal ctrl is set to “4” to turn on all four current switches S. In this case, the capacitance voltage ramp is indicated by a broken line.

When the time interval from time t ₀ to t ₂ (that is, the period of the clock signal clk) is T (clock period), the capacitance voltage ramp at time t = t ₂ is the same as in the first embodiment. Each of the control delay generator cells VCDG_0 to VCDG_3 can be expressed as follows. Here, time t = t ₂ is the time when the start pulse signal start, which is the start point for converting the voltage value of the analog voltage Vin into time information on the time axis, rises.

In the first voltage controlled delay generator cell VCDG_0,
ramp_0 = 0
In the second voltage controlled delay generator cell VCDG_1,
ramp_1 = IT / T / C
In the third voltage controlled delay generator cell VCDG_2,
ramp_2 = 2 · I · T / C
In the fourth voltage controlled delay generator cell VCDG_3,
ramp_3 = 3 · I · T / C
Next, as shown in FIG. 8, at time _{t 2} is the rise time of the start pulse signal start, all the control signals ctrl for the voltage controlled delay generator cell VCDG_0~VCDG_3 "4" is set to. That is, all four current switches S are turned on for all four voltage controlled delay generator cells VCDG_i (i = 0, 1, 2, 3) of the voltage controlled delay generator cells VCDG_0 to VCDG_3.

As a result, the capacitor C of each voltage controlled delay generator cell VCDG_0 to VCDG_3 starts to be charged from the four current sources I at the same rate, and the ramp voltage ramp, that is, the capacitance voltage ramp generated by the capacitor C is When t ₂ ≦ t <t ₃ , as shown in FIG. 8, the ramp wave has a steep slope with the same slope according to the current values of the currents from all four current sources I. . That is, the capacity voltage ramp at the time t in the range of t ₂ ≦ t <t ₃ is expressed as follows in each of the voltage controlled delay generator cells VCDG_0 to VCDG_3 as in the case of the first embodiment. Can do.

That is,
In the first voltage controlled delay generator cell VCDG_0,
ramp — 0 = 4 · I · (t−t ₂ ) / C
In the second voltage controlled delay generator cell VCDG_1,
ramp_1 = 4 · I · (t−t ₂ ) / C + I · T / C
In the third voltage controlled delay generator cell VCDG_2,
ramp_2 = 4 · I · (t−t ₂ ) / C + 2 · I · T / C
In the fourth voltage controlled delay generator cell VCDG_3,
ramp_3 = 4 · I · (t−t ₂ ) / C + 3 · I · T / C
Although not actually shown in FIG. 8, for reference, a fifth voltage control delay for turning on all four current switches S by setting the control signal ctrl to “4” at t ₀ ≦ t <t ₂ . The capacity voltage ramp at t ₂ ≦ t <t ₃ when it is assumed that the generator cell VCDG — 4 exists is also indicated by a broken line.

  The voltage comparator CMP in each of the voltage controlled delay generator cells VCDG_0 to VCDG_3 includes a ramp voltage ramp_0 to ramp_3 of each voltage controlled delay generator cell VCDG_0 to VCDG_3, that is, a capacitance voltage ramp_0 to ramp_3, and an analog voltage input from the outside. When the magnitude of the voltage value with Vin (common to each voltage controlled delay generator cell VCDG_0 to VCDG_3) is compared and the capacitance voltage ramp exceeds the voltage value of the analog voltage Vin, the delay time according to the voltage value of the analog voltage Vin A pulse (stop pulse signal stop) rises as a delay time signal (that is, a digital signal indicating voltage information as time information on the time axis).

The delay time Tout from the rise of the start pulse signal start at time t = t ₂ to the rise of the stop pulse signals stop0 to stop3 in each of the voltage controlled delay generator cells VCDG_0 to VCDG_3 is the analog voltage Vin. The delay time according to the voltage value is expressed by the equations (1) to (4) shown in the first embodiment.

  FIG. 9 is a circuit diagram showing an example of the circuit configuration of the rising edge detection circuit DET in the voltage-controlled delay generator VCDG having the time loop configuration shown in FIG. 7, and the voltage-controlled delay generator VCDG having the time loop configuration according to the present embodiment. Therefore, a configuration example of a circuit newly added to the voltage control delay generator VCDG having a voltage interleave configuration is shown. The rising edge detection circuit DET shown in FIG. 9 includes a first exclusive OR gate EXOR1, a D flip-flop D-FF having two inputs (four inputs in FIG. 9), and a second exclusive OR EXOR2 having two inputs. A rising edge of any one of the input stop pulse signals stop0 to stop3 is detected and output as a stop holding pulse signal stop_folding.

  In FIG. 9, a four-input first exclusive OR gate EXOR1 performs an exclusive OR operation on four input stop pulse signals stop0 to stop3, and four input stop pulse signals stop0 to stop3. When the number of high levels is an even number, a parity signal parity is output that is at a low level, and when the number is at an odd number, is at a high level. The D flip-flop D-FF holds the value of the parity signal parity at the rising edge of the start pulse signal start, and outputs the negative logic as the parity start signal parity_start. The 2-input second exclusive OR EXOR2 performs an exclusive OR operation on the parity signal parity from the first exclusive OR gate EXOR1 and the parity start signal parity_start from the D flip-flop D-FF, and matches them. / A mismatch is detected, and a stop holding pulse signal stop_folding is output.

  Immediately after the start pulse signal start rises, the parity signal parity and the parity start signal parity_start do not match, and the stop holding pulse signal stop_folding, which is the negative logic output of the two-input second exclusive OR EXOR2, is at the low level. is there. Here, when one of the stop pulse signals stop0 to stop3 rises, the parity signal parity is inverted, so that the parity signal parity and the parity start signal parity_start coincide with each other, and the stop holding pulse signal stop_folding is at a high level. Get up to.

  In the first embodiment described above, the stop pulse signals stop0 to stop3 are individually output. In the third embodiment, the rising edge of any one of the stop pulse signals stop0 to stop3 is detected. The point of outputting one output signal reflecting the rising edge as the stop holding pulse signal stop_folding is different from the case of the first embodiment.

  FIG. 10 is a characteristic diagram showing the voltage-time conversion characteristics of the voltage-controlled delay generator VCDG having the time folding configuration of FIG. 7, where the horizontal axis is the voltage value of the analog voltage Vin, and the vertical axis is the start pulse signal start. Is the delay time Tout from the time when the signal rises to the time when any one of the stop pulse signals stops, that is, the time when the stop holding pulse signal rises. In FIG. 10, the four straight lines of the stop holding pulse signal stop_folding are respectively expressed by equations (1) to (4) relating to the first voltage controlled delay generator cell VCDG_0 (4) relating to the fourth voltage controlled delay generator cell VCDG_3. ), And Expressions (1) to (4) are the same as those in the first embodiment, as described above.

  However, in the case of the first embodiment, the stop pulse signals stop0 to stop3 are individually output as shown in FIGS. 1 and 5, but in the third embodiment, as described above, The difference is that the rising edge of any one of the stop pulse signals stop0 to stop3 is detected, and one output signal reflected in time is reflected as the stop holding pulse signal stop_folding. .

  In the case of the configuration of the voltage-controlled delay generator VCDG having the time folding configuration of FIG. 7, the analog voltage Vin is in the range of 0 to (4 · I · T / C) and the delay time Tout is 0 to 0, as shown in FIG. Within the range of T / 4, when the analog voltage Vin is applied, the delay time Tout from the rise of the start pulse signal start to the rise of the stop pulse signal stop is uniquely determined.

That is, the maximum value tmax of the delay time Tout is, for example, the case where Vin = I · (T / C) in Expression (1), as in the first embodiment.
tmax = {I · (T / C)} · C / (4 · I) = T / 4
Given in. Here, in the case of the conventional voltage controlled delay generator VCDG shown in FIG. 17, the maximum value of the delay time Tout is given by tmax = T (clock period) as shown in FIG. In the case of the voltage-controlled delay generator VCDG having the time folding configuration according to the present embodiment shown in FIG. 6, as in the case of the voltage-controlled delay generator VCDG having the voltage interleave configuration according to the first embodiment, In comparison, the maximum value tmax of the delay time Tout can be compressed to (1/4).

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at the timing when the start pulse signal start rises, the sampling time can be matched with the rise timing of the start pulse signal start. As a result, the sampling time shift can be eliminated, and the characteristics can be further improved.

(Fourth embodiment)
Next, as a fourth embodiment of the voltage-controlled delay generator cell VCDG_i, the voltage-controlled delay generator VCDG, and the analog-digital converter ADC according to the present invention, an analog using a voltage-controlled delay generator VCDG having a time folding configuration is used. An example of the digital converter ADC will be described.

  FIG. 11 is a block configuration diagram showing an example different from FIG. 6 of the block configuration of the analog / digital converter ADC using the voltage controlled delay generator VCDG according to the present invention. 1 shows an example of a configuration in the case of using a voltage-controlled delay generator VCDG having a time folding configuration as exemplified in FIG. The analog-to-digital converter ADC in the fourth embodiment includes a coarse analog-to-digital converter roughADC, a time-controlled voltage controlled delay generator VCDG, a time-digital converter TDC, and an encoder ENC. The point that the coarse analog-to-digital converter roughADC is provided and the point that there is one time digital converter TDC are different from the case of FIG. 6 of the second embodiment.

  The coarse analog-to-digital converter roughADC is a converter with sufficient coarse accuracy to convert the digital value into the upper bit position digital data having a predetermined number of digits with reference to the voltage value of the input analog voltage Vin. However, in some cases, the digital data at the upper bit position may be generated by the same mechanism as in the second embodiment, and the coarse analog-to-digital converter highADC may be omitted.

  As described above in the third embodiment, the voltage-controlled delay generator VCDG having the time folding configuration has the delay time Tout determined by the equations (1) to (4) according to the analog voltage Vin given from the outside. A rising stop holding pulse signal stop_folding is generated. The stop holding pulse signal stop_folding, which is the output of the rising edge detection circuit DET, is input to the subsequent time digital converter TDC.

  The time digital converter TDC detects the delay time Tout from the rising point of the start pulse signal start to the rising point of the input stop holding pulse signal stop_folding, and converts it into digital data comprising a thermometer code.

  Here, the stop holding pulse signal stop_folding rises within the time tmax = T / 4 of the delay time Tout after the start pulse signal start rises.

  In the second embodiment described above, it is necessary to specify the voltage controlled delay generator VCDG in which the stop pulse signal stop rises to the high level in order to obtain the information of the upper bits of the output of the analog-digital converter ADC. Met. However, in the fourth embodiment, a coarse analog-to-digital converter that converts the upper bits of digital data output from the analog-to-digital converter ADC into digital data with coarse accuracy according to the voltage value of the analog voltage Vin. The voltage-controlled delay generator VCDG having a configuration obtained from the output of the round ADC is the digital data at the upper bit position output from the coarse analog-to-digital converter, round ADC among the output data from the analog-to-digital converter ADC. Unlike the case of the second embodiment, the voltage controlled delay generator VCDG in which the stop pulse signal stop rises to a high level is used. There is no need to specify.

  The encoder ENC converts the digital data output from the time digital converter TDC from a thermometer code into a predetermined appropriate code (binary code, gray code, etc.) and outputs the digital data output from the analog / digital converter ADC. Output as the lower bits of. The lower bit digital data output from the encoder ENC is converted into the same code as the upper bit digital data output from the coarse analog-to-digital converter roughADC and output.

  Also in the analog / digital converter ADC of the fourth embodiment, as in the case of the second embodiment, the maximum value tmax of the delay time Tout is set to the delay of the conventional analog / digital converter ADC shown in FIG. The maximum value T (period of the clock signal clk) can be reduced to (T / 4). Therefore, the deviation of the sampling time can be reduced, and the sampling rate can be increased and the analog input signal can be widened. Further, the necessary number of time digital converters TDC can be reduced to (1/4) compared with the analog / digital converter ADC in the second embodiment, so that the analog / digital converter ADC having the same resolution can be obtained. Therefore, the circuit scale can be reduced and the power consumption can be reduced.

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at the timing when the start pulse signal start rises, the sampling time can be matched with the rise timing of the start pulse signal start. As a result, the sampling time shift can be eliminated, and the sampling rate can be further increased and the analog input signal can be widened.

(Fifth embodiment)
Next, as a fifth embodiment of the voltage-controlled delay generator cell VCDG_i, the voltage-controlled delay generator VCDG, and the analog-digital converter ADC according to the present invention, an analog using a voltage-controlled delay generator VCDG having a time folding configuration is used. Another example of the digital converter ADC will be described.

  FIG. 12 is a block configuration diagram showing an example different from FIGS. 6 and 11 of the block configuration of the analog / digital converter ADC using the voltage controlled delay generator VCDG according to the present invention. The voltage controlled delay generator VCDG is shown in FIG. FIG. 8 shows another example of the configuration in the case where the voltage-controlled delay generator VCDG having the time folding configuration illustrated in FIG. 7 is used. The analog / digital converter ADC in the fifth embodiment includes a first encoder ENC1, a voltage-controlled delay generator VCDG having a time folding configuration, a time digital converter TDC, and a second encoder ENC2.

  The analog / digital converter ADC of FIG. 12 is different from the case of FIG. 6 of the second embodiment in that there is one time digital converter TDC as in the case of FIG. 11 of the fourth embodiment. Yes.

  Further, in the analog-digital converter ADC of FIG. 12, the first encoder ENC1 is the same as the encoder ENC of FIG. 11 of the fourth embodiment, but the case of FIG. 11 of the fourth embodiment. A second encoder ENC2 is provided instead of the coarse analog-to-digital converter roughADC. Here, the second encoder ENC2 is connected to the start pulse signal start output from the control circuit CTL and each voltage control delay generator cell VCDG_i (FIG. 12) that constitutes the voltage control delay generator VCDG having the time folding configuration of FIG. In this case, stop pulse signals stop 0 to 3 output from i = 0 to 3) are input, and digital data of higher-order bit positions having a predetermined number of digits is extracted according to the voltage value of the analog voltage Vin. , Convert to a predetermined code.

  That is, in the analog-digital converter ADC of the fifth embodiment, the time folding configuration is not used without using the coarse analog-digital converter highADC used in the analog-digital converter ADC of the fourth embodiment. The stop pulse signals stop0 to stop3 output from the first voltage controlled delay generator cell VCDG_0 to the fourth voltage controlled delay generator cell VCDG_3 of the voltage controlled delay generator VCDG of FIG. By providing the second encoder ENC2 for output, the high-order bit of the output data of the analog / digital converter ADC is obtained, which is different from the analog / digital converter ADC in the fourth embodiment.

  As described above in the third embodiment, the voltage-controlled delay generator VCDG having the time folding configuration has the delay time Tout determined by the equations (1) to (4) according to the analog voltage Vin given from the outside. A rising stop holding pulse signal stop_folding is generated. The stop holding pulse signal stop_folding, which is the output of the rising edge detection circuit DET, is input to the subsequent time digital converter TDC.

  The time digital converter TDC detects a delay time Tout from the rising point of the input start pulse signal start to the rising point of the input stop holding pulse signal stop_folding, and converts it into digital data comprising a thermometer code. .

  The first encoder ENC1 converts the digital data output from the time digital converter TDC from a thermometer code into a predetermined appropriate code (binary code, gray code, etc.), and is output from the analog / digital converter ADC. Are output as lower-order digital data of the remaining number of digits excluding the upper-bit digital data output by the second encoder ENC2. The lower bit digital data and the upper bit digital data output from the first encoder ENC1 and the second encoder ENC2, respectively, are converted into the same code and output from each.

  On the other hand, the stop voltage signals stop0 to stop3 output from the first voltage controlled delay generator cell VCDG_0 to the fourth voltage controlled delay generator cell VCDG_3 at the time when the start pulse signal start rises are analog voltages at the time. The voltage level of Vin is 0 to (I · T / C), (I · T / C) to (2 · I · T / C), (2 · I · T / C) to (3 · I · T). / C) and (3 · I · T / C) to (4 · I · T / C). For example, when the analog voltage Vin is (2 · I · T) / C <Vin <(3 · I · T / C), as shown in FIG. 3, the stop is performed when the start pulse signal start rises. The pulse signal stop3 has already risen to the high level, and the stop pulse signals stop0, stop1, and stop2 are at the low level.

  That is, the data of the stop pulse signals stop0 to stop3 at the time when the start pulse signal start rises can be regarded as a thermometer code representing the upper bits of the output data (digital data) of the analog / digital converter ADC. The second encoder ENC2 uses a predetermined appropriate code (binary code, binary code, digital data at a high-order bit position of a predetermined number of digits from the thermometer code of the stop pulse signals stop0 to stop3 at the time when the start pulse signal start rises. The code is converted into a gray code or the like, and the high-order bits of the digital data output from the analog-digital converter ADC analog-digital converter ADC are obtained.

  An example of code conversion when the thermometer code is converted into binary code digital data in the second encoder ENC2 is as follows. When the stop pulse signals stop0 to stop3 at the time when the start pulse signal start rises are in the state represented by the thermometer code “0000”, the binary code “00” is converted and output, and the thermometer code “0001” is output. Is converted to binary code “01” and output, and in the state expressed by thermometer code “0011”, it is converted to binary code “10” and output. In the case of the state represented by the thermometer code “0111”, it is converted into a binary code “11” and output.

  Also in the analog / digital converter ADC of the fifth embodiment, as in the case of the fourth embodiment, the maximum value tmax of the delay time Tout is set to the delay of the conventional analog / digital converter ADC shown in FIG. The maximum value T (period of the clock signal clk) can be reduced to (T / 4). Therefore, the deviation of the sampling time can be reduced, and the sampling rate can be increased and the analog input signal can be widened. Further, the necessary number of time digital converters TDC can be reduced to (1/4) compared with the analog / digital converter ADC in the second embodiment, so that the analog / digital converter ADC having the same resolution can be obtained. Therefore, the circuit scale can be reduced and the power consumption can be reduced.

  Further, compared with the analog / digital converter ADC in the fourth embodiment, the coarse analog / digital converter roughADC is unnecessary, and the same function is realized by the second encoder ENC2 capable of digital processing. Therefore, when an analog / digital converter ADC having the same resolution is to be configured, the circuit scale can be further reduced and the power consumption can be reduced.

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at the timing when the start pulse signal start rises, the sampling time can be matched with the rise timing of the start pulse signal start. As a result, the sampling time shift can be eliminated, and the sampling rate can be further increased and the analog input signal can be widened.

(Sixth embodiment)
Next, as a sixth embodiment of the voltage controlled delay generator cell VCDG_i, the voltage controlled delay generator VCDG and the analog / digital converter ADC according to the present invention, a voltage controlled delay generator VCDG having a voltage interleave configuration is further time-interleaved. The voltage controlled delay generator VCDG configured will be described.

  FIG. 13 is a block diagram showing another example of the block configuration of the voltage controlled delay generator VCDG according to the present invention, which is different from those shown in FIGS. 1 and 7, and a plurality of (four in the case of FIG. 13) voltages. The voltage control delay generator VCDG of the voltage interleave configuration (× 4) composed of the control delay generator cells VCDG_i is further operated in a plurality of stages (8 stages in the case of FIG. 13) as a time interleave configuration (× 8) for each stage. An example in the case where a voltage controlled delay generator VCDG with a shifted timing is configured is shown.

  That is, the voltage controlled delay generator VCDG shown in FIG. 13 includes a control circuit CTL and a plurality of voltage controlled delay generator cells VCDG_i (in the case of FIG. 13, as in the case of the first embodiment, four). A voltage-controlled delay generator having a voltage interleave configuration has a multi-stage (8 stages in the case of FIG. 13) time interleave configuration, so that a plurality of multi-stage configurations (in the case of FIG. 13, 4 × 8 stages = total). The 32 voltage controlled delay generator cells VCDG_i are composed of voltage controlled delay generator cells VCDG_0, VCDG_1, VCDG_2, VCDG_3, VCDG_10, VCDG_11, VCDG_12, VCDG_13,.

  FIG. 14 is a time chart showing an example of the operation of the voltage controlled delay generator VCDG in which the voltage interleave configuration (× 4) shown in FIG. 13 is changed to a time interleave configuration (× 8). The time interleaving shift time can be freely designed, and the voltage control delay generator VCDG of each stage can be operated by shifting by a predetermined time interval. In the example shown in FIG. A case is shown in which the maximum delay time tmax = T / 4 required until the stop pulse signal stop is output after the start pulse signal start is output from the CTL.

  That is, after (T / 4) elapses after the start pulse signal start0 of the first-stage voltage-controlled delay generator VCDG of the time-interleaved configuration rises, the second-stage voltage-controlled delay generator VCDG After the start pulse signal start1 rises and further (T / 4) elapses, the start pulse signal start2 of the voltage control delay generator VCDG at the third stage rises. Finally, after 7 · (T / 4) has elapsed since the start pulse signal start0 of the voltage control delay generator VCDG at the first stage rises, the voltage control delay generator VCDG at the eighth stage. Start pulse signal start7 rises. Further, after the elapse of (T / 4), the start pulse signal start0 of the first-stage voltage controlled delay generator VCDG rises again, thereby realizing a time interleaving (time interleaving) operation at intervals of (T / 4). be able to.

  As described above, when the timing at which the voltage control delay generator VCDG of each stage operates is shifted by the maximum delay time tmax, the voltage control delay generator cell VCDG_i constituting each voltage control delay generator VCDG of each stage The number of the current sources I is an even number (four in the case of FIG. 13), and the number of stages of the voltage controlled delay generator VCDG arranged in parallel is equal to the time 2T corresponding to two cycles of the clock signal clk. The number of stages divided by the maximum value tmax (2T ÷ (4 / T) = 8 stages) is assumed.

  As shown in the time chart of FIG. 14, the voltage control delay generator VCDG of the voltage interleave configuration (× 4) composed of the four voltage control delay generator cells VCDG_i of FIG. 13 is further divided into eight stages of time interleave configuration (× 8 In general, the voltage-controlled delay generator VCDG is a pulse (stop pulse signal stop0i) that rises after an arbitrary delay time Tout from each pulse (start pulse signals start0 to start7) input to each stage of the time interleave configuration. ~ Stop7i: i = 0, 1, 2, 3), and the delay time Tout can be changed by an analog voltage Vin input from the outside. FIG. 14 shows pulse waveforms of stop pulse signals stop02 to stop72 output from the third voltage controlled delay generator cells VCDG_02 to VCDG_72 in each stage of the time interleave configuration of FIG. In the initial state of each voltage controlled delay generator VCDG at each stage, first, the current switch S is turned off and the leak switch LS is turned on to leak the charge in the capacitor C.

  In the case of the voltage controlled delay generator VCDG in which the voltage interleaved configuration as shown in FIG. 13 of the sixth embodiment is a multi-stage time interleaved configuration, the voltage controlled delay generator VCDG at each stage every (T / 4). This delay generation operation can be realized continuously and repeatedly, so that (1/8) compared to the one-cycle operation (2T) of the voltage controlled delay generator VCDG of the voltage interleave configuration of the first embodiment. It is possible to perform a delay operation at the time interval. Therefore, when the delay operation is used in the analog-to-digital converter ADC, a high-speed operation can be performed at a sampling rate eight times that when the voltage-controlled delay generator VCDG having the voltage interleave configuration of the first embodiment is used. .

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at each timing when the start pulse signals start0 to start7 rise, the sampling time can be matched with the rising timing of the start pulse signals start0 to start7. As a result, the sampling time shift can be eliminated, and the characteristics can be further improved.

(Seventh embodiment)
Next, as a seventh embodiment of the voltage controlled delay generator cell VCDG_i, the voltage controlled delay generator VCDG and the analog / digital converter ADC according to the present invention, a voltage controlled delay generator VCDG having a voltage interleave configuration is further time-interleaved. An example of the analog / digital converter ADC using the voltage controlled delay generator VCDG configured as described above will be described.

  FIG. 15 is a block configuration diagram showing an example of the block configuration of the analog / digital converter ADC using the voltage controlled delay generator VCDG according to the present invention, which is different from those shown in FIGS. 6, 11, and 12. FIG. A voltage interleave comprising a plurality (four in the case of FIG. 15) of voltage controlled delay generator cells VCDG_i (i = 0, 1, 2, 3 in the case of FIG. 15) as illustrated in FIG. 13 as the generator VCDG. The voltage controlled delay generator VCDG of the configuration (× 4) is further configured in a plurality of stages (8 stages in the case of FIG. 15) time interleave configuration (× 8), and the operation timing for each stage is shifted by a predetermined time interval. An example of the configuration of the analog / digital converter ADC when the voltage controlled delay generator VCDG is used is shown.

  That is, the analog-to-digital converter ADC in the seventh embodiment is an analog-to-digital converter ADC using the voltage-controlled delay generator VCDG of the voltage interleave configuration (× 4) in FIG. 6 of the second embodiment. As the time interleave configuration, a plurality of stages (eight stages in the case of FIG. 15) are used, and the operation timing is shifted for each stage (time interleave).

  As shown in FIG. 15, the analog-to-digital converter ADC in the seventh embodiment has a plurality (four in the case of FIG. 15) of voltage interleaving configurations constituting each stage of the time interleaving configuration (× 8). Voltage control delay generator cells VCDG_j0 to VCDG_j3, time digital converters TDC_j0 to TDC_j3 (j = 0, 1, 2,..., 7) of each stage, and time digital converters TDC_j0 to TDC_j3 (j = 0) of each stage. , 1, 2,..., 7) and an encoder ENC that converts the code. Here, the time digital converters TDC_j0 to TDC_j3 (j = 0, 1, 2,..., 7) of each stage respectively have digital data Dout00 to Dout03 composed of thermometer codes corresponding to the analog voltage Vin given from the outside. , Dout10 to Dout13,..., Dout70 to Dout73 are output at different timings.

  The encoder ENC is based on the control signal from the control circuit CTL, and the digital data Dout00 to Dout03, Dout10 to Dout13 output from the time digital converters TDC_j0 to TDC_j3 (j = 0, 1, 2,..., 7) of each stage. ,..., Dout70 to Dout73, digital data Doutk0 to Doutk3 output from the time digital converters TDC_k0 to TDC_k3 (k: any integer of 0 to 7) to which the start pulse signal start is input are selected. The code is converted into digital data of a predetermined appropriate code (binary code, gray code, etc.).

  Although the time interleaving time can be freely designed, in the seventh embodiment, after the start pulse signal start is output from the control circuit CTL, as shown in FIG. 14 of the sixth embodiment. The maximum delay time tmax = T / 4 required until the stop pulse signal stop is output.

  That is, after (T / 4) elapses after the start pulse signal start0 of the first-stage voltage-controlled delay generator VCDG of the time-interleaved configuration rises, the second-stage voltage-controlled delay generator VCDG After the start pulse signal start1 rises and further (T / 4) elapses, the start pulse signal start2 of the voltage control delay generator VCDG at the third stage rises. Finally, after 7 · (T / 4) has elapsed since the start pulse signal start0 of the voltage control delay generator VCDG at the first stage rises, the voltage control delay generator VCDG at the eighth stage. Start pulse signal start7 rises. Further, after the elapse of (T / 4), the start pulse signal start0 of the first-stage voltage controlled delay generator VCDG rises again, thereby realizing a time interleaving (time interleaving) operation at intervals of (T / 4). be able to.

  In the case of the analog-digital converter ADC using the voltage controlled delay generator VCDG in which the voltage interleaved configuration as shown in FIG. 15 of the seventh embodiment is a time interleaved configuration, each stage (T / 4) Since the delay generating operation of the voltage controlled delay generator VCDG can be realized continuously and repeatedly, the analog-digital converter ADC using the voltage controlled delay generator VCDG of the voltage interleave configuration of the second embodiment is used. Compared with the one-cycle operation (2T), a delay operation at a time interval of (1/8) is possible. Therefore, a high-speed operation at a sampling rate 8 times that of the analog-digital converter ADC using the voltage-controlled delay generator VCDG having the voltage interleave configuration of the second embodiment is possible.

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at each timing when the start pulse signals start0 to start7 rise, the sampling time can be matched with the rising timing of the start pulse signals start0 to start7. As a result, the sampling time shift can be eliminated, and the sampling rate can be further increased and the analog input signal can be widened.

(Eighth embodiment)
Next, as an eighth embodiment of the voltage controlled delay generator cell VCDG_i, the voltage controlled delay generator VCDG and the analog / digital converter ADC according to the present invention, a time controlled interleaved voltage controlled delay generator VCDG is further time-interleaved. An example of the analog / digital converter ADC using the voltage controlled delay generator VCDG configured as described above will be described.

  FIG. 16 is a block configuration diagram showing an example different from FIGS. 6, 11, 12, and 15 of the block configuration of the analog-digital converter ADC using the voltage controlled delay generator VCDG according to the present invention. A plurality (four in the case of FIGS. 11 and 12) of voltage controlled delay generator cells VCDG_i (FIG. 11 and FIG. 12) as illustrated in FIG. 11 of the fourth embodiment or FIG. 12 of the fifth embodiment. In this case, an analog / digital converter ADC using a voltage-controlled delay generator VCDG having a time folding configuration (× 4) consisting of i = 0, 1, 2, 3) and a rising edge detection circuit DET is further time-interleaved ( FIG. 8 shows an example in which an analog / digital converter ADC is configured using a plurality of stages (eight stages in the case of FIG. 16) with the operation timing shifted for each stage.

  In other words, the analog / digital converter ADC in the eighth embodiment is a voltage-controlled delay generator having a time folding configuration (× 4) illustrated in FIG. 11 of the fourth embodiment or FIG. 12 of the fifth embodiment. The analog-to-digital converter ADC_j (j = 0, 1, 2,..., 7) using the VCDG has a time interleave configuration, and the analog-to-digital converters ADC_0, ADC_1,. , 8 stages), and the operation timing of each stage is shifted (time interleaving).

  In FIG. 16, the clock distribution circuit CLK_DIS has eight phases of 45 ° in order to realize time interleaving for each stage of the analog-digital converter ADC_j (j = 0, 1, 2,..., 7). A shifted clock signal clk is generated. Further, the encoder ENC uses analog / digital converters ADC_0, ADC_1,..., ADC_7 (that is, a voltage-controlled delay generator VCDG having a time folding configuration) based on a control signal from a control circuit CTL (not shown). Of the digital data Dout0, Dout1,..., Dout7 output from the analog / digital converter ADC), the analog / digital converter ADC_k (k: any of 0 to 7) to which the start pulse signal start is input. The digital data Doutk output from the (integer) is selected and converted into digital data of a predetermined appropriate code (binary code, gray code, etc.).

  Although the time interleaving time can be freely designed, in the eighth embodiment, after the start pulse signal start is output from the control circuit CTL, as shown in FIG. 14 of the sixth embodiment. The maximum delay time tmax = T / 4 required until the stop pulse signal stop is output.

  That is, after (T / 4) has elapsed from the rise of the start pulse signal start0 input to the time digital converter TDC_0 constituting the first stage analog-digital converter ADC_0 having the time interleave configuration, the second After the start pulse signal start1 input to the time digital converter TDC_1 constituting the stage analog-digital converter ADC_1 rises and (T / 4) has passed, the third stage analog-digital converter ADC_2 is configured. The start pulse signal start2 input to the time digital converter TDC_2 rises. Finally, after 7 · (T / 4) has elapsed since the start pulse signal start0 input to the time digital converter TDC_0 constituting the first stage analog / digital converter ADC_0 rises, The start pulse signal start7 input to the time digital converter TDC_7 constituting the eighth-stage analog / digital converter ADC_7 rises. After the elapse of (T / 4), the start pulse signal start0 input to the time digital converter TDC_0 constituting the first-stage analog / digital converter ADC_0 rises again, so that the (T / 4) interval is increased. A time interleaving (time interleaving) operation can be realized.

  In the case of the analog / digital converter ADC using the voltage controlled delay generator VCDG in which the time folding configuration as shown in FIG. 16 of the eighth embodiment is a time interleaved configuration, Since the delay generation operation of the analog / digital converter ADC_j (j = 0, 1, 2,..., 7) can be continuously repeated, the time folding of the fourth or fifth embodiment is realized. Compared with the one-cycle operation (2T) in the case of the analog / digital converter ADC using the voltage-controlled delay generator VCDG having the configuration, the delay operation can be performed at a time interval of (1/8). Therefore, a high-speed operation at a sampling rate eight times that in the case of the analog-digital converter ADC using the voltage-controlled delay generator VCDG of the time folding configuration of the fourth embodiment or the fifth embodiment is possible.

  A sample and hold circuit can be inserted into the analog voltage Vin input. By holding the analog voltage Vin by the sample hold circuit at each timing when the start pulse signals start0 to start7 rise, the sampling time can be matched with the rising timing of the start pulse signals start0 to start7. As a result, the sampling time shift can be eliminated, and the sampling rate can be further increased and the analog input signal can be widened.

(Description of effects in the embodiment)
As described in detail above, according to the voltage controlled delay generator cell VCDG_i, the voltage controlled delay generator VCDG, and the analog / digital converter ADC according to the embodiments of the present invention, the following effects can be obtained. .

  In the voltage controlled delay generator cell VCDG_i and the voltage controlled delay generator VCDG as in the above-described embodiments, a voltage controlled delay generator cell having a plurality of current sources I (constant current sources) and a plurality of current switches S is provided. A voltage that can be taken by an externally input analog voltage Vin by providing a plurality of VCDG_i (basic cells of the voltage controlled delay generator VCDG) and adopting a voltage interleave configuration or a time folding configuration The maximum value tmax of the delay time can be greatly reduced as compared with the conventional voltage controlled delay generator VCDG while keeping the range (FS: full scale) constant.

  Further, in the analog-to-digital converter ADC using the voltage controlled delay generator VCDG as in each of the above-described embodiments, it is possible to reduce the deviation of the sampling time, increase the sampling rate, and the analog input signal. The bandwidth can be increased.

ADC, ADC_0, ADC_1,..., ADC_7 ... Analog to digital converter, C ... Capacitor, clk ... Clock signal, CLK_DIS ... Clock distribution circuit, CMP ... Voltage comparator, CTL ... Control circuit, ctrl ... Control data, D-FF ... D flip-flop, Dout, Dout0, Dout1, Dout2, Dout3 ... digital data, DET ... rising edge detection circuit, ENC ... encoder, ENC1 ... first encoder, ENC2 ... second encoder, EXOR1 ... first exclusive OR Gate, EXOR2 ... second exclusive OR, FS ... full scale, I ... current source, leak ... leak signal, LS ... leak switch, parity ... parity signal, parity_start ... parity start signal, ramp ... capacitance voltage (ramp voltage) ) Rough ADC ... coarse analog-to-digital converter, S ... current switch, start ... start pulse signal, stop, stop0, stop1, stop2, stop3 ... stop pulse signal, stop_folding ... stop holding pulse signal, T ... clock cycle, td ... delay buffer TDC, TDC_0, TDC_1, TDC_2, TDC_3, TDC_00, TDC_01, TDC_02, TDC_03, ..., TDC_70, TDC_71, TDC_72, TDC_73 ... time digital converter, Tout ... delay time, tmax ... maximum value of delay time, VCDG ... voltage Control delay generator, VCDG_0, VCDG_1, VCDG_2, VCDG_3, VCDG_00, VCDG_01, VCDG_02, VCDG_03 ~, VCDG_70, VCDG_71, VCDG_72, VCDG_73 ... voltage-controlled delay generator cell, Vin ... analog voltage.

Claims (18)

  In a voltage controlled delay generator cell for generating a digital signal having a delay time corresponding to a voltage value of an input analog voltage signal, a current source for supplying a current of a predetermined current value and a serial connection to the current source A current switch that turns on and off current from the current source, a capacitor that is connected in series with the current switch and generates a ramp voltage according to a current value of the current from the current source, and the capacitor generates A voltage comparator that outputs a result of comparing the voltage values of the ramp voltage and the analog voltage signal as a delay time signal indicating the delay time, and a leak for discharging the lamp voltage charged in the capacitor A voltage controlled delay generator cell comprising at least a switch, wherein the current source and the current switch connected in series are arranged in parallel. Voltage controlled delay generator cell characterized by being connected to.   A voltage-controlled delay generator cell according to claim 1 is provided in parallel with the number of the current sources, and a control signal for controlling each voltage-controlled delay generator cell based on a clock signal supplied from the outside. A voltage-controlled delay generator having a voltage-interleaved configuration including a control circuit for output, wherein the capacitor of each voltage-controlled delay generator cell is charged by a leak signal output as one of the control signals from the control circuit. After the lamp voltage is discharged, a different number of the current switches are turned on in each of the voltage controlled delay generator cells by a control signal output as one of the control signals from the control circuit, The voltage control delay generator cell is configured to apply the ramp voltage corresponding to the current from the different number of the current sources to each of the voltage control delay generator cells. The capacitor of each generator cell is charged, and then the control signal is changed at the rising edge of the start pulse signal output as one of the control signals from the control circuit, so that all the voltage controlled delay generator cells And turning on all the current switches to charge the capacitors of the voltage controlled delay generator cells with the ramp voltages corresponding to the currents from all the current sources, respectively. A voltage controlled delay generator characterized in that the delay time signal, which is a comparison result between the ramp voltage generated by the capacitor and the voltage value of the analog voltage signal, is output from the voltage comparator as a stop pulse signal. .   3. The voltage controlled delay generator according to claim 2, wherein when the number of the voltage controlled delay generator cells is N, the lamp voltage charged in the capacitor of each of the voltage controlled delay generator cells is discharged. After that, the number of turning on the current switch of each of the voltage controlled delay generator cells is set to 0, 1, 2,..., (N−1) by the control signal output from the control circuit. A voltage-controlled delay generator.   4. The voltage controlled delay generator according to claim 2, wherein the stop pulse signal is output from each of the voltage controlled delay generator cells constituting the voltage controlled delay generator after outputting the start pulse signal from the control circuit. Is controlled to a value obtained by dividing the time of one period of the clock signal by the number of the current sources provided in parallel in the voltage controlled delay generator cell. A voltage controlled delay generator.   5. The voltage controlled delay generator according to claim 2, wherein the voltage controlled delay generator is one of the voltage controlled delay generator cells after the start pulse signal is output from the control circuit. 6. A voltage control delay characterized by further comprising a rising edge detection circuit for detecting that the stop pulse signal is output from the cell and outputting the stop pulse signal as a stop holding pulse signal, wherein the voltage control delay generator has a time folding configuration. Generator.   6. The voltage controlled delay generator according to claim 5, wherein the rising edge detection circuit outputs an exclusive OR operation result of the stop pulse signal output from each of the voltage controlled delay generator cells as a parity signal. An exclusive OR gate, a D flip-flop that holds the value of the parity signal at the rising edge of the start pulse signal, and outputs a negative logic signal as a parity start signal, and the first exclusive OR gate And a second exclusive OR gate for performing an exclusive OR operation between the parity signal output and the parity start signal output from the D flip-flop. Voltage controlled delay generator.   A voltage-controlled delay generator according to any one of claims 2 to 4 is provided in a plurality of stages in parallel, and each of the voltage-controlled delay generators at each stage is operated while being shifted by a predetermined time interval. Voltage controlled delay generator.   8. The voltage controlled delay generator according to claim 7, wherein the time interval for operating each of the voltage controlled delay generators at each stage is outputted after the start pulse signal is outputted from the control circuit, and then the voltage controlled delay generator is used. A voltage-controlled delay generator characterized in that the maximum delay time required until the stop pulse signal is output from a cell.   9. The voltage controlled delay generator according to claim 8, wherein the number of the current sources in the voltage controlled delay generator cell constituting each of the voltage controlled delay generators in each stage is an even number and arranged in parallel. The voltage-controlled delay generator is characterized in that the number of stages of the voltage-controlled delay generator is a value obtained by dividing the time of two cycles of the clock signal by the maximum value of the delay time.   5. An analog-to-digital converter for converting to digital data corresponding to a voltage value of an input analog voltage signal and outputting the digital data, and the voltage control delay generator according to any one of claims 2 to 4; After outputting the start pulse signal, each output delay time until the stop pulse signal is output from each of the voltage controlled delay generator cells constituting the voltage controlled delay generator is converted into digital data and output. An analog / digital converter comprising: a time digital converter; and an encoder for converting the digital data output from each of the time digital converters into digital data having a predetermined code and outputting the digital data. .   7. An analog-to-digital converter for converting to digital data corresponding to the voltage value of an input analog voltage signal and outputting the digital data, and the start pulse signal from the control circuit according to claim 5 or 6; A time-to-digital converter that converts an output delay time until the stop-holding pulse signal is output from the rise detection circuit that constitutes the voltage-controlled delay generator, and outputs the digital data; An analog / digital converter, comprising: an encoder for converting the digital data output from the time digital converter into digital data of a predetermined code and outputting the digital data.   12. The analog-to-digital converter according to claim 11, wherein the analog voltage signal is input, and the voltage value of the analog voltage signal is converted into digital data at a high-order bit position having a predetermined number of digits. The coarse analog-to-digital converter outputs the low-order bit digital data of the remaining number of digits excluding the digital data at the high-order bit position converted by the coarse analog-to-digital converter. An analog-to-digital converter, wherein the digital data is converted into digital data having the same code as the digital data at the upper bit position.   13. The analog-to-digital converter according to claim 12, wherein the coarse analog-to-digital converter outputs the digital data at the upper bit position as a gray code or a binary code.   12. The analog / digital converter according to claim 11, wherein the start pulse signal output from the control circuit and the stop pulse signal output from each of the voltage controlled delay generator cells constituting the voltage controlled delay generator. And a second encoder for extracting digital data at a higher-order bit position having a predetermined number of digits with respect to the voltage value of the analog voltage signal and converting the digital data into digital data with a predetermined code. The encoder outputs the lower bit digital data of the remaining number of digits excluding the upper bit position digital data converted by the second encoder, and the higher bit position digital data output by the second encoder. Is converted into digital data with the same code as Analog-to-digital converter.   10. An analog / digital converter for converting to digital data corresponding to a voltage value of an input analog voltage signal and outputting the digital data, and the voltage controlled delay generator according to claim 7 and the voltage at each stage. Each of the voltage controlled delay generators constituting the voltage controlled delay generator at each stage after the start pulse signal is output from the control circuit by shifting the time by a predetermined time interval for each of the controlled delay generators Among the time digital converters for each stage for converting each output delay time of the stop pulse signal output from each cell to digital data and outputting the digital data, and among the time digital converters for each stage, the start pulse signal is The digital data output from each of the time digital converters of the stage output from the control circuit Analog-to-digital converter, characterized in that it comprises an encoder, a for converting the digital data code that defines Luo beforehand.   15. An analog-to-digital converter for converting to digital data according to the voltage value of an input analog voltage signal and outputting the digital data, comprising the analog-to-digital converter according to claim 11 in a plurality of stages in parallel. After the start pulse signal is output from the control circuit, the maximum delay time required until the stop pulse signal is output from the voltage controlled delay generator cell constituting each of the analog / digital converters in each stage The time interval for inputting the start pulse signal to the analog-to-digital converter at each stage is shifted by a value, and the encoder includes the analog / digital converter at the stage where the start pulse signal is input from the control circuit. The digital data output from the digital converter is stored in a predetermined code. Analog-to-digital converter and outputs converted to digital data.   17. The analog / digital converter according to claim 10, wherein each of the encoder and / or the second encoder converts input digital data from a thermometer code to a gray code or binary code digital data. An analog / digital converter characterized by converting to data and outputting it.   18. The analog-to-digital converter according to claim 10, further comprising a sample-and-hold circuit that samples and holds an input analog voltage signal, and the sample-and-hold circuit rises the start pulse signal. An analog / digital converter characterized in that the analog voltage signal is sampled and held at timing.

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