JPS60112148U - Vertical synchronization signal separation circuit - Google Patents
Vertical synchronization signal separation circuitInfo
- Publication number
- JPS60112148U JPS60112148U JP20392583U JP20392583U JPS60112148U JP S60112148 U JPS60112148 U JP S60112148U JP 20392583 U JP20392583 U JP 20392583U JP 20392583 U JP20392583 U JP 20392583U JP S60112148 U JPS60112148 U JP S60112148U
- Authority
- JP
- Japan
- Prior art keywords
- vertical synchronization
- synchronization signal
- signal separation
- separation circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａ、 ｂは再生映像の垂直同期信号と擬似垂直同
期信号とが重なっている垂直同期信号帰線期間部におけ
る信号の波形図、第２図は本考案の第１の実施例のブロ
ック図、第３図は本考案の第２の実施例のブロック図、
第４図は第３図に示すゲート回路とゲート制御回路部分
の詳細回路図、第５図は第４図に示す回路の動作タイミ
ング図である。
１・・・・・・擬似垂直同期パルス、２，３・・・・・
・再生映像信号の垂直同期信号、５・・・・・・再生映
像信号、６・・・・・・ゲート回路、７・・・・・・垂
直同期信号分離部、８・・・・・・ゲート制御回路、９
・・・・・・出力、ａ、ｂ、Ｃ。
ｄ・・・・・・節点、ｅ・・・・・・出力垂直同期信号
、Ｃ１・・・・・・容量、Ｑ１〜Ｑ８・・・・・・トラ
ンジスタ、Ｒ□〜Ｒ□３・・・・・・抵抗。Figures 1a and 1b are waveform diagrams of signals in the blanking period of the vertical synchronization signal where the vertical synchronization signal of the reproduced video and the pseudo vertical synchronization signal overlap, and Figure 2 is a block diagram of the first embodiment of the present invention. 3 is a block diagram of the second embodiment of the present invention,
FIG. 4 is a detailed circuit diagram of the gate circuit and gate control circuit shown in FIG. 3, and FIG. 5 is an operation timing diagram of the circuit shown in FIG. 4. 1...Pseudo vertical synchronization pulse, 2,3...
- Vertical synchronization signal of reproduced video signal, 5... Reproduction video signal, 6... Gate circuit, 7... Vertical synchronization signal separation section, 8... Gate control circuit, 9
...Output, a, b, C. d...Node, e...Output vertical synchronization signal, C1...Capacitance, Q1 to Q8...Transistor, R□ to R□3... ···resistance.
Claims (1)
記再生映像信号から垂直同期信号を分離する垂直同期信
号分離部と、前記分離された垂直同期信号のうちの最初
の垂直同期信号のみを通した後その垂直同期帰線期間中
はゲートを閉じるゲート回路、と、該ゲート回路の開閉
を制御するゲート制御回路とを含むことを特徴とする垂
直同期信号分離回路。a vertical synchronization signal separation unit that inputs a reproduced video signal into which a pseudo vertical synchronization signal has been inserted and separates the vertical synchronization signal from the reproduced video signal; 1. A vertical synchronization signal separation circuit comprising: a gate circuit that closes the gate during the vertical synchronization retrace period after the vertical synchronization blanking period; and a gate control circuit that controls opening and closing of the gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20392583U JPS60112148U (en) | 1983-12-28 | 1983-12-28 | Vertical synchronization signal separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20392583U JPS60112148U (en) | 1983-12-28 | 1983-12-28 | Vertical synchronization signal separation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60112148U true JPS60112148U (en) | 1985-07-30 |
Family
ID=30766329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20392583U Pending JPS60112148U (en) | 1983-12-28 | 1983-12-28 | Vertical synchronization signal separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60112148U (en) |
-
1983
- 1983-12-28 JP JP20392583U patent/JPS60112148U/en active Pending
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