JPS60109224A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60109224A
JPS60109224A JP21731683A JP21731683A JPS60109224A JP S60109224 A JPS60109224 A JP S60109224A JP 21731683 A JP21731683 A JP 21731683A JP 21731683 A JP21731683 A JP 21731683A JP S60109224 A JPS60109224 A JP S60109224A
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
ion
semiconductor substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21731683A
Other languages
Japanese (ja)
Inventor
Akihiro Sawairi
澤入 明弘
Kazumasa Onodera
小野寺 和正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21731683A priority Critical patent/JPS60109224A/en
Publication of JPS60109224A publication Critical patent/JPS60109224A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To form the electrode which has a good ohmic contact for a semiconductor substrate and is extremely stable thermally by performing ion implantation of the same semiconductor as the semiconductor substrate into a main electrode wiring metal and if necessary, into the aperture part of the semiconductor substrate and subjecting the substrate to heat treatment to form the alloy of the main electrode wiring metal and the ion-implanted semiconductor. CONSTITUTION:A predetermined P-N junction is formed and apertures 3 for forming a contact are arranged on the surface of a semiconductor substrate 1 which is the Si substrate convered with an electric insulating coating 2, e.g., an Si oxide film by using photo-etching technic. Next, on the surface of the semiconductor substrate 1 which is the Si substrate provided with the apertures 3, the metallic film 5 consisting of an Al film is formed by spattering or vapor deposition. Next, Si atoms which are the same semiconductor material as of the semiconductor substrate 1 are ion-implanted to form a semiconductor ion implantation layer 6 which is an Si ion implantation layeor. Then the metallic film 5 consisting of Al film ion-implanted is patterned by photo-etching technic to form an electrode wiring, followed by sintering to complete the electrode wiring 7.

Description

【発明の詳細な説明】 〔発明の楓する技術分野〕 本発明は半導体装置の製造方法に関し、特に浅い接合を
有する半導体装置の電極配線の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming electrode wiring of a semiconductor device having a shallow junction.

〔従来技術〕[Prior art]

従来、半導体装置の電極材料としては一般にアルミニウ
ムが使用されているが、アルミニウムは半導体材料と比
較的低い温度で合金反応を起こすため、超高周波増幅器
用トランジスタや超高速度スイッチ用トランジスタ等の
様な浅い接合を有する、又は拡散窓と電極取出し窓が同
じである半導体装置の場合には、容易に合金反応領域が
接合部に到達して接合を破壊するという欠点があった。
Conventionally, aluminum has generally been used as an electrode material for semiconductor devices, but since aluminum undergoes an alloy reaction with semiconductor materials at relatively low temperatures, it is often used in transistors for ultra-high frequency amplifiers, ultra-high speed switches, etc. In the case of a semiconductor device having a shallow junction or in which the diffusion window and the electrode extraction window are the same, there is a drawback that the alloy reaction region easily reaches the junction and destroys the junction.

この為、従来のアルミニウム電極を用いた半導体装置は
熱的に著しく不安定であった。
For this reason, conventional semiconductor devices using aluminum electrodes have been extremely unstable thermally.

以下、説明の便利の為、現在最も一般に用いられている
材料、すなわち、半導体としてシリコン、主電極配線全
域としてアルミニウムを例として説明する。
Hereinafter, for convenience of explanation, the materials most commonly used at present, ie, silicon as the semiconductor and aluminum as the entire area of the main electrode wiring, will be described as an example.

シリコン基板とアルミニウム電極との合金反応による接
合破壊の主因は、シリコンとアルミニウムを合金反応が
少し起ぎ冶程度の高温(一般に350〜600℃)に加
熱、即ちシンターしたとき、電極開孔部のシリコンがア
ルミニウム中へ拡散すると同時に、アルミニウムもシリ
コン基板に入シエミ、タベース接合部がアルミニラ・・
ムーシリコン合金によシ短絡する為であることが知られ
ている。
The main cause of bond failure due to an alloy reaction between a silicon substrate and an aluminum electrode is that when silicon and aluminum are heated to a high enough temperature (generally 350 to 600°C) that a slight alloy reaction occurs, i.e., sintered, the electrode openings are damaged. At the same time as the silicon diffuses into the aluminum, the aluminum also enters the silicon substrate, causing the base joint to become an aluminum oxide...
It is known that this is due to a short circuit caused by the mu-silicon alloy.

この接合短絡を防止する方法として従来(a) ニッケ
ル、タンタル、チタンなどの高融点金属とアルミニウム
との2層構造とし、また白金。
Conventional methods for preventing this junction short circuit include (a) a two-layer structure consisting of a high melting point metal such as nickel, tantalum, or titanium and aluminum, or platinum.

モリブデンなどとシリコンの化合物をシリコン基板とア
ルミニウムとの間に形成し、基板シリコンがアルミニウ
ム中に拡散するのを防ぐ。
A compound of silicon and molybdenum is formed between the silicon substrate and aluminum to prevent the substrate silicon from diffusing into the aluminum.

(b) アルミニウムーシリコン合金を蒸着又はスパッ
タし、シリコン入シアルミニウム配線を形成して基板シ
リコンがアルミニウム配線中へ拡散するのを防ぐ。
(b) Vapor depositing or sputtering an aluminum-silicon alloy to form a silicon-containing sia aluminum wiring to prevent substrate silicon from diffusing into the aluminum wiring.

(c) アルミニウムを用いず1例えば金、銀などを主
体とした多層配線構造とする。
(c) A multilayer wiring structure using gold, silver, etc. as the main material without using aluminum.

等の方法が知られているが、製法が複雑すぎたシ、実現
が因難であったシ、接触抵抗が高すぎたシ、バラツキが
大きいなど多くの欠点があった。
These methods are known, but they have many drawbacks, such as the manufacturing method being too complicated, the realization difficult, the contact resistance being too high, and the variation being large.

〔発明の目的」 本発明の目的は、上記欠点を除去し、半導体基板と電極
金属との良好なオーミック接続を得ると共に熱的に安定
な半導体装−の製造方法を提供することにある。
[Object of the Invention] An object of the present invention is to provide a method for manufacturing a thermally stable semiconductor device, which eliminates the above-mentioned drawbacks, obtains a good ohmic connection between a semiconductor substrate and an electrode metal, and is thermally stable.

〔発明の構成〕[Structure of the invention]

本発明の第1の発明の半導体装置の製造方法は、半導体
基板の一生面を憶う電気絶縁被膜に開孔を設ける工程と
、該基板上に金属膜を被着する工程と、該金属膜に半導
体基板と同一半導体材料をイオン注入する工程と、該金
属膜とイオン注入された半導体材料とを少なくとも部分
的に合金化する工程と、該金属膜をパターニングし電極
配線を形成する工程とを含んで構成される。
A method for manufacturing a semiconductor device according to a first aspect of the present invention includes the steps of providing an opening in an electrically insulating film that covers the entire surface of a semiconductor substrate, a step of depositing a metal film on the substrate, and a step of depositing a metal film on the substrate. a step of ion-implanting the same semiconductor material as that of the semiconductor substrate, a step of at least partially alloying the metal film and the ion-implanted semiconductor material, and a step of patterning the metal film to form electrode wiring. It consists of:

また、本発明の第2の発明Q半導体装置の製造方法は、
半導体基板の一生面を覆う電気絶縁被膜に開孔を設ける
工程と、前記開孔を通して半導体基板内に該基板と同−
半導体材料をイオン注入する工程と、該基板上に金属膜
を被着する工程と、該金属膜に半導体基板と同一半導体
材料をイオン注入する工程と、該金属膜とイオン注入さ
れた半導体材料とを少なくとも部分的に合金化する工程
と、該金属膜をパターニングし電極配線を形成する工程
とを含んで構成される。
Further, the second invention Q semiconductor device manufacturing method of the present invention includes:
A step of forming an opening in an electrically insulating film that covers the whole surface of a semiconductor substrate, and forming a hole in the semiconductor substrate through the opening, the same as that of the substrate.
A step of ion-implanting a semiconductor material, a step of depositing a metal film on the substrate, a step of ion-implanting the same semiconductor material as the semiconductor substrate into the metal film, and a step of ion-implanting the metal film and the ion-implanted semiconductor material. The method includes a step of at least partially alloying the metal film, and a step of patterning the metal film to form electrode wiring.

〔実施例の説明〕[Explanation of Examples]

以下、本発明の実施例について、図面を参照して説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)〜(c)は本発明の第1の発明の一実施例
を説明するための工程順に示した断面図である。
FIGS. 1(a) to 1(c) are sectional views shown in order of steps for explaining an embodiment of the first invention of the present invention.

第1図(a)K示すように1所定のPN接合を形成し、
表面が電気絶縁被膜21例えばシリコン酸化膜で覆われ
たシリコン基板である半導体基板1の電気絶縁被膜2に
ホトエツチング技術を用いてコンタクト形成用の開孔3
を設ける。
A predetermined PN junction is formed as shown in FIG. 1(a)K,
Openings 3 for forming contacts are formed in the electrically insulating film 2 of the semiconductor substrate 1, which is a silicon substrate whose surface is covered with an electrically insulating film 21, for example, a silicon oxide film, using a photoetching technique.
will be established.

次に、第1図(b)に示すように、開孔3の設けられた
シリコン基板である半導体基板1の表面に厚さ0.6μ
m程度のアルミニウム膜よシなる金属膜5をスパッパ又
は蒸着によ多形成する。
Next, as shown in FIG. 1(b), the surface of the semiconductor substrate 1, which is a silicon substrate provided with the opening 3, is coated with a thickness of 0.6 μm.
A metal film 5 such as an aluminum film having a thickness of approximately 1.5 m is formed by sputtering or vapor deposition.

次に、半導体基板1と同一半導体材料であるシリコン原
子をイオン注入しシリコンイオン注入層である半導体イ
オン注入層6を形成する。この場合、シリコン原子のイ
オン注入条件を加速電圧200KV、注入* 3.6X
 10”/an”とすると、飛程が0.24μmで、ア
ルミニウム内のシリコンの密度がアルミニウムのそれの
1%となシ適当である。
Next, silicon atoms, which are the same semiconductor material as the semiconductor substrate 1, are ion-implanted to form a semiconductor ion-implanted layer 6, which is a silicon ion-implanted layer. In this case, the ion implantation conditions for silicon atoms are acceleration voltage 200KV, implantation * 3.6X
Assuming 10"/an", it is appropriate that the range is 0.24 μm and the density of silicon in aluminum is 1% of that of aluminum.

次に、第1図(C)に示すように、イオン注入されたア
ルミニウム膜よシなる金属膜5をホトエツチング技術に
よシバターニングし電極配線を形成するO 次いで、450℃で10分程度シンターすることによシ
ミ極配線7は完成する。本実施例ではこのシンターによ
り、イオン注入されたシリコンはアルミニウム膜中に拡
散し、大部分がアルミニウムーシリコン合金に変換する
Next, as shown in FIG. 1(C), the ion-implanted metal film 5, such as an aluminum film, is patterned using a photoetching technique to form an electrode wiring.Then, it is sintered at 450°C for about 10 minutes. Particularly, the stain electrode wiring 7 is completed. In this embodiment, by this sintering, the ion-implanted silicon is diffused into the aluminum film, and most of it is converted into an aluminum-silicon alloy.

本実施例によればt極配線はアルミニウム膜中にシリコ
ンイオン注入を施したためアルミニウムーシリコン合金
で形成され、アルミニウムーシリコン合金はシリコンで
飽和し、その後の熱処理(一般にシンタ一温度よシ低温
である)によっても基板シリコンはアルミニウムーシリ
コン合金配線中に拡散することなく、接合は熱的に極め
て安定となり、かつシリコンがアルミニウム膜全体に拡
散するまでにシリコン基板とアルミニウム膜の界面でわ
ずかに合金化を生じるため、シリコン基板に対する良好
なオーミック接触がとれる。
According to this embodiment, the t-electrode wiring is formed of an aluminum-silicon alloy because silicon ions are implanted into the aluminum film, and the aluminum-silicon alloy is saturated with silicon, and then heat-treated (generally at a temperature lower than the sintering temperature). ), the substrate silicon does not diffuse into the aluminum-silicon alloy wiring, and the bonding becomes extremely stable thermally.Also, by the time the silicon diffuses into the entire aluminum film, a slight amount of alloying occurs at the interface between the silicon substrate and the aluminum film. Because of this, good ohmic contact with the silicon substrate can be achieved.

また、必要に応じアルミニウム膜上に電気絶縁膜を被着
してもよい。
Furthermore, an electrical insulating film may be deposited on the aluminum film if necessary.

なお、本実施例ではシンターは電極配線のパターニング
後に行なったが本発明はこれに限定されるものでなく、
シンターを電極配線のバターニング前に行なってもよい
In this example, sintering was performed after patterning the electrode wiring, but the present invention is not limited to this.
Sintering may be performed before patterning the electrode wiring.

第2図は本発明の第2の発明の一実施例を説明するため
の一部工程の断面図である。
FIG. 2 is a sectional view of a part of the process for explaining an embodiment of the second aspect of the present invention.

なお、本実施例で第1図(a)〜fc)に示した工程と
同じものは、それを引用して説明する。
In this example, the same steps as those shown in FIGS. 1(a) to fc) will be described with reference to them.

まず、第1図(a)に示したのと同様に% Par定の
PN接合を形成し、表面が一気絶縁被膜2、例えはシリ
コン酸化膜で後われだ半導体基板1の電気絶縁膜2にホ
トエツチング技術を用いてコンタクト形成用の開孔3t
−設ける。
First, a PN junction with a constant % Par is formed in the same manner as shown in FIG. Opening 3t for contact formation using photoetching technology
- Provide.

次に、第2図に示すように接合に達しない程度に浅く半
導体基板1と同一半導体材料であるシリコンをイオン注
入し、基板シリコン表面近傍に過剰シリコンイオン注入
層である過剰半導体イオン注入IwI4を形成する。
Next, as shown in FIG. 2, silicon, which is the same semiconductor material as the semiconductor substrate 1, is ion-implanted to a shallow depth that does not reach the junction, and an excess semiconductor ion implantation layer IwI4, which is an excess silicon ion-implanted layer, is implanted near the surface of the silicon substrate. Form.

次に基板上にアルミニウム膜よシなる金属膜5を被着す
る。
Next, a metal film 5 such as an aluminum film is deposited on the substrate.

次にアルミニウム膜よシなる全極膜5に半導体基板と同
一半導体I料であるシリコンをイオン注入し、シリコン
イオン注入層である半導体イオン注入層6を形成する。
Next, silicon, which is the same semiconductor material as the semiconductor substrate, is ion-implanted into the all-pole film 5, which is an aluminum film, to form a semiconductor ion-implanted layer 6, which is a silicon ion-implanted layer.

次に第1図(c)の場合と同様に、イオン注入されたア
ルミニウム膜よりなる金属膜5をホトエツチング技術に
よシバターニングし電極配線を形成する。
Next, as in the case of FIG. 1(c), the metal film 5 made of the ion-implanted aluminum film is patterned by photoetching to form electrode wiring.

次に、450℃で10分程度シンターすることによ#)
電極配線は完成する。なお、イオン注入の除虫じたシリ
コン基板の欠陥はシンター罠よシ回復するので問題はな
い。
Next, sinter at 450℃ for about 10 minutes.
Electrode wiring is completed. Note that defects in the silicon substrate that have been removed by ion implantation are not a problem because they can be recovered by the sinter trap.

本実施例によれば、アルミニウム膜被着前にイオン注入
を行ないシリコン基板の開孔部に過剰シリコンが存在し
ておシ、さらにアルミニウム膜中にも十分なイオン注入
を施しであるため、シンターの際には基板からアルミニ
ウム膜中へのシリコンの拡散は、このイオン注入された
過剰シリコンだけで済ますことができ、良好なオーミッ
ク接触が得られると同時に、基板シリコンがアルミニウ
ム膜中に拡散するのを妨げるので、特に浅い接合を有す
る半導体&箇を製造する場合に好都合となる。
According to this example, ion implantation is performed before depositing the aluminum film, so that excess silicon exists in the openings of the silicon substrate, and since sufficient ion implantation is also performed in the aluminum film, the sintering In this case, the diffusion of silicon from the substrate into the aluminum film can be completed with only this ion-implanted excess silicon, which provides good ohmic contact and at the same time prevents the diffusion of silicon from the substrate into the aluminum film. This is especially advantageous when manufacturing semiconductors with shallow junctions.

〔発明の効果〕〔Effect of the invention〕

以上説明したとお9、本発明によれば、主電極配線金属
内及び必要に応じて半導体基板の開孔部に半導体基板と
同一の半導体をイオン注入し熱処理することに、よシ主
電極配線金属とイオン注入された半導体との合金を形成
することによシ、半導体基板に対する良好な第4ミツク
接触を持ち、熱的に極めて安定な電極を有する半導体装
動が得られる。
As explained above, according to the present invention, the same semiconductor as the semiconductor substrate is ion-implanted into the main electrode wiring metal and, if necessary, into the opening of the semiconductor substrate and heat-treated. By forming an alloy with the ion-implanted semiconductor and the ion-implanted semiconductor, a semiconductor device is obtained that has a very thermally stable electrode with good fourth microcontact to the semiconductor substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第11伯)〜(C)は本発明の第1の発明の一実施例を
説明するだめの工程順に示した断面図、第2図は本発明
の第2の発明の一実施例を説明するだめの一部工程の断
面図である。 1・・・・・・半導体基板、2・・・・・・電気絶縁膜
、3・・・・・・開孔、4・・・・・・過剰半導体イオ
ン注入層、訃・・・・・金属膜、6・・・・・・半導体
イオン注入層、7・・・・・・電極配線。
11) to (C) are sectional views shown in the order of steps for explaining an embodiment of the first invention of the present invention, and FIG. 2 is a sectional view showing an embodiment of the second invention of the present invention. It is a sectional view of a part of the process of the pot. 1... Semiconductor substrate, 2... Electrical insulating film, 3... Opening, 4... Excessive semiconductor ion implantation layer, End... Metal film, 6... Semiconductor ion implantation layer, 7... Electrode wiring.

Claims (2)

【特許請求の範囲】[Claims] (1) 半導体基板の一生面を榎う電気絶縁被膜に開孔
を設ける工程と、該基板上に金属膜を被着する工程と、
該金属膜に半導体基板と同一半導体材料をイオン注入す
る工程と、該金属膜とイオン注入された半導体材料とを
少なくと4部分的に合金化する工程と、該金属膜をパタ
ーニングし電極配線を形成する工程とを含むことを特徴
とする半導体装置の製造方法。
(1) A step of providing an opening in an electrically insulating film covering the whole surface of a semiconductor substrate, and a step of depositing a metal film on the substrate,
A step of ion-implanting the same semiconductor material as that of the semiconductor substrate into the metal film, a step of alloying the metal film and the ion-implanted semiconductor material at least in four parts, and patterning the metal film to form electrode wiring. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.
(2)半導体基板の一生面を嶺う電気絶縁被膜に開孔を
設ける工程と、前記開孔を通して半導体基板内に該基板
と同一半導体材料をイオン注入する工程と、該基板上に
金鋼膜を被着する工程と、該金拠膜に半導体基板と同一
半導体材料をイオン注入する工程と、該金属膜とイオン
注入され九半導体材料とを少なくとも部分的に合金化す
る工程と、該金属膜をパターニングし電極配線を形成す
る工程とを含むことを特徴とする半導体装置の製造方法
(2) A step of providing an opening in an electrically insulating film covering the whole surface of a semiconductor substrate, a step of ion-implanting the same semiconductor material as that of the substrate into the semiconductor substrate through the opening, and a step of forming a gold steel film on the substrate. a step of ion-implanting the same semiconductor material as the semiconductor substrate into the metal film; a step of at least partially alloying the metal film and the ion-implanted semiconductor material; 1. A method for manufacturing a semiconductor device, comprising the steps of: patterning a semiconductor device to form an electrode wiring;
JP21731683A 1983-11-18 1983-11-18 Manufacture of semiconductor device Pending JPS60109224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21731683A JPS60109224A (en) 1983-11-18 1983-11-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21731683A JPS60109224A (en) 1983-11-18 1983-11-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60109224A true JPS60109224A (en) 1985-06-14

Family

ID=16702252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21731683A Pending JPS60109224A (en) 1983-11-18 1983-11-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60109224A (en)

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