JPS60108920A - Constant voltage circuit - Google Patents

Abstract

PURPOSE:To obtain output voltage reduced at its dispersion by making the threshold voltage of the 1st FET coincide with that of the 2nd FET and forming depression type FETs. CONSTITUTION:For instance, IGFETs 6, 7 are formed as depression type FETs having equal threshold voltage in adjacent channel dope. The voltage between a terminal VDD8 and an output voltage terminal 10 is set up to Vout and the voltage between the terminals VDD8 and VSS9 is set up to power supply voltage. When the FET6 shorts its gates and drain and the threshold voltage of the FET6 is set up to VTD1, VDD-Vout-VTD1>VDD-Vout is always valid because the VTD1 is negative voltage, so that the FET6 operates always at unsaturated status. When the FET7 shorts its gate and source and the threshold voltage of the FET7 is set up to VTD2, the output voltage Vout is made constant independently of the voltage variation between VDD and VSS at the time of -VTD2< VSS-Vout, i.e. at the time of saturated operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides two field effect transistors C and GF.
Abbreviated as ET. ), the process is easy and constant voltage output variation is minimized.

Conventionally, constant voltage circuits used in IG"FBT integrated circuits have been designed so that the output voltage does not change even if the power supply voltage fluctuates. Figure 1(a) and Figure 1(b) show an example of a conventional constant voltage circuit.The GFBT1 is a depression type, with a threshold voltage of Assume that
, let the value be Kx. A constant voltage output yo independent of the power supply voltage is output between the output terminal 5 and the Vss terminal 4. VC
are V TD , V Tl! l, KD, K
By F+, vo=VTI! ! -, li lower < z
X V, TD ・−= −(11)
) or the circuit shown in FIG. 1(b).

In order to create such a constant voltage value, two N-channel transistors are manufactured at the same time, and one transistor is made into a depletion type by doping the channel with, for example, phosphorus, so that the difference in threshold voltage is 9. However, variations in threshold voltage due to channel doping and variations in output voltage due to variations in K value are generally said to be 100 mV. Furthermore, in equation (1), in order to match the output voltage, it is necessary to precisely calculate and design ρrZ5. The temperature characteristics of the circuit shown in FIG. 1 include four temperature characteristics terms. This results in complex characteristics. The present invention was made in order to eliminate the above-mentioned conventional drawbacks, namely, variations in output voltage, complexity in design, and complexity in temperature characteristics. It provides a circuit.

Hereinafter, the present invention will be explained in detail based on Examples.

FIGS. 2(a) and 2(b) show circuit diagrams of first and second embodiments of the constant voltage circuit of the present invention.

The X GFKT 6 and the GFET 7 are depletion type transistors with equal threshold voltages. The circuit connection is
Conventional Fig. 1<1. ) and the circuit shown in FIG. 1(b). A feature of the present invention is that the depression carved GFETs 6 and 7 are made to have equal threshold voltages.

In manufacturing, the two GFFiTs 6 and 7 are simultaneously doped with, for example, phosphorus, to create a depression carved GFET with equal threshold voltage. The output constant voltage value obtained by the constant voltage circuit of the present invention is determined as follows. - As an example, solve the circuit of FIG. 2(b). Figure 2 (b
), the voltage between VDD8 and output voltage terminal 10 is set to V
The voltage between out, VDD8 and ss9 is the power supply voltage. For engineering GF'KT6, short-circuit the gate and drain.
If the threshold voltage of GFKT 6 is vTDI, then VT
Since DI is a negative voltage, it is always V flD −V
out - VTDI > VDD - Vout holds true and always operates in non-saturation. = On the other hand, the gate and source of the GFET7 are shorted. If the threshold voltage of the engineering GFEAT 7 is VTD2, then -V TD2 〈V B
When the output voltage V out becomes e −V out , that is, in the saturated operation, the output voltage V out becomes a constant voltage regardless of the voltage fluctuation between 7DD and 7ss.

Since a constant current flows through the painter GFET, K, (VTDI
)”= (2(Vout −V TD2)(Vout)
-Vout”) holds true, solve this, and V TDI
: Since V TD2 = V TD, V out = (1-y'2) VTD = 0.414
X(VTD) is obtained. In other words, the condition for determining the threshold voltage to obtain a certain output voltage is VTn=Vout10
．． It can be obtained from the simple relationship 414. Incidentally, the same holds true for the circuit shown in FIG. 2(a). Furthermore, the output voltage variation of the constant voltage circuit of the present invention is caused by two engineering GFEs.
Since the threshold value is determined by performing ion implantation with the same amount of implanted ions at the same time, T can be reduced by half compared to a conventional constant voltage circuit obtained from the difference in threshold voltage. Moreover, if the shapes of IGFETs 6 and 7 are designed in exactly the same way, the values will be the same, so complex human design calculations are not required. Further, since the value does not affect the constant voltage output value, variations in temperature characteristics can be eliminated and uniform characteristics can be obtained.

As detailed above, according to the constant voltage circuit of the present invention,
In order to obtain the desired constant voltage circuit on C, logic r←FnA
＾〒＾■Uram＾Hpl Omatagu τTM Heya V TD:
It can be easily determined from the formula V out / 0.414, and the variation in output voltage can be reduced by half compared to the conventional circuit using the difference in threshold voltage. A circuit with small variations can be obtained, and an extremely stable constant voltage circuit can be provided within the factory.

[Brief explanation of drawings]

Figures 1(a) and 1(b) are circuit diagrams of conventional constant voltage circuits, and Figures 2(a) and 2(b) are circuit diagrams of constant voltage circuits of the present invention, respectively. FIG. 3 is a circuit diagram of a first and second embodiment. 6.7...Depression carver GFET8 ・
...VDD 9...vs [+10...
...output voltage terminal or higher Applicant: Seiko Electronic Industries Co., Ltd. Attorney + Mogami Figure 2 and a) Figure 2 (b)

Claims (1)

[Claims] A source of a first field effect transistor whose gate and drain are connected and a drain of a second field effect transistor of the same conductivity type as the first field effect transistor whose gate and source are connected to a power source. 1. A constant voltage circuit, characterized in that the threshold voltages of the first and second field effect transistors are made equal in the circuit connected in series, and the circuit is of a depletion type.