GB2081940A - MOS transistor circuit - Google Patents

MOS transistor circuit Download PDF

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Publication number
GB2081940A
GB2081940A GB8025488A GB8025488A GB2081940A GB 2081940 A GB2081940 A GB 2081940A GB 8025488 A GB8025488 A GB 8025488A GB 8025488 A GB8025488 A GB 8025488A GB 2081940 A GB2081940 A GB 2081940A
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Prior art keywords
circuit
transistors
mos
series
voltage
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Withdrawn
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GB8025488A
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STC PLC
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STC PLC
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

Abstract

With an integrated circuit using MOS transistors it is often necessary to be able to generate the inversion threshold voltage VT accurately. The present invention achieves this with an all-MOS transistor circuit. In this circuit, a p-channel enhancement-mode transistor (M5) is in series with two series circuits (M1-M2 and M3-M4) each of which includes two series-connected MOS transistors. In the first series circuit the transistors (M1, M2) are diode-connected, and in the second series circuit one transistor (M3) is diode-connected. The other transistor (M4) of the second series circuit has its gate connected to the junction between the two transistors (M1, M2) of the first series circuit. By suitable proportioning of the transistors (M1, M2, M3, M4) in the two series circuits, and especially by suitable choice of the aspect ratios of their channels, the voltage produced at the junction of the transistors (M3, M4) of the second series circuit, which is the circuit's output, is equal to VT. By using MOS transistors for this circuit, an arrangement is produced which is compatible with the MOS devices for which it produces the voltage VT.

Description

SPECIFICATION MOS transistor circuit This invention relates to an electrical circuit for generating a defined voltage.

In the production of integrated circuits using MOS transistors it is often desired to have the voltage VT, often known as the strong inversion threshold voltage, generated by a circuit which is on the same substrate as the circuit elements to which that voltage is applied. Hence the present invention has as its object the production of such a circuit which is cheap and economical.

According to the present invention there is provided an electrical circuit for the generation of a defined voltage, which includes a first series circuit including two MOS transistors connected with their source-drain paths in series, each said MOS transistor having its gate connected to its drain, a second series circuit including two MOS transistors with their source-drain paths in series, one of the MOS transistors in said series circuit having its gate connected to its drain, and a connection from the junction between the transistors of the first series circuit and the gate of the other transistor of the second series circuit, the parameters of the transistors being such that the voltage generated at the junction between the transistors of the second series circuit is the defined voltage.

According to the present invention there is further provided an electrical circuit for the generation of a defined voltage, which includes first, second, third, fourth and fifth MOS transistors, of which the fifth MOS transistor is of opposite polarity type to the other four transistors and functions as a current source, in which one end of the source-drain path of the fifth MOS transistor is connected to one side of a direct current source when the circuit is in use, while the other end of that source-drain path is connected to two series circuits each of which is connected to the other side of the direct current supply when the circuit is in use, in which the first of said series circuits includes said first and second MOS transistors with their source-drain paths in series, each of said two MOS transistors having its gate connected to its drain, in which the second of said series circuits includes said third and fourth MOS transistors with their source-drain paths in series, the gate of the third MOS transistor being connected to the drain thereof, in which a connection extends from the junctions between the first and the second MOS transistors to the gate of the fourth MOS transistor, and in which the parameters of said first, second, third and fourth MOS transistors are such that the voltage at the junction between the third and fourth MOS transistors when the circuit is in use, which provides the circuit's output, in said defined voltage.

An embodiment of the invention will now be described with reference to the accompanying drawing, which relates to an integrated circuit implementation of the invention. In the circuit shown, transistors M1, M2, M3 and M4 are n-channel enhancement mode transistors, while M5, which functions as a current source, is a p-channel enhancement mode transistor. Note that M2 and M4 are current sinks. M1, M2, and M3, but not M4 are diode-connected.

The operation of the circuit depends on the fact that when a current I flows through an MOS transistor in the enhancement mode and with its gate connected to its drain, the current can be closely approximated by: I = B(VGS-VT)2 -- --- (1) 2 W where B = UOCOX L UO = carrier mobility Ccx = oxide (thin) capacitance per unit area W = = aspect ratio of the MOST (effective width W W divided by effective length L) VGS iS the gate source voltage and VET ITS the threshold voltage.

We may also define B0 = U0 C0x We now define VGS-VT=Ve (2) where Ve is referred to as the effective gate voltage. From the above definition and equation 1 we obtain <img class="EMIRef" id="026903690-00010001" />

Note that equations (1) and (2) imply that for a saturated enhancement mode transistor the voltage drop from gate to source is given by: VGS=VT+Ve (4) We now refer to the drawing. In the integrated circuit implementation, transistors M1, M2 and M4 are as nearly identical as close proximity on the substrate and uniform processing can make them. The current 1 flows in the series combination of M1 and M2, and as a result the voltage at the node (1) rises to Ve + VT.

Similarly the voltage generated at node 2 is 2Ve + 2VT, since M1 and M2 are as nearly as possible identical.

To obtain a voltage VT at node (3), which is the output of the circuit, the diode-connected transistor M3 has to drop a voltage 2Ve + VT. Such a voltage drop is obtained by so proportioning the transistors that M3 has a B factor one quarter that of M1, M2 or M3. Thus if the aspect ratio of M1, M2 or M4 is W/L as mentioned above, then the aspect ratio of M3 has to be W14L. These proportions are readily attained by the design of the transistors.

The closeness of the approximation of the output voltage to VT depends on the output impedance of M2, as this transistor is connected to M4, and on the AVT differential of M2 and M4. Any deviation from VT at the output is of the same order as the differential.

Note that M4 must be in saturation for the currents 11, and 12 in the two series circuit branches to be as close to each other in magnitude as possible. This means that Ve of M4 should be less than the minimum expected VT. In this case, the simple relationship ss3 = ss1/4 no longer applies: instead a correction factor is necessary, and the relationship between ss3 and ssl is: <img class="EMIRef" id="026903690-00020001" />

Claims (5)

1. An electrical circuit for the generation of a defined voltage, which includes a first series circuit including two MOS transistors connected with their source-drain paths in series, each said MOS transistor having its gate connected to its drain, a second series circuit including two MOS transistors with their source drain paths in series, one of the MOS transistors in said series circuit having its gate connected to its drain, and a connection from the junction between the transistors of the first series circuit and the gate of the other transistor of the second series circuit, the parameters of the transistors being such that the voltage generated at the junction between the transistors of the second series circuit is the defined voltage.
2. An electrical circuit for the generation of a defined voltage, which includes first, second, third, fourth and fifth MOS transistors, of which the fifth MOS transistor is of opposite polarity type to the other four transistors and functions as a current source, in which one end of the source-drain path of the fifth MOS transistor is connected to one side of a direct current source when the circuit is in use, while the other end of that source-drain path is connected to two series circuits each of which is connected to the other side of the direct current supply when the circuit is in use, in which the first of said series circuits includes said first and second MOS transistors with their source-drain paths in series, each of said two MOS transistors having its gate connected to its drain, in which the second of said series circuits includes said third and fourth MOS transistors with their source-drain paths in series, the gate of the third MOS transistor being connected to the drain thereof, in which a connection extends from the junction between the first and the second MOS transistors to the gate of the fourth MOS transistor, and in which the parameters of said first, second, third and fourth MOS transistors are such that the voltage at the junction between the third and fourth MOS transistors when the circuit is in use, which provides the circuit's output, in said defined voltage.
3. An electrical circuit as claimed in claim 2, in which the first, second, third and fourth MOS transistors are n-channel enhancement mode transistors, and the fifth MOS transistor is a p-channel enhancement mode transistors.
4. An electrical circuit as claimed in claim 1, 2 or 3, in which the defined voltage to be provided is the strong inversion threshold voltage VTfor transistors on an integrated circuit, the circuit for producing that voltage being formed on the same substrate as the circuitry for which is supplies that voltage.
5. An electrical circuit for the generation of a defined voltage, substantially as described with reference to the accompanying drawing.
GB8025488A 1980-08-05 1980-08-05 MOS transistor circuit Withdrawn GB2081940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8025488A GB2081940A (en) 1980-08-05 1980-08-05 MOS transistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8025488A GB2081940A (en) 1980-08-05 1980-08-05 MOS transistor circuit

Publications (1)

Publication Number Publication Date
GB2081940A true true GB2081940A (en) 1982-02-24

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ID=10515247

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8025488A Withdrawn GB2081940A (en) 1980-08-05 1980-08-05 MOS transistor circuit

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GB (1) GB2081940A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499416A (en) * 1981-11-25 1985-02-12 Tokyo Shibaura Denki Kabushiki Kaisha Reference voltage circuit for obtaining a constant voltage irrespective of the fluctuations of a power supply voltage
DE3704609A1 (en) * 1986-02-13 1987-08-20 Toshiba Kawasaki Kk Means for generating a DC reference voltage
EP0262156A1 (en) * 1986-03-20 1988-04-06 Motorola, Inc. Cmos voltage translator
EP0397408A1 (en) * 1989-05-09 1990-11-14 Advanced Micro Devices, Inc. Reference voltage generator
GB2238890A (en) * 1989-10-24 1991-06-12 Samsung Electronics Co Ltd Circuit for stabilizing a reference voltage
US5083079A (en) * 1989-05-09 1992-01-21 Advanced Micro Devices, Inc. Current regulator, threshold voltage generator

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499416A (en) * 1981-11-25 1985-02-12 Tokyo Shibaura Denki Kabushiki Kaisha Reference voltage circuit for obtaining a constant voltage irrespective of the fluctuations of a power supply voltage
DE3704609A1 (en) * 1986-02-13 1987-08-20 Toshiba Kawasaki Kk Means for generating a DC reference voltage
US4814686A (en) * 1986-02-13 1989-03-21 Kabushiki Kaisha Toshiba FET reference voltage generator which is impervious to input voltage fluctuations
EP0262156A1 (en) * 1986-03-20 1988-04-06 Motorola, Inc. Cmos voltage translator
EP0397408A1 (en) * 1989-05-09 1990-11-14 Advanced Micro Devices, Inc. Reference voltage generator
US5083079A (en) * 1989-05-09 1992-01-21 Advanced Micro Devices, Inc. Current regulator, threshold voltage generator
GB2238890A (en) * 1989-10-24 1991-06-12 Samsung Electronics Co Ltd Circuit for stabilizing a reference voltage

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