JPS60107909A - Manufacture of oscillating element - Google Patents

Manufacture of oscillating element

Info

Publication number
JPS60107909A
JPS60107909A JP21520383A JP21520383A JPS60107909A JP S60107909 A JPS60107909 A JP S60107909A JP 21520383 A JP21520383 A JP 21520383A JP 21520383 A JP21520383 A JP 21520383A JP S60107909 A JPS60107909 A JP S60107909A
Authority
JP
Japan
Prior art keywords
chip
electrodes
terminal
opposing
facing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21520383A
Other languages
Japanese (ja)
Inventor
Iwao Sasaki
巌 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21520383A priority Critical patent/JPS60107909A/en
Publication of JPS60107909A publication Critical patent/JPS60107909A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/177Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator of the energy-trap type

Landscapes

  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PURPOSE:To reinforce the adhesion between a chip and terminal electrodes and reduce spurious phenomena by beveling facing terminals of a piezoelectric chip where terminal electrodes are formed, and then forming facing electrodes on main facing surfaces of the chip and said terminal electrodes. CONSTITUTION:An oscillating element 21 is formed by forming the facing electrodes 23 on the main facing surfaces of the chip 22 which is rectangular in plane view respectively and then forming terminal electrodes 24 for external connections at the lengthwise terminal parts. Said terminal parts are beveled piror to the formation of the electrodes 23 to form slanting surfaces 22a. Then, the terminal electrodes of the oscillating element are beveled and formed at the terminal parts of the oscillation chip, so the adhesive strength between the chip and terminal electrodes is increased enough to withstand a thermal shock, and reflected elastic waves are refracted on the chip end surfaces, thereby reducing spurious radiation.

Description

【発明の詳細な説明】 +1) 発明の技術分野 本発明は振動素子の製造方法、特にチップの端部に形成
された端子電極の′4L着性を高める製造方法に関する
DETAILED DESCRIPTION OF THE INVENTION +1) Technical Field of the Invention The present invention relates to a method for manufacturing a vibrating element, and particularly to a method for improving the adhesion of terminal electrodes formed at the end of a chip.

fb) 技術の背景 圧電チップの対向主面にそれぞれ適当なパターン電極全
形成してなる振動素子は、該電極Iて交流電界を印加す
ると、チップは印加電界と等しい+61波数の応力を生
じ、かつ印加電界の周波数がチップの固有振動数に一致
すると共振し、強勢な振動が得られる。
fb) Background of the technology A vibrating element formed by forming appropriate patterned electrodes on the opposing main surfaces of a piezoelectric chip is such that when an alternating current electric field is applied to the electrodes I, the chip generates a stress of +61 wave number equal to the applied electric field, and When the frequency of the applied electric field matches the natural frequency of the chip, resonance occurs and strong vibrations are obtained.

第1図は振動素子の構成例金示す斜視図で・ちり、振動
素子1はLiNbO,等の圧電材料にてなるウェーハか
ら切出したチップ2の対向主面にそオ1ぞれ対向電極3
を形成1,、その長さ方向端部にはそれぞれ導体層4と
5にてなる外部4d続川端子冠極6が形成されている,
、なお対向取部3幻主部の一側から延長する引出しパタ
ーン3aを有し、引出しパターン3aはそれぞれ異なる
端子電極tVc接続されている。
FIG. 1 is a perspective view showing an example of the configuration of a vibrating element.The vibrating element 1 is made of a piezoelectric material such as LiNbO, and has a chip 2 cut out from a wafer, with one opposing electrode 3 on the opposing main surface.
1, and an external 4d connecting terminal crown pole 6 consisting of conductor layers 4 and 5 is formed at each end in the longitudinal direction.
Note that the facing portion 3 has a lead pattern 3a extending from one side of the main part, and each lead pattern 3a is connected to a different terminal electrode tVc.

(C) 従来技術と問題点 −−のように構成された振動素子において、大形のもの
はチップを切出したのち、対向電極及び端子電極が個別
忙形成されるが、例えばチップの長手方向の寸法が5+
m程度でありその厚さが500勾程度であるが如く小形
のものは、フォトリソグラフィック技術及びスクリーン
印刷技術を用い、多数個を間開に作成している。
(C) Prior art and problems - In the case of a large-sized vibrating element, after cutting out a chip, a counter electrode and a terminal electrode are individually formed. Dimensions are 5+
Small pieces, such as those with a thickness of about 500 mm and a thickness of about 500 mm, are manufactured in large numbers at intervals using photolithographic technology and screen printing technology.

第2図は、1枚のウェーハがら複数個の振動素子を、フ
ォトリングラフイック技術及びスクリーン印刷技術で作
成する従来方法の主要工程を工程順に説明するための図
である。
FIG. 2 is a diagram for sequentially explaining the main steps of a conventional method for producing a plurality of vibrating elements from one wafer using photophosphorographic technology and screen printing technology.

第21別(イ)において、圧電性を有するLiNb0.
やLiTa03v+の単結晶から作成されたウェーハ1
1の対向主面°(表面と異面)にAujN?12を蒸着
する。
In Part 21 (A), LiNb0.
Wafer 1 made from a single crystal of LiTa03v+
AujN? 12 is deposited.

次いで、第2図(ロ)に示す如くAuM12をフォトリ
ソグラフィック技術により選択的にエツチング溶去し、
複数個の対向7八仙3が2列に接続された梯子形状のA
uパターン13、即ち引出しパターン3a/i向合せに
接続されて21をなす電極3の複数対が各電極主部で引
出しパターン3aと直交方向に接続されたパターン13
を形成させる。ただし、ウェーハ11の表面と裏面に形
成されたパターン13は、同一方向かつ側面視チドリ状
に設けられ、パターン13の前記電極主部に′なる部分
がウェーハ11の表裏に対向している。
Next, as shown in FIG. 2(b), AuM12 was selectively etched and dissolved away using photolithographic technology.
Ladder-shaped A with multiple opposing 7-8 immortals 3 connected in two rows
U pattern 13, that is, a pattern 13 in which a plurality of pairs of electrodes 3 forming 21 connected to the lead-out patterns 3a/i facing each other are connected in a direction orthogonal to the lead-out pattern 3a at each electrode main part.
to form. However, the patterns 13 formed on the front and back surfaces of the wafer 11 are provided in the same direction and in a staggered pattern when viewed from the side, and the portions of the patterns 13 that correspond to the electrode main portions face the front and back sides of the wafer 11.

次いで、スクリーン印刷技術により紀2図(ハ)に示す
如く、ウェーハ11の対向主面専体層4となる導体パタ
ーン14を対向形成、即ち複数個の導体層4をその幅方
向及び長さ方向に接続した帯状、パターン141Auパ
ターン13の長さ方向中心部とその反対側のウェーハ主
面V:対向形成させる。
Next, as shown in Fig. 2 (c) of the wafer 11, the conductor patterns 14, which will become the dedicated layer 4 on the opposite main surface of the wafer 11, are formed facing each other by screen printing technology, that is, the plurality of conductor layers 4 are formed in the width direction and the length direction. A strip-like pattern 141 connected to the longitudinal center of the Au pattern 13 and the wafer main surface V on the opposite side are formed to face each other.

次いで、導体パターン14の昆さ方向中心線に沿って、
及びAuパターン13の前記電極主部接続線に沿ってダ
イシングンーにより切断すると第2図に)に示す如く、
チップ2に1対の対向′べ電極3及び2対の導体層4を
形成させた伽111II′l/:子1aが完成される。
Next, along the center line of the conductor pattern 14,
And when the Au pattern 13 is cut by dicing along the connection line of the electrode main part, as shown in FIG. 2),
A chip 1a is completed in which a pair of opposing electrodes 3 and two pairs of conductor layers 4 are formed on the chip 2.

このように作成された振動素子1aは、その櫨まパッケ
ージの基板に搭載し、チップ2の厚嘔ヵ向に対向する1
対の導体層4を前記搭載するための導電性接麓利で接続
させてもよいが、第1図に示す如くチップ2の端面に均
一で必要とする厚さの導体層5を形成して振動素子1を
完成させることにより、チップ2の小形化及び端面で減
衰するエネルギーを低減させることができる。
The vibrating element 1a created in this way is mounted on the substrate of the square package, and the vibrating element 1a is mounted on the board of the chip 2.
The pair of conductor layers 4 may be connected by the conductive contact for mounting, but as shown in FIG. By completing the vibrating element 1, the chip 2 can be made smaller and the energy attenuated at the end face can be reduced.

しかし、ウェー7・110対向主面は鏡面に仕上げてあ
り、該鏡面に形成された導体層4は接着力が不十分であ
ること及び接着面積を大きくし難いこともあって、熱衝
撃により動かされることがあった1、 fdl 発明の目的 本発明の目的は、上記問題点の除去された振動素子f提
供することである。
However, the main surfaces of the wafers 7 and 110 facing each other are finished with a mirror surface, and the conductor layer 4 formed on the mirror surface has insufficient adhesive strength and is difficult to increase the adhesive area, so it does not move due to thermal shock. 1. fdl OBJECT OF THE INVENTION An object of the present invention is to provide a vibrating element f that eliminates the above-mentioned problems.

tel 発明の構成 上家目的は、端子η1、極が形成される圧電チップの対
向端全面取り加工したのち、チップ対向主面の対向…′
11乍及びM’i記※iM子亀榛を形成することを特徴
とする振動素子の製造方法により達成される。
tel The purpose of the invention is to process the opposing end of the piezoelectric chip where the terminal η1 and the pole are formed, and then process the opposing main surface of the chip...'
This is achieved by a method for manufacturing a vibrating element characterized by forming 11 and M'i notes.

(f、l 発明の実施例 以下に、図面音用いて本発明の実l′庭例に係わる振動
素子を説明する。
Embodiments of the Invention Below, a vibrating element according to an embodiment of the present invention will be explained with reference to the drawings.

第3図は本発明方法にてなる振動共振子の一例を示す側
面図、第4図はチップ端面の面取り用砥石例の間部を示
す断面図、第5図は第3図に示す振動素子の量産例′f
:錆、明するためその主便工程全工程順VC示した図で
ある。
FIG. 3 is a side view showing an example of a vibration resonator made by the method of the present invention, FIG. 4 is a cross-sectional view showing an example of a grindstone for chamfering the end face of a chip, and FIG. 5 is a vibration element shown in FIG. 3. Mass production example'f
: Rust, for clarity, is a VC diagram showing the entire process order of the main process.

第3図において、振動素子21は平面視長方形のチップ
22の対向主面にそれぞれ対向電極23を形成し、前記
長方形の長さ方向端部には外部接続用の端子電極24が
、対向電極23を形成したのちに形成されているが、前
記端部には電極23を形成するのに先立って面取り加工
が施され、斜面22aが形成されている。
In FIG. 3, the vibrating element 21 has opposing electrodes 23 formed on opposing main surfaces of a chip 22 that is rectangular in plan view, and a terminal electrode 24 for external connection is provided at the longitudinal end of the rectangle. However, prior to forming the electrode 23, the end portion is chamfered to form a slope 22a.

なお、前記面取り加工はチップ22の上面縁と下面縁と
を別工程で実施してもよいが、第4図(イ)に示す如く
断面V字形の溝31が形成されたダイヤモンド砥石32
、又は第4図(ロ)VC示す如く断面U字形の溝33が
形成されたダイヤモンド砥石;(4を用いて、前記上面
縁と下面縁とを同時に研削すミも るが望ましい。また、砥石34f、用いる際に溝33の
幅がチップ22の厚さとほぼ同寸法のものを使用すれば
、チップ22の端面近傍主面が砥石34及び面取り加工
の切粉により荒されるため、端子電極24の接着力が強
められるようになる。
Note that the chamfering process may be performed on the upper surface edge and the lower surface edge of the chip 22 in separate processes, but as shown in FIG.
, or a diamond grindstone in which a groove 33 having a U-shaped cross section is formed as shown in FIG. 34f, if the width of the groove 33 is approximately the same as the thickness of the chip 22, the main surface near the end face of the chip 22 will be roughened by the grindstone 34 and chips from the chamfering process, and the terminal electrode 24 will be roughened. The adhesive strength will be strengthened.

第5図(イ)において、圧電材料にてなるウェーハを切
断した短冊片41は、その幅寸法がチップ22の長さ方
向の寸法(例えば約5m)と同じになっており、その厚
さはチップ22の厚さく例えば500/zm)と同じで
ある。
In FIG. 5(a), a strip 41 cut from a wafer made of piezoelectric material has a width that is the same as the length of the chip 22 (for example, about 5 m), and a thickness of the strip 41. The thickness of the chip 22 is the same as, for example, 500/zm).

そこで、第4図に示した如きダイヤモンド砥石を用いて
第5図(ロ)に示す如く、短冊片41の幅方向端面に面
取り加工を施し、2対の斜面42を研削形成する。
Therefore, using a diamond grindstone as shown in FIG. 4, as shown in FIG. 5(b), the end faces of the strips 41 in the width direction are chamfered to form two pairs of slopes 42 by grinding.

次いで、卯、5図(ハ)K示す如く、短冊片41の全面
にAu層を被着したのち複数個の電極23の主部を接1
t!;+:L−たa歯状のAuパターン43を、フォト
リソグラフィック技術等にて形成させるが、電極引出し
パターン23a(第3図)の先端に相当するAuパター
ン43の一部は斜面42と側面45及び反対面の一部に
形成させる。
Next, as shown in FIG.
T! ;+: An L-a tooth-shaped Au pattern 43 is formed by photolithographic technology, etc., but a part of the Au pattern 43 corresponding to the tip of the electrode lead pattern 23a (FIG. 3) is formed on the slope 42 and the side surface. 45 and a part of the opposite surface.

次いで、第5図に)に示す如く、短冊片41の前記面取
り端面に沿って、端子電極24が並列に接続された1対
の導体層44t−スクリーン印刷技術で形成させたのち
、図中に一点@線で示す如くA1】パターン43を各櫛
歯に分けて割断すると、第3図に示す袂数個(図は16
個)の振動素子21が同時に完成する。なお、ウェーハ
から短冊片41に割断及び振動素子21に割断する手法
は、従来方法における切断と同じ手法で行なわれる。
Next, as shown in FIG. 5), a pair of conductor layers 44t in which terminal electrodes 24 are connected in parallel are formed along the chamfered end surface of the strip 41 by screen printing technology. When the A1 pattern 43 is divided into each comb tooth as shown by the single point @ line and cut, several comb teeth are cut as shown in Fig. 3 (the figure shows 16
) vibrating elements 21 are completed at the same time. Note that the method of cutting the wafer into strips 41 and into the vibrating elements 21 is the same as the cutting method used in the conventional method.

tg+ 発明の効果 以上説明した如く本発明方法によれば、振@11素子の
端子電極が面取り加工され振動チップの輸部に形成され
る7’Cめ、該チップと端子電極との接着力が強化され
て従来の熱衝撃にも十分耐えるようになったのみならず
、前記面取りによりチップ端面における弾性波の反射が
屈折されるため、スプリアスが低減された効果は極めて
大きい。
tg+ Effects of the Invention As explained above, according to the method of the present invention, the terminal electrode of the vibration @11 element is chamfered and the adhesive force between the chip and the terminal electrode is Not only is it strengthened and can withstand conventional thermal shocks, but the chamfering refracts the reflection of elastic waves at the end face of the chip, which has an extremely significant effect in reducing spurious waves.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は振動素子の構成例を示す斜視図、第2図は前記
振動素子を量産する従来方法の主要工程を説明するため
の図、第3図は本発明方法になる振動素子の一例を示す
側面図、第4図は第3図に示す振動素子のチップ端v1
を面取りする砥石例の要部を示す断面図、第5図は第3
図に示す振動素子の蓋産例を説明するためその主要工程
を示した図である。 なお図中において、1ela、21は振動素子、2.2
2はナツプ、22aは面取り斜面、3.23は対向電極
、3a、23&は引出しノくターン、6゜24は端子…
′極、13.43は対向電極の集合ノくターン、14.
24は端子電極の集合パターン、41は短冊片を示す。
FIG. 1 is a perspective view showing an example of the configuration of a vibrating element, FIG. 2 is a diagram illustrating the main steps of the conventional method for mass-producing the vibrating element, and FIG. 3 is an example of a vibrating element according to the method of the present invention. The side view shown in FIG. 4 is the tip end v1 of the vibrating element shown in FIG. 3.
A sectional view showing the main parts of an example of a grindstone for chamfering.
FIG. 3 is a diagram showing the main steps for explaining an example of lid production of the vibrating element shown in the figure. In the figure, 1ela, 21 is a vibration element, 2.2
2 is a nap, 22a is a chamfered slope, 3.23 is a counter electrode, 3a, 23 & is a drawer turn, 6° 24 is a terminal...
'pole, 13.43 is a set of counter electrode turns, 14.
Reference numeral 24 indicates an aggregate pattern of terminal electrodes, and 41 indicates a strip.

Claims (2)

【特許請求の範囲】[Claims] (1) LiNb0.等の圧電材料=vc″Cなるウェ
ーハから切出したチップの対向主面て、引出しパターン
が一側から延長する対向或矯を形成し、前記チップの対
向端には前記引出しパターンの一方がそれぞれ接続され
る端子電極を形成しCなる振#素子において、前記チ2
プの1jil記対向端倉面取り加工したのち前記対向i
、、極及び端子IL極極刑形成ることを特徴とする振屯
す素子の製造方法。
(1) LiNb0. Opposing main surfaces of a chip cut out from a wafer made of piezoelectric material = vc''C form opposing leading patterns extending from one side, and one of the leading patterns is connected to the opposite end of the chip, respectively. In the oscillator element C, the terminal electrode of the chip 2 is
After chamfering the opposing end wells of the
A method for manufacturing a oscillating element, characterized by forming poles and terminals IL.
(2)蓄数個の前記チップがマトリックス配列で切出さ
れる前記ウェーハを前記対向端の対向長さを幅とした短
冊片に切断し、前記短冊片はその幅方向端面を面取り加
工したのち複数組の前記対向載椿と端子電極を形成し、
次いで前記チップに切断することを特徴とする特許 に記献した振f#素子の模造方法。
(2) The wafer from which an accumulated number of chips are cut out in a matrix arrangement is cut into strips whose width is the length of the opposing ends, and the strips are cut into a plurality of strips after chamfering the end faces in the width direction. forming a terminal electrode with the opposing camellia of the pair;
A method for imitating a wave f# element described in a patent, characterized in that the above-mentioned chip is then cut.
JP21520383A 1983-11-16 1983-11-16 Manufacture of oscillating element Pending JPS60107909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21520383A JPS60107909A (en) 1983-11-16 1983-11-16 Manufacture of oscillating element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21520383A JPS60107909A (en) 1983-11-16 1983-11-16 Manufacture of oscillating element

Publications (1)

Publication Number Publication Date
JPS60107909A true JPS60107909A (en) 1985-06-13

Family

ID=16668396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21520383A Pending JPS60107909A (en) 1983-11-16 1983-11-16 Manufacture of oscillating element

Country Status (1)

Country Link
JP (1) JPS60107909A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0211008A (en) * 1988-06-29 1990-01-16 Matsushita Electric Ind Co Ltd Piezoelectric resonator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0211008A (en) * 1988-06-29 1990-01-16 Matsushita Electric Ind Co Ltd Piezoelectric resonator

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