JPS60106069A - Recorder of digital signal - Google Patents

Abstract

PURPOSE:To allow data transfer between a host computer and a digital signal recorder even when a data format and a data rate are different from record data by installing small capacity memory between a host computer and large capacity buffer memory. CONSTITUTION:A buffer memory 2 is constituted with a memory 31 having memory banks 32 and 33, a serial/parallel convertor 34 and parallel/serial convertor 35 which are provided on output and input sides of the memory 31, respectively, an external clock CKW, and a buffer controller 36 supplied with a system clock CKS. An interface 5 is constituted with small capacity memory 41, for example, which can store one block data, a memory controller 42, a data size detection circuit 43 and a buffer address controller 44. Thus interface with an external computer can be easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION 1-Industrial Application The present invention relates to a digital signal recording device applied to, for example, a digital data recorder.

``--Background Art and Problems Therewith'' Conventional data recorders merely have the function of recording and reproducing external input, and are not constructed with particular attention to interfacing with an external computer.

Therefore, it was not possible to send a part of the input gage signal to a computer for analysis, or to supply graphics data from the computer to a data recorder for recording.

Therefore, it is conceivable to provide a buffer memory in which recorded data is stored, and to exchange data between this buffer memory and an external computer. However, the data rate and data format of the data from the computer and the input digital signal to the data recorder do not match, and it is necessary to switch between these two types of data and addresses.
()<11() into the memory causes a problem in that the configuration of the selector and the control of the selector become complicated.

1. OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a digital signal recording device that can be easily interfaced with an external computer.

1-Summary of the Invention The present invention comprises a buffer memory in which human-powered digital signals are stored, a recording processor to which the input digital signals read from the backup memory are supplied, and an output of the recording processor on a recording medium. This is a digital signal recording device equipped with a recording head for recording, and a memory for mediating the exchange of data between the sofa memory and an external microprocessor.

"Embodiment" An embodiment in which the present invention is applied to a digital data recorder will be described below. In FIG. 1 showing the overall configuration of this embodiment, numeral 1 indicates an A/D converter to which analog data is supplied.

An external clock CKW is supplied to the A/D converter 1, and one signal is inputted from the 8-bit digital clock A/1 converter 1 to the backup memory 2, for example. Output data of the A/D converter 1 is written into the buffer memory 2 by an external clock CKW, and read from the buffer memory 2 by a system clock CKS from a clock generation circuit 3 inside the data recorder. The external clock CKW is well-controlled and highly accurate to avoid temperature-induced drift. Digital data read from backup memory 2 is supplied to redundant code generation circuit 4.

5 shows the interface. The interface 5 generates a control word during recording, and this control word is supplied to the redundancy code generation circuit 4. An address controller for controlling the address of the buffer memory 2 is provided within the interface 5. The interface 5 also serves as an intermediary for storing data such as graphics status from an external host computer in the buffer memory 2 regardless of the recording operation, and for transferring input digital data from the backup memory 2 to the host computer.

The redundant code generation circuit 4 performs jabbing to convert the order of data into a different order from the original one, using the length of one scan recorded by one scan of the rotary head as a unit, and also performs jabbing to convert the order of data into a different order from the original one. In this method, an error correction code is applied to the data of one scan. As the error correction code, for example, a product code using a Reed-Solomon code as the vertical and horizontal error correction codes can be used. The block address and identification data of the recording data are also generated by the redundant code generation circuit 4 and inserted into each block of recording data.

Output data of redundant code generation circuit 4 is supplied to encoder 6. The encoder 6 performs channel encoding of recording data and inserts a block synchronization signal,
The encoder 6 outputs recording data divided into four channels. As channel encoding, for example, (8-9) conversion can be used to convert 1 x 8 bits to 1 x 9 bits.

The output of each channel of encoder 6 is sent to recording amplifier 7A.
,7B,7C,? D and rotating I lance (not shown)
through rotating heads 8A, 8B, 8C.

8D and recorded on the magnetic tape 9. Processing and processing of digital data read from the buffer memory 2 or the memory of the interface 5 described above is performed by the system clock CKS.

FIG. 2 shows the recording pattern of the magnetic tape 9 in this embodiment. Rotating head "8A, 8B.

8G and 8D scan the magnetic tape 9 wound on the tape guide drum from the bottom to the top, and in one scan, four 1-rank 10A,
10B, 10C, 10D force'-3 cedar is formed.

Along the longitudinal direction of the magnetic tape 9, a sequence number J as an l-rank address is recorded in the first ranks 11A, 11B, and 11C of the magnetic tape 9 and the control track 11C, and a sequence number J as an l-rank address is recorded on the control track 11D. , the signal for the servo is even recorded.

Data processing should be done in units of one scan of data. FIG. 3A shows one scan of recording data output from the redundant code generation circuit 4.

One scan includes 512 blocks from θth to 511th blocks. 32 out of 512 blocks
One block is redundant code, two blocks are control words and the L478 block is digital data. The control word is one block consisting of a sequence number, a data size signal indicating the number of input data in one scan period, and a user's code, and the same word is recorded twice as two blocks. These 512 blocks of recording data are recorded on four tracks at a data rate reduced to 1/4. As shown in FIG. 3B, the block (1) is 128 bytes including a 4-byte CRC code (a type of cyclic code and a redundant code for error detection).

At the beginning of each block, the encoder 6 sends a 2-byte block synchronization signal 5YNC, a 2-byte block address AD, and an identification signal ID as shown in FIG. 3C.
is added.

Rotary heads 8A, 8B, 8C from magnetic tape 9.

The signal reproduced by 8D is transferred to a rotating transformer (not shown).
and reproduction amplifiers 12A, 12B, 12C.

12D to the PLL circuit 13, and the PLL
The circuit 13 extracts a clock from the reproduced data of each track. The output of the PLL circuit 13 is supplied to a decoder 14. The decoder 14 includes a circuit for extracting the linear synchronization signal, a TBC for removing time axis fluctuations, a channel decoder, etc., and reproduced data returned to one channel is obtained as an output of the decoder 14. This reproduced data is supplied to the error correction circuit 15.

The error HJ' tlE circuit 15 includes a de-yaffling circuit that returns the data arrangement to the original order, and a correction circuit that performs vertical and horizontal error correction twice. At the output of the error correction circuit 15, reproduced digital data to which a 1-bit error flag has been added for each sample data is taken out and supplied to a buffer memory 16 and an interface 17. The error flag is at a low level in the case of sample data in which no error is detected or in which the error has been corrected, and is at a high level in the case of sample data on the contrary, that is, Sunnor data containing an error. Among the reproduced data, sample data whose error flag is at a low level, that is, valid sample data is written into the buffer memory 16 and the memory of the interface 11.

Digital data is written into the buffer memory 16, and control words are written into the memory of the interface 11.

This writing is performed using the system clock CKS from the clock generation circuit 3. On the other hand, buffer memory 1
6 and interface 11 are read out using an external clock CKH. The interface 17 is provided with an address controller I roller that controls the address of the backup memory 16. The reproduced digital data read from the buffer memory 16 is supplied to the D/A converter 18, and the external clock CKR
is converted to analog data and output.

This external clock CKR is the same as the external clock CKW used during recording, and is a well-managed and extremely stable lock signal. In addition, the external clocks CKR and CKW are used in the buffer memory 2 and the buffer memory 16 when processing one scan of data.
To avoid overflow, the system clock C
It has a lower frequency than KS.

The interface 11 not only inputs control data during playback, but also acts as an intermediary for uploading playback data with a no-ken number that matches the 7-ken number specified by the user to the host I-computer. Reference numeral 19 denotes a microprocessor provided in the above-mentioned processor that processes data on the recording side and reproduction side, and this microprocessor-19 and the interfaces 5 and 11
A data and address bus 20 is provided therebetween.

21 shows the system controller of this embodiment,
A data and address bus 22 is provided between the system controller 21 and the microprocessor 19;
The system controller 21 is connected to a host computer (not shown). System controller 21
It has a built-in microprocessor, which is associated with a system controller 21, a keyboard 23, and a data file. J24. A CRT display 25 and a Norinta 26 are provided. The system controller 21 controls various operations of a remote control coder of a rotary head type recorder that connects the rotary heads 8A to 8D, the magnetic tape 9, and the like. Furthermore, the keyboard 23
A user's code representing the date, time, data type, etc. is generated by the user's operation.

FIG. 4 shows the configuration of the buffer memory 2 and interface 5 provided on the recording side. Buffer memory 2 is
Memo IJ31 with two memory banks 32 and 33
, a serial-parallel converter 34 and a parallel-serial converter 35 provided on the input side and output side, respectively, and an external clock CK.
It is composed of a buffer controller 36 to which W and a system clock CKS are supplied. The interface 5 includes a memory 41 capable of storing a small capacity, for example, one block of data, a memory controller 42, a data size detection circuit 43, and a buffer address controller 44.
It is composed of. 20D and 20A are a data bus and a here address bus of the microprocessor 19.

Microprocessor 19 via address bus 20A
The address supplied from the memory controller 42 is supplied to the memory controller 42 .

Data bus 20D and recording digital signal input terminal 45
A tristate G4 + G5 + GG + G7 is provided in association with the recording digital signal output terminal 46 and the recording digital signal output terminal 46, respectively. The microprocessor 19 receives commands from the system controller 21, and these tri-stays G1 to G7 are controlled by control signals from the microprocessor 19. When recording,
One of the memory banks 32 and 33 of the memory 31 is set to a write state, and the other is set to a read state;
The write state and read state of the memory banks 32 and 33 are switched for each cycle.

A human input digital signal tristated from an input terminal 45 is applied to one of the memory banks, such as the memory bank 32, which is in a write state by an external clock CKW. During this one scan period, digital signals that have already been written from the memory bank 33 are read out by the seven stem clock CKS. Writing to and reading from the memory 31 is performed, for example, in 8-byte parallel format.

Each of the memory banks 32 and 33 has a capacity capable of storing recordable digital signals (478 blocks x 124 bytes, as described above) in one scan period. When the frequencies of the external clock CKW and the 7-stem clock CKS are both equal, the digital signal is fully written into the memory bank 32 in one scan period so that there is no empty space, and the digital signal is written once from the other memory bank 33. Read out. When the frequency of the external clock CKW is lower than the frequency of the system clock CKS, the number of digital signals written during the scan period decreases, and an empty space is created in the memory bank 32 in which no digital signals are written.

The data size detection circuit 43 detects to which address of the memory bank 32 (or 33) a digital signal has been written during the scan period. This detected address bus size signal is supplied to the microprocessor 19 via the data bus 20D. This data size signal 7j is supplied from the micro 70 processor 19 to the buffer address controller 44, and is used to control the digital signals 11, 7, without reading out the digital signal (+i;;).

When reading a digital signal from the memory bank 32 (or 33), the read address changes from the start address to the end address and then again to the start address '1'.
・Return to address tc and change to end address.

This +iJG output operation is performed over the period of (1) scan. Therefore, when there is space in the memory bank 32 (or 33) within one scan period,
At least some of the digital signals are read out twice and recorded on the magnetic tape 9 twice.

A digital signal read out from one memory bank of the memory 31 is converted back to bi1-normal data by the parallel-to-serial conversion circuit 35, and taken out to the output terminal 46 via the tristate circuit G6.

The memory 41 also stores the aforementioned data size signal and Norial number from the microprocessor 19.

A control word such as a user's code formed by the system controller 21 is supplied via the data bus 20D and the tri-state circuit G1, and a write address is supplied to the memory controller 4 via the address bus 20A.
/stem chrono/' CKS writes the hunt roll word into memory 41. and,
The contents of the memory 41 are read twice in the first and second block periods of one scan period,
It is taken out to the output terminal 46 via the tri-stay I/circuit G2. As shown in FIG. 5, during the first two blocks of one scan period, the control signal related to tristate circuit G2 is set to low level, and the control signal related to tristate circuit G6 is set to high level, so that the tristate Circuit G2 is activated. In the remaining period of one scan period, the control signal is reversed and is in a tristate state, and a digital signal consisting of two consecutive blocks of control words and 478 blocks of digital signals is obtained at the output terminal 46. .

"Irrespective of the two series of recording operations, data is sent from the external host computer to the buffer memory 2 via the microprocessor and microprocessor 19 of the system controller 21.
Digital signals can be loaded into the memory 31 of the computer and recorded on the magnetic tape 9.

At this time, data is transferred to the microprocessor of the postcomputer/stem controller 21, and then sent to the microprocessor 19 via the data and address bus 22.
Data is transferred from the microprocessor 19 to the memory 41 using the data bus 20D and
- Data is transferred using circuit G+ and address bus 20A. Data is transferred from the memory 41 to the memory 31 based on the system clock CKS with only the tristate circuit G4 in the active state. The memory address and address at which the data of the memory 41 is to be written are instructed from the microprocessor 19 to the memory address controller 44.

The data in the memory 31 of the buffer memory 2 can also be transferred to an external host computer.

In this case, the address corresponding to the block of digital signals to be pulled up to the buffer address controller 1-roller 44 is sent from the microprocessor 19 to the data bus 2.
Supplied via 0D.

Then, only the 1-right state circuit G7 is activated, and one designated block of tickle signals is transferred to the memory 41. Next, the digital signal read from the memory 41 is placed on the data bus 20D via the active tristate circuit G5, and is supplied to the microprocessor 19. Digital signals are transferred from the microprocessor 19 to the host computer via the microprocessor of the system controller 21.

FIG. 6 shows the configuration of the buffer memory 16 and interface 17 provided on the playback side. Buffer memory 1
6 consists of a memory 51 having two memory banks 52 and 53, a serial-to-parallel converter 54 and a parallel-to-serial converter 55 provided on its input and output sides, respectively, and a buffer controller 56. . The interface 1T has a memory 61, !, which has a capacity that can store one block of data. :． A memory controller 62, a buffer address controller 6, a data bus 20D, and an input terminal 6 for playback tick/cle signals.
5 and 11f raw digital signal output terminal 66, respectively, tri-stay I circuit Gll + G12 + G
I3+ G14+ GI5+ GI6+ G17 are provided. Reproduction digital No. 111 has a unit of 9 bits in which a 1-bit error flag is added to 1 byte of data.

During playback operation, tri-state circuits G11 and G16
is in the active state, and the tri-stay 1 and the circuit G1□ are in the active state during the block period of the control word. Among the control words and reproduced digital signals, only valid data whose error flag is determined to be at a low level, that is, there is no error, are written into the memories 51 and 61. The same control word is recorded over at least two blocks;
Digital signals are also recorded twice when the frequency of the external clock CKW is lower than the frequency of the stem clock CKS, so in addition to error correction using an error correction code, most of the valid data can be reproduced. .

The memory banks 52 and 53 of the memory 51 are switched between a write state and a read state every scan period. When the reproduced digital signal is supplied, valid data of the control words of the first two blocks is written to the memory 61, and valid data of the reproduced digital signals included in the next block and subsequent blocks is written to the memory 51. written to one memory bank. The control word taken into the memory 61 is supplied to the microprocessor 19 via the tri-state circuit GI4 and the data bus 20D, and the end address in one scan determined by the data size signal in the control word is sent from the microprocessor 19 to the buffer. It is supplied to the address controller 64. As a result, the IIf raw digital signal present during one scan is correctly written to one memory bank of the memory 51, and is read out by the external clock CKR during the next one scan period, and the IIf raw digital signal that exists during one scan is read out by the external clock CKR, and the IIf raw digital signal that exists during one scan is correctly written to one memory bank of the memory 51. The signal is taken out to the output terminal 66 through the terminal. The external clock CKR is a clock having the same frequency as CKW, and a continuous digital signal can be taken out from the output terminal 66.

The user can send a digital signal of a designated serial number to an external host computer by operating keys on the keyboard 23. When the serial number in the reproduced control word matches the specified serial number, a command from the microprocessor 19 inhibits the write operation of the memory 51, and the contents of one memory bank are repeatedly read out. be done. This read digital signal is transferred block by block to the memory 61 via the 1-right state circuit G17. The data stored in this memory 61 is transferred to the microprocessor 19 via the tri-state circuit GI4 using the data bus 20D and address bus 20A of the microprocessor 19. The microprocessor 19 transfers this retrieved data to the microprocessor K of the system controller 21, and further, the system controller 210 microprocessor transfers the data to the host computer according to its request.

Data from the host computer is stored in the buffer memory 51.
You can also write to . At this time, the tristate circuit G15 is activated, and the microprocessor 1
One block of data is transferred to the memory 61 using the data bus 20D and address bus 20A of 9, and the address to be written is transferred to the buffer address controller 64.
supplied to next,! - The license state circuit G13 is activated and the contents of the memory 61 are transferred to the memory 51.

11 Application Example The present invention is applicable not only to a rotary head type recording device but also to a digital signal recording device using a fixed head.

1. A plurality of buffer memories capable of storing reproduction data of different scans continuously or intermittently may be prepared on the 1f raw side, and these buffer memories may be used selectively.

1. Effects of the Invention] According to this invention, there is a digital signal recording device that can record data from an external host computer and send a part of the digital signal to be recorded to the host computer. The device can be realized. In this invention, a small-capacity memory is provided as a middle stage between the host I/computer and the large-capacity buffer memory, and data transfer between this memory and the buffer memory is performed based on the system clock. Even if the data format or data rate is different from the recorded data, it can be easily configured and controlled by an external boss! - Data can be transferred between a computer and a Digital E recording device.

The present invention makes it possible to record graphics data generated by a host computer, extract digital data, analyze it, and file it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a route map showing a trunk pattern according to an embodiment of the present invention, FIG. 3 is a route map showing a structure of a recorded signal according to an embodiment of the present invention, and FIGS. FIG. 6 is a block diagram and time chart showing a part of the structure on the recording side in an embodiment of the present invention, and FIG. 6 is a block diagram showing a part of the structure on the playback side in an embodiment of the present invention. 2.16・・・・・・・・・Buffer memory, 5.17
...-...Interface, 9...-
...Magnetic tape, 31゜51 ...Memory constituting the buffer memory, 41.61-...
-Memory within the interface. Agent Tadashi Sugiura Figure 2 Figure 3 Figure 4 Figure 0 Figure 5

Claims (1)

[Claims] a buffer memory in which an input digital signal is stored; a recording processor to which the input digital signal read from the buffer memory is supplied; a recording head for recording the output of the recording processor on a recording medium; A digital signal recording device equipped with a memory that mediates data exchange with an external microprocessor.