JPS60105385A - Device for altering time base of digital information signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to techniques for changing the time axis (time reference axis) of a temporally varying signal, and more specifically to techniques for changing the time axis (time reference axis) of a temporally varying signal.
The present invention relates to time varying techniques particularly suited for electronically correcting undesired time base differences in time varying signals.

During the processing of time-varying electrical signals for signal conversion, analysis, or correction, it is often necessary to change or compensate for the time axis of the signal. For example, signal timebase compensation is commonly used to correct for undesired timebase differences in signals that have repetitive timebase synchronization components. Changing the signal time base to correct for undesired time base differences occurs when the signal is between different regions, such as occurs when the signal is recorded on or played back on magnetic tape or other forms of recording media. This is especially important when undergoing transformations. During the recording and playback process, the time function of the signal is converted to a spatial function and then back to a time function. Timing or time base errors are often introduced into a signal as it undergoes a transformation. Such time base errors, which are dynamic or in other words temporally variable, prevent the achievement of the required transient-free and temporally stable signal reproduction required in high-resolution signal processing devices. For example, generation of temporally stable signals is desired in all television signal processing equipment, and highly stable generation requirements are desired in equipment used to prepare television signals for public transmission. .

Two techniques are used to correct undesired time base errors in signals reproduced from recording media: electro/mechanical and electronic. Electromechanical techniques are used to correct large time base errors and accomplish such corrections by synchronizing the operation of signal recording and reproducing equipment. Electronic techniques are used to correct small residual time base errors not corrected by electro/mechanical devices by displacing the signal in time after reproduction and to accomplish such correction.

The present invention is concerned with electronic time base error correction techniques.

Traditionally, electronic signal time base changing devices have used adjustable time delays inserted into the signal path to correct for time base errors. In such devices, a time base error is measured and the amount of time delay inserted into the signal path is adjusted to compensate for and correct the measured time base error. One particular type of device that is widely used uses lumped inductors and voltage variable capacitance diodes interconnected in a delay line configuration.

A voltage corresponding to the measured time base error is applied to this variable diode to determine the delay necessary to correct the time base error. See US Pat. No. 3,202,769 for a voltage variable delay linear signal timebase changer.

In another type of electronic signal time base changing device, multiple fixed delay lines or a single delay line with a series of taps spaced along it are combined by electronic switches. arranged in a shape. Timebase errors are corrected by operating switches in accordance with the measured error to selectively insert the necessary corrective delay lines into the signal path. A fixed delay linear signal time base changing device is described in U.S. Pat. No. 3,763,317, and a tapped delay linear signal time base changing device is described in U.S. Pat. No. 3,748.
, No. 368.

In recent years, digital delay devices, such as clocked storage devices, have been used in devices for correcting time base errors in analog signals. In this digital device, the analog signal being corrected is digitized, corrected and reconstructed. Correction is accomplished by loading or writing this digitized signal to an adjustable storage register at a fixed frequency determined by the frequency of the reference clock signal. This storage register is operated to correct the time base error by reading signals from the register at a higher or lower frequency that is adjusted according to the time base error. This constant write rate and variable successive rate technique cannot handle large discontinuities or step-by-step time changes in the signal. In magnetic tape recorders, such progressive time base changes are usually caused by irregularities in their operation, and most commonly occur when switching between magnetic transducer heads.

For signal time base modification devices, especially those arranged to eliminate time base errors and provide a high degree of signal time base stability, a coarse time base correction device and a fine time base correction device are cascaded. It is customary. A voltage variable delay line device was used to provide the desired fine time base correction, and a switched delay line device was used to provide the coarse time base correction. Since all such delay line devices are analog devices, they are prone to drift and have other disadvantageous characteristics of analog devices. Gradual time base changes that occur as a result of irregularities in tape recorder operation may affect signal processing operational performance because such time base error correction devices do not have the ability to accommodate gradual changes. This often results in errors or costly interruptions. Furthermore, when it is necessary to correct a large range of time base errors, a large and complex correction device is required.

Therefore, there would be considerable advantages in utilizing a technique for performing signal time base compensation that allows all time base changes, including incremental ones, to be made without error. It is also possible to change the signal time base by any fraction of the known step amount necessary to bring the signal within a desired time base reference of an integer known step amount, and then move the signal to the desired time base. Additional benefits to the performance of such signal time base compensation can be provided by varying the signal time base by one such integer known step amount to adjust to.

A feature of the present invention is the use of digital techniques for signal timeline adjustment, which makes it possible to use digital circuits that are much cheaper to construct and maintain than analog circuits. Another feature of the invention is that time base compensation can be performed without the need for analog measurements of the desired amount of compensation, thereby avoiding all of the disadvantageous characteristics of analog circuits. Another object of the present invention is to temporarily store signals in a time buffer at times that are adjusted according to desired time base changes while maintaining a fixed storage readout time relative to an established time base reference. is to retime the signal by a fraction of the known step amount.

Another feature of the present invention is to make further incremental changes in the time base of the signal in accordance with desired time base changes while maintaining a fixed storage write time relative to an established time base reference. This can be done without error by adjusting the different memory readout times. Yet another feature of the invention is that a change in the time axis of a signal that is larger than one major division of the time axis defined by the period of one cycle of a time axis component of the signal is first performed by changing the time axis of the signal to this major time axis. accomplished by changing the signal by any desired amount corresponding to the fractional amount of the subdivision, and then further incrementally changing the signal by any desired amount corresponding to an integer multiple of the major time axis subdivision. It is possible. Yet another feature of the present invention is the use of a guidance control signal to effect the time base change which greatly reduces the effects of noise.

These and other features of the invention find particular advantageous application in eliminating time base errors in television signals reproduced from video recording devices.

According to the invention, the information signal whose time axis is to be modified or compensated is sampled in order to obtain a representative part of this signal.

This information signal must include or be provided with time base components that appear at least at spaced points in the information signal. A timing or time base reference, such as a clock signal having a frequency that remains fixed relative to the nominal frequency of the time base component associated with the uncompensated information signal, is first used to control the sampling time and frequency. This reference clock signal must be generated for the occurrence of the information signal such that at least a portion of the time domain component is sampled multiple times. Such sampling must be sufficient to make it possible to reconstruct the time axis component from a representative portion thereof.

When the time base component is sampled under the control of the reference clock signal, a representative sample is stored and subsequently used to regenerate a representative portion of the time base component. It is frequency stable and phase coherent with the original time domain component associated with the uncompensated information signal. An information lock signal is derived from this regenerated time component such that its frequency and phase characteristics are constant relative to those of the regenerated time component and thus the original time component. During the period of the information signal following the portion of the time base component that derives the information clock signal, the derived information clock signal is used to time additional processing of the information signal to introduce a desired amount of time base change. It will be done.

The use of a derived clock signal obtained in the manner described above is useful for further processing an information signal, such as a television signal, for the purpose of removing timing differences or time base errors that are common in such signals. It is especially advantageous for changing. When using the technique of the present invention to eliminate time base errors that occur in television signals, the frequency and phase of the reference clock signal are kept fixed, and the derived clock signal is the same as the information signal that derived the information clock signal. It is used to time the further sampling of the information signal during the period following the portion of the time axis component. To remove time base errors from the color television signal, an information clock signal is obtained from the re-occurrence of the color synchronization burst that occurs at the beginning of each horizontal scan line period of the composite color television signal. The clock signal thus obtained is used to time the sampling of the video information signal components following the synchronization period located at the beginning of each horizontal scan line of the television signal.

Following further sampling, a representative portion of the resulting video signal is written to a clock isolator or time buffer at a time determined by the resulting clock signal.

These video signal representative portions are then read from the buffer at times determined by a fixed frequency and phase reference clock signal.

In this manner, the time buffer acts to realign these video signal representative portions with respect to the reference clock signal. The original form of the video signal can be reconstructed from this realigned and sampled representative portion read from the buffer.

The use of a clock signal obtained from the regeneration of the time axis component of the information signal to time the further processing, ie sampling, of the information signal is one of the basic features of the invention which facilitates changes in the signal time axis. It is. As mentioned above, obtaining the information clock signal in this way ensures that the frequency and phase of the induced clock signal are always accurately related to those of the time-base components contained in the information signal. Guarantee.

Therefore, the time axis of the induced clock signal follows changes in the time axis relationship of the information signal and the timing reference. Because the time axis of the induced clock signal is precisely locked to the time axis of the information signal, and because the induced clock signal is used to control the further sampling of the information signal, the information signal is always in time with the information signal and the timing reference. Further samples are taken at the same point during the period regardless of axis relationship. A change in the temporal relationship of the information signal and the timing reference does not change the sampling point within the period of the information signal. In this manner, the sampled information signal can be retimed with respect to any desired time base, regardless of changes in the time base relationship of the information signal and the timing reference. As will be readily apparent upon consideration of the following detailed description of a preferred embodiment of the signal time base modification technique of the present invention:
The derivation of the information clock signal and its use for further sampling of the information signal makes it possible to realize significant advantages in the implementation of this technique, the most important of which is high reliability. The purpose of this invention is to accurately correct time axis errors in television signals.

Usually, the time axis component of the information signal is a simple periodic signal. However, an information signal such as a television signal has a number of time base components arranged to define the main and sub-periods of the information signal and the time base conditions within the period. Since such time axis components have different frequencies, it is possible in certain situations to ensure that the sub-periods are correctly aligned with respect to the underlying reference even if the higher-order periods are not. be. The highest frequency time base component is selected to derive the information clock signal to avoid adverse effects that may be caused by a false indication of correct time base alignment. Signal time base compensation of up to one cycle of the highest frequency time base component is automatically provided by the technique of using this guided information clock signal to further sample the information signal. When signal time base compensation of more than one cycle of the highest frequency time base component is required to achieve correct time base alignment, the information signal is further examined to determine the number of total cycles and this is further modified. the time axis must be aligned correctly. This required further modification is accomplished by storing the sampled representative portion in memory for a number of cycles corresponding to the determination. Preferably, this further modification is performed after the sampled representative portion has passed through a time buffer.

In addition to changing the time base of an information signal to eliminate undesired time base differences, signal time base compensation according to the present invention can be used to introduce desired time base changes to the information signal. Such a desired time base change is introduced by changing the time base of the reference clock signal according to the desired time base change. In other respects, the signal time base compensation of the present invention is performed in the same manner as described above for time base error removal.

Changing the time axis of the reference clock signal causes a change in the time axis relationship of the time axis components included in the reference clock signal and information. As mentioned above, such a relative time base change introduces an equivalent time base difference between the time base of the sampling of the information signal and the time base of the time scaled reference clock signal. Therefore, reading a sample of the information signal from the time buffer at a time defined by the time-altered reference clock signal results in re-timing the information signal with respect to the modified reference signal, thereby aligning the information signal with the desired time axis. Resulting in the introduction of changes.

As can be seen from the foregoing, the signal time base compensation according to the invention can be easily applied to digitization and thus presents advantages that can be obtained by utilizing digital circuits. Furthermore, the time axis of the information signal is first changed by a known time increment, i.e., by a major time axis division (i.e., a fraction thereof), and then by an arbitrary increment equal to an integer multiple of such increment, regardless of the magnitude of the time axis change. The ability to change the time base of an information signal by an amount of 100 kHz has the advantage of avoiding the limitations associated with cascading analog time base changing devices.

Preferred embodiments of the present invention will be described below with reference to the drawings.

A signal time base compensator 110 according to the present invention, as shown in FIG. shown as being configured to remove. However, the principles of the present invention apply to other signal time corrections such as correction of time base errors present in other time-varying information signals, removal of relative time base differences of the signals, and intentional modification of the time base of the signal. It should be understood that it is equally applicable to performing axial compensation. Particularly with reference to FIG.
/D converter) 111, which operates to produce at its output 112 a digital signal in the form of a pulse code modulation of the television signal. This digital signal is further processed so that it is finally provided to a decoding digital/analog converter (hereinafter referred to as a D/A converter) 113 without any errors, ie, with the errors removed. D
/A converter 113 reproduces the television signal in analog form at output 114. Since the synchronization component included in the television signal output from the D/A converter 113 is usually not in a strong form and contains undesirable excessive components as a result of passing through the compensator 110, the television signal is transmitted to the video recorder. Output processing device 11 of a type commonly used in
6. Such processing unit 116 is operative to remove the synchronization component from the incoming television signal and insert therein a new correctly shaped and timed synchronization component to form the desired composite television signal at its output 117. do.

In the compensation device 110 of the invention, the encoded A/D converter 111 outputs 1
12 to generate a multiple bit word signal of the incoming signal.

Converter 111 is clocked to sample the instantaneous analog amplitude of the incoming television signal so that a series of binary words are generated at its output 112. Each word consists of a number of binary bits which together represent one particular amplitude level in binary form.

This analog-to-digital conversion operation is commonly referred to as pulse code modulation of the incoming signal. The inverse of this operation is performed by decoding D/A converter 113. Decryption D/
A converter 113 has these two inputs on line 119.
generating and processing a reconstructed or decoded analog television signal that receives the hex-encoded word and is provided to output processing unit 116 in response to a series of reference clock signals received by lines 121 and 122; Device 11
6 provides this corrected television signal at output 117.

In accordance with the present invention, time base compensation is achieved by inducing a clock signal from a time base component contained in a television signal such that the clock time of the derived clock signal is coherent with the time base component. This derived clock signal is used to clock the A/D converter 111 to sample the uncorrected television signal and encode the television signal into a digital binary word signal. After encoding, the digitized television signal is time-buffered and decoded in D/A converter 113 by a clock signal that is coherent and time-locked to a reference time base signal, such as a reference color subcarrier. It will be transformed. As a result of such buffering and decoding, the decoded television signal is brought into phase with the reference color subcarrier.

For color television signals, accurate timebase correction is achieved by deriving a clock signal associated with the information signal from a color synchronization burst timebase component located on the back porch of each horizontal scan line blanking period. Ru. This induction is applied to the input of the recirculating digital storage device 123.
This is achieved by combining the binary word signal portions of one or more cycle portions of the color burst of the signal obtained at the output 112 of the /D converter 111. Storage 123 provides digital storage of a plurality of binary words corresponding to the amplitude level of the signal color burst at the sample time. By storing the binary words obtained during sampling of the color burst of the signal, such that a continuous signal identical to the color burst of the uncorrected television signal can be generated continuously over the duration of the color burst of the signal. Sufficient information is stored in storage 123 to repeatedly regenerate a full cycle of color bursts. The derived clock signal is obtained by further processing this continuously regenerated color burst signal, and it is used to digitize the rest of the horizontal scan lines of the regenerated television signal. used.

This continuous signal, and thus the derived clock signal regenerated from the color burst samples stored in recirculable storage δ 123, is maintained in phase with the color burst and therefore the uncorrected television signal by the A/D converter. 11
1 is clocked first during the sampling of the color burst of the television signal and during the storage of the resulting samples by a clock signal that is coherent or in lock time with the reference clock signal. A/D converter 111 will therefore be clocked by two clock signals on line 118.

Initial clocking is preferably performed during a sampling and storage mode period lasting for a color burst time base component of several cycles. During this first mode,
The clock input (CL) of the A/D converter 111 is connected to line 1.
18 receives a clock signal clocked in the same phase as the reference clock signal. A/D converter 111 is clocked by a second induced clock signal received on line 118 during a recirculation mode, which mode lasts for the remainder of the horizontal scan line period after the first clocking. . For these two modes of operation, the line 11
8 to the clock output line 122 of the X3 reference clock source 128;
will be provided. The switching device 126 switches the line 118 to the line 12.
7 is operable to set a second or recirculating state connected to the inductive clock signal provided by the digital storage circuit 129 via 7. In this recirculation mode, switching device 126 connects the clock input (CL) of A/D converter 111 to x3 signal clock circuit 131 to provide a clock output for storage circuit 129.

The x3 signal clock circuit 131 responds to the output of the D/A converter 133 via the bandpass filter 132.

D/A converter 133 converts or reconstructs the binary word portion of the signal color burst recycled within recirculable storage 123 into analog form. The signal obtained from D/A converter 133 thus appears as a continuous unfiltered replica of the input signal time domain component, which in this example is a sinusoidal color burst of the television signal. The bandpass filter 132 is set to give a center frequency equal to that of the color burst of the signal being corrected;
This is 3 for the NTSC standardized color television signal.
．． It has a frequency of 58 MHz. filter 132
/A converter 133 output and x3 signal clock circuit 131
It has been found to be advantageous to recover the color burst frequency after various conversion and digital storage operations by connecting between the input to the . If portions of multiple signal color burst cycles are sampled and stored in storage 123 so as to regenerate the derived clock signal, filter 132 detects any signals contained in this recirculated signal color burst. The noise is averaged over a large number of storage cycles, thereby improving the timing accuracy of the induced clock signal.

As mentioned above, the switching device 126 of the switching means 124 is normally in the second state shown, that is, the recirculation mode state, and connects the X3 signal clock circuit 131 to the clock input (CL) of the A/D converter 111. and time the encoding of the uncorrected television signal with recirculated color burst samples obtained from the signal. In order to operate the switching device 126 to set the other state, the first state, the sampling and storage mode state, the switching means 124 includes a circuit for detecting the occurrence of a color burst time component in the television signal and a circuit for detecting the occurrence of a color burst time base component in the television signal. includes a device (i.e., switching device 126) that responds accordingly. Specifically, a sync separator 134 is provided to separate the occurrence of each horizontal sync pulse (signal H) that appears during the blanking interval of each horizontal scan line of the television signal at the input of the compensator 1. To detect. The output of this separation device is coupled to the input of a switched control pulse generator 136. When the leading edge of the horizontal sync pulse is detected, the separator 134 commands the pulse generator 136. After a period of about 6 microseconds, the pulse generator 136 switches the switching device 1
A pulse lasting approximately 2 microseconds is generated to activate 26 into its sampling and storage mode. In this way, in response to the occurrence of a horizontal synchronization pulse on the input to A/D converter 111, separator 134 and pulse generator 136 switch 126 to convert the encoded x3 reference clock signal to the clock signal of converter 111. input (CL), and converter 111 responsively digitizes the signal color burst for a selected number of cycles. The timing of the operation of separator 134 and pulse generator 136 in this embodiment is such that switching device 126 is operated in the sampling and storage mode during periods that are in the middle of the color burst period. It is designed to be adapted. It is desirable to sample and store the digital portion of the color burst of the signal as it occurs in the middle of the color burst period, since this period is the most accurate representation of the color sync burst frequency. This is because it is highly reliable. In addition, due to the small change in position of the color burst on the back porch of the horizontal blanking period, there is less possibility of introducing errors in the derivation of the clock signal related to the information signal.

A burst detector 137 is connected to the input of the compensator 110 to condition the recirculable storage 123 to store a five-cycle color burst digital portion. When a color burst occurs in an incoming television signal,
Burst detector 137 generates a command signal on line 138 that extends to the write enable input (WE) of the digital recirculable storage device. This command signal causes memory device 124 to write the multi-bit binary word appearing at output 112 from A/D converter 111. An actual write or store operation occurs at each reference clock time defined by the clock signal input from the x3 reference clock generator 128 to the storage device 123. The subsequent operation of recirculable storage 123 will be best understood by reference to both FIGS. 1 and 2.

Referring to FIG. 2, storage device 123 includes a random access memory 139 having a write control input (W) and an address control input (A).

Multiple bits 2 at output 112 of A/D converter 111
A binary word input is connected for receiving a binary word. 2 to generate a recirculating digital signal on line 140.
A forward word output is provided. Address generator 141
memory 139 according to an address signal generated on connecting line 142 in response to the x3 reference clock signal on line 122.
Generates address signals for writing to and reading from. A write clock generator 143 is included within storage device 123 and is responsive to a command signal on line 138 from burst detector 137 . This command signal sets write clock generator 143 to line 144 to the write enable input (W) of random access memory 139 each time a x3 reference clock signal is received from line 122.
A write enable signal is generated via the write enable signal. When the write enable signal is received by random access memory 139, the binary word generated by A/D converter 111 should be stored (written) to memory 139.
3 also includes a counter 145 responsive to a command signal received at the RESET (R) input coupled to line 138 from burst detector 137. This command signal resets counter 145 to count the address signals generated by address generator 141. Counter 145 is also reset by an internally generated command signal as described below. A reset command signal is generated on line 146 each time counter 145 is reset. The first reset command signal generated following the command signal provided on line 138 by burst detector 137 causes write clock generator 143 to be reset by resetting write clock generator 143 until the next command signal is generated by burst detector 137. ,
The previously enabled write clock generator 143 is disabled.

In this manner, random access memory 139 is prevented from receiving the binary word portion of the television signal after receiving the 15 samples of the color burst. Counter 145 also serves to recirculate address generator 141. Each time address generator 141 generates an address signal, enabled counter 145 is activated on line 12.
2 and examines the address signal generated by the address generator 141 and received at its data (D) via line 148. Counter 145 connects address generator 141 via line 146 when it detects the occurrence of the last of the 15 address signals generated by address generator 141.
Generates a heli-set command signal. Counter 145 also uses this reset command signal internally to reset itself and re-examine the address signal generated by generator 141. In this way, the address generator 141
is sequentially cycled across 15 address signals to identify locations in random access memory 139 that store 15 multi-bit binary words representing five sampled cycle portions of the signal color burst. A further explanation of the operation of recirculable storage device 123 is provided in conjunction with a description of the actual operating sequence of compensator 110.

In selecting the frequency at which the incoming information signal must be sampled, the well-known sampling theorem states that the clocking or sampling frequency must be at least twice the maximum signal frequency at which the signal will pass through the system without substantial loss of quality. Must. Furthermore, the clocking frequency and the storage capacity of the random access memory 139 are such that the number of digitized samples stored in the random access memory 139 is equivalent to an integer multiple of the total cycle of the time domain component of the signal, in other words, the number of digitized samples stored in the random access memory 139 is It must be chosen to be equal to the number of samples per cycle or period multiplied by an integer multiple of cycles. With this selection of clocking frequency and storage capacity, the random access memory 139 is responsible for an integer multiple of the digital portion of a full cycle of the timing component of the signal, which when recycled is in the recirculation mode. This results in the generation of a continuous clock signal. In the case of color television signals, both the storage capacity and the sampling frequency criteria are advantageously selected such that the encoded clock signal has a frequency three times the color burst frequency and by storing 15 samples of the color burst. Satisfied. Therefore, in this example, the X3 signal clock circuit 131 includes a frequency multiplier for multiplying the continuously regenerated color burst signal generated by the storage device 123, the D/A converter 133, and the bandpass filter 132 by 3. Configure. The frequency of the encoded clock signal used during the sampling and storage modes must be equal to the established encoding frequency for each purpose, but the phase may differ from the induced clock signal according to the time base error of the signal being compensated. Good things are recognized.

In the embodiment of FIG. 1, the basic reference time base signal is, for example, a reference color subcarrier derived from a studio reference signal source for synchronizing all of the studio equipment for broadcast purposes. . This reference color subcarrier is provided to a reference signal processor 148. This processing device is a common component that compensates for the fixed delays present in cables etc.
(terminating 1ine) produces the necessary phase change for the reference signal for the European color system. The output of processor 148 provides the basic time base signal upon which compensator 110 acts to compensate the incoming television signal. Because an x3 reference clock signal is required, the frequency of this reference time base signal is tripled by a frequency multiplier included in the x3 reference clock generator 128.

Since the X1 reference clock signal is also required by the compensator 110, the x11 reference clock generator 149 receives the reference time base signal from the processor 148 and outputs this
11 reference clock signal is generated.

Following the aforementioned selection of encoding and decoding clock frequencies, A/D converter 111 generates a separate binary word at each clock time that occurs during a period equal to one cycle of the color burst. perform the functions to be performed. In this embodiment, A/D converter 111 is designed to generate one 8-bit word at each clock time, each 8-bit word having an amplitude of 0 to 256 to provide a digital signal of the incoming television signal. Give level capacity. Therefore, recirculable digital storage 123
has a capacity of 15 words, each word consisting of 8 bits. Since there are three sampling points for each cycle of a color burst, random access memory 139 of storage device 123 can store all five cycles of a digitally represented color burst.

In operation, memory 139 is commanded by write clock generator 143 (when a burst occurs) to write a 2 microsecond pulse to the line while switching control pulse generator 136 generates a 2 microsecond pulse in response to the detection of a horizontal sync pulse. The binary word that occurs at the output 112 of A/D converter 111 on each x33 reference clock signal received via 122 is written or stored. Referring to FIG. 2, address generator 141
memory 13 in response to each of the x3 reference clock pulses.
Each newly accessed word store receives the instantaneous state bits of the binary word at output 112. Pulse generator 136
The 2 microsecond pulse emitted by the switching device 12
6 into its sampling and storage mode state, which provides the x33 reference clock signal on line 122 to A/D converter 111 to clock it.

The storage operation is performed by detecting, via line 147, the 15th address generated by address generator 141 following the generation of a 2 microsecond pulse and generating a reset command signal to write clock generator 143. The process is terminated after five cycles of digitized color bursts have been stored by counter 145. This reset command signal disables write clock generator 143, thereby stopping applying the write enable signal to random access memory 139.

Following termination of the sample and store mode, address generator 141 continues to access memory 139 in response to the x33 reference clock signal on line 122, repeating in sequence the same 15 word locations accessed during the write operation. . This causes the stored 8-bit words to be read out sequentially via output line 140 to D/A converter 133.

Memory 139 is permanently placed in a read mode so that the stored binary words are continuously read out via line 140. The successive function is activated when new digital information received from the A/D converter 111 is stored by the operation of the bypass switch 151.

Switch 151 has two inputs and one output.

One input of the shunt switch 151 is connected by a line 153 to the output of the random access memory 1:39, and the other input is connected by a shunt path 154 to the line 112 of the input of the storage device 123. During sampling and storage modes, write clock generator 143 is set to provide a write enable signal so that bypass switch 15
1 to connect to lines 112 and 140;
This allows the binary word being stored in memory 139 to be passed directly to the output. At the end of the sampling and storage mode, write clock generator 143 is disabled, thus switching switch 151 to output line 15 of memory 139.
3 is left coupled to line 140.

Switch 151 remains in this state during the entire recirculation mode to allow the stored color burst word to be coupled to D/A converter 133 for inducing an information related clock signal. The provision of bypass switch 151 allows the x3 clock signal circuit to be ready to generate an inductive x3 clock signal.

Address generator 141 and counter 1 in recirculation mode
45 work together to have the same address order (sequence)
to cause repeated generation of This occurs in memory 13 for the entire remainder of the horizontal scan line period following the color burst.
The stored binary words in 9 are read out repeatedly in this order.

Figures 3A and 3B illustrate how the induced clock signal is generated to be in phase with the time component of the information signal from which it was induced.

FIG. 3A shows the situation that would exist if the incoming color television signal were free of errors. In the figure, 1"@2#, "3#, and "1" indicate the timing of the X3 reference clock, the upper waveform is the color burst waveform, the next row is the sampled value with the X mark, and the 3rd and 4th row Each row shows a recycled color burst and its X3 waveform. During sampling and storage mode, X3
The reference clock causes the sampling of the signal color burst within A/D converter 111 and the storage of the sample values in recirculable storage 123. Since there is no error in the incoming television signal, the first sample of each cycle of the color burst of the signal at timing position "1" in the diagram occurs at the beginning of the color burst cycle. Storage device 12
When the 15 words stored in 3 are recirculated, the output of filter 132 will be in phase with the color burst contained in the incoming television signal. When a time base error is present in the incoming television signal, as shown in FIG. 3B, the sample values represented by the binary words obtained from A/D converter 111 will be different. This difference occurs because there is a time base difference between the reference time base signal and the incoming television signal, and therefore between sample points during the color burst cycle. When the 15 words stored in storage device 123 are recycled,
The regenerated color burst signal output from filter 132 is in phase with the color burst contained in the incoming television signal. Therefore, the clock signal derived from the filter output is always in phase with the time axis component included in the television signal, regardless of any time axis changes or errors that may occur in the television signal.

Although a random access memory, an address generator, and a counter were used as recirculable storage 123 in this embodiment, it should be understood that other digital storage circuits could be used instead. For example, a recirculating shift register can serve as the storage device 123, as will be understood by those skilled in the art.

In order to avoid errors in the re-alignment of the digital representative portion of the television signal output from the A/D converter 111 in a simplified configuration when in recirculation mode, a time buffer 156 is used, which Word serial/3 word parallel converter 157 and complementary 3 word parallel/3 word parallel converter 157 at its output.
It has a one word serial converter 158. Transducers 157 and 158 are shown in FIG.

The consecutive binary words produced at output 112 are fed into a serial-in parallel-out converter 157. This converter 1
57 clocks each of a series of binary words at three times the clock frequency of the recirculating signal color burst by applying clock pulses from an X3 clock source available on line 118 to the clock input (CL) of this converter. receive.

Converter 157 converts 3 of the binary words generated at output 112
a type configured to store one in series, and each new word added to this converter shifts out the last word so that the converter is always filled with three complete binary words. belongs to. This serially loaded information is stored in a clock separator (isolator) 163 contained in a time buffer 156.
(see FIG. 4) and is transferred in parallel to converter 158. During each scan line period of the input television signal, the transfer time to the clock separator 163 is x1 signal clock circuit 1
59 (see FIGS. 1 and 4) at a clock time defined by a clock pulse generated by the 59 (see FIGS. 1 and 4). The x1 signal clock circuit is connected to the output of bandpass filter 132 to generate clock pulses at the recirculating color burst frequency, which is the frequency of the color burst as it occurs at the beginning of the scan line period. Specifically, the x1 signal clock circuit 159 limits the filter output and uses the positive leading edge of the square waveform generated therefrom to generate clock pulses. Each positive transition leading edge of this limited reoccurrence color burst identifies the beginning of a cycle of color bursts. x1 signal clock circuit 159 is connected to time buffer 156 via line 161. In this manner, clock separator 163 receives the entire contents of converter 157 in response to each applied clock pulse, which, as previously described, includes the three complete contents generated by A/D converter 111 at output 112. Retains a binary word at all times. 3 received in parallel by the clock separation device 163
The three words correspond to three words generated during one cycle of the regenerated color burst.

The output of converter 157 is a 24 bit word applied to the input of clock separator 163.

Separator 163 can read and write 24-bit words simultaneously. Since the separation device 163 can thus read and write simultaneously, clocking operations can be performed on its input and output sides for different non-coherent clock signals;
This provides time buffering and the ability to retime the signal. To write or store the output of converter 157, the clock signal generated by signal clock circuit 159 is applied by line 161 to the write address (WA) and write enable (WE) inputs of isolation device 163. This clock signal is in phase with the color burst of the uncompensated television signal.

The stored 24-bit word associated with each cycle of the time domain component is responsive to the x1 reference clock signal generated by reference clock generator 149 and applied by line 121 to the successive address (RA) input of separator 163. It is read out or outputted from the separation device 163.

By clocking the separator 163 with two clock signals, the phase of the separator output is realigned and synchronized with respect to the phase of the reference color subcarrier.

Converter 158 is complementary to converter 157 in that it provides a parallel-in-serial-out conversion of the digital word information received from converter 157 via clock separation device 163. Converter 158 thus converts this digital information back to a one-word serial format, however, in this embodiment, the serial word is transferred to the converter via line 121 as shown in FIG. converter 15 at a clock time determined by the X1 reference clock provided at
8 and output. These serial words are applied by line 119 to the input of D/A converter 113 and are then decoded under the control of the X3 reference clock on line 122. The D/A converter 113 reconstructs a desired analog signal synchronized with the phase of the reference subcarrier and supplies it to the output 4.

As described above, the digital compensator of the present invention serves to synchronize the incoming information signal with a reference or standard time base signal. It has been found that the time correction range is a period corresponding to a complete cycle of the time axis component in this embodiment. Specifically, for color television signals, the correction range is 3.5
The duration of one cycle of the color burst frequency corresponds to the inverse of 8 megahertz or approximately 0.28 microseconds. When the phase error of the incoming video signal exceeds this range, as is the case, for example, when reproducing a television signal from a tape recorder, the signal presented at output 114 is shifted from the phase of the color burst component to the reference color subcarrier. It is shifted so as to be synchronized with. However, the horizontal synchronization signal of the television signal is in an incorrect phase with respect to the reference horizontal synchronization signal. For some applications, such as those associated with disk storage, a correction range of one complete cycle of the color burst, i.e. 0.28 microseconds provided by this embodiment, is sufficient, and with the aid of an additional time base error compensator. Not necessary.

If a larger time base error exists, a random access memory (RAM) 164 is used as shown in FIG.
It is inserted between 8 and 8. Memory 164 corrects the time axis of the signal by an incremental amount equal to an integer multiple of the period of one cycle of the color burst. This is accomplished by writing a 24-bit word to the address in memory 164 defined by write address generator 166. memory 164
is enabled via its enabling input (WE) 2
Writing a 4-bit word, generator 166 is clocked by the x1 reference clock on line 121.

The contents of memory 164 are read according to address signals provided by read address generator 167. Generator 1
The successive address signals provided by 67 are determined by the relative times of the occurrence of the horizontal sync of the information signal and the occurrence of the reference horizontal sync. The relative times of these occurrences are determined by a counter acting as a horizontal sync comparator 168. Power'
Counter 168 begins counting in response to a reference horizontal sync and is stopped by the occurrence of a horizontal sync signal. Counter 168 counts at the frequency of the color burst. The output of counter 168 is applied to the set (S) input of successive address generator 167 and varies by setting the output successive address in accordance with the count of counter 168 following the occurrence of horizontal synchronization of the signal.

Successive 24-bit words are written to successive addresses in memory 164. The capacity of memory 164 can be adjusted as desired. At least one horizontal scan line period or about 63.
For a 5 microsecond correction, memory 164 has 256
Configured to have a capacity of 1 word. Each word represents the duration of one color burst cycle, or approximately 32 microseconds. Therefore, a capacity of 256 words provides over 63.5 microseconds of storage. The read address generator 167 is set to the write address generator 166 when the horizontal synchronization signal and the reference horizontal synchronization signal are in the same phase.
The same address signals produced by two generators are separated by a time equivalent to that required to cycle through approximately one-half of the capacity of this memory, and the occurrence of the write address precedes the occurrence of the read address. It is made to happen. For a correction capacity of one horizontal scan line period, this separation time is approximately 32 microseconds.

The above-described structure and operation of the invention applies to an apparatus for correcting information signals having recurrent time-synchronized components in the form of bursts of alternating amplitude fluctuations, such as color bursts. The present invention is also capable of compensating for time base errors in information signals having no or having a time base component in the form of other than alternating amplitude time base signals.

For example, a black-and-white television signal may be corrected in accordance with the principles of the present invention by introducing a pilot signal consisting of an artificial burst or bursts of alternating amplitude variations during the blanking period of the black-and-white television signal. Specifically, such a burst signal can be added to the back porch of each blanking interval accompanying a horizontal scan line of a black and white television signal, where the horizontal sync pulse acts as a time base component and this This inserted pilot signal is selected to have a predetermined phase relationship with respect to the time axis component.

Referring to FIG. 5, by introducing an artificial burst signal consisting of bursts of time domain information of alternating amplitude,
A modification of the apparatus of FIG. 1 for compensating black and white television signals is shown. Burst insertion is accomplished by a ringing oscillator type burst generator 171 having an input controlled by the uncorrected black and white horizontal sync provided by the sync separator 134. The output line 17 of the generator 171 is used to generate bursts of alternating amplitude time-base information to be incorporated into the black and white television signal at the summing connection 174 by means of the output line from the gate 176.
3 is provided. Connection 174 is provided by a conventional signal summing circuit. With this configuration, the black and white television signal is injected with the generated artificial burst signal one time before the incoming signal is applied to the encoded A/D converter 111. Such an arrangement is only operable if there are no color bursts in the incoming signal. For this purpose,
A connection is made between the output of burst detector 137 and gate 176 to disable the gate whenever a color burst is detected in the incoming signal.

This apparatus for use with black-and-white television signals is essentially the same as that associated with the apparatus of FIG. 1 used for color television signals, except that in the apparatus of FIG. 5 the burst signals are artificially generated and inserted. Functions in the same manner as above. Artificial burst generator 171 is designed to generate a burst signal with the same frequency and phase relationship as the color burst, thus using the standard reference color subcarrier as the reference time base signal in the black and white television circuit of FIG. Can be used. This is accomplished in accordance with the present invention by a generator 171 which receives a horizontal sync signal from a sync separator 134 and which detects the horizontal sync pulse of each black and white television scan line as it appears in the incoming television signal. Achieved by using the leading edge of the synchronization pulse to trigger a phase-controlled ringing circuit that is designed to give an oscillation frequency equal to the frequency of the standard color burst (which is nominally equal to the frequency of the reference color subcarrier) be done. The phase of the output burst signal produced by this ringing generator 171 is controlled according to the output of a ÷2 flip-flop 179, which has an input responsive to the leading edge of the horizontal sync pulse produced by the sync separator 134. Flip-flop 179 has a pair of outputs 181 and 182 and produces signals that are 180 degrees out of phase. The purpose of the ÷2 flip-flop 179 is that the phase-controlled ringing oscillator 171 generates one signal on each television scan line for artificially generated burst signals.
Color burst and NTS with 80° phase change
The phase controlled ringing oscillator 171 is driven to match the standard phase alternating signal that exists between the synchronization timing in the C standardized color television signal.

Thus, flip-flop 179 changes state in response to each horizontal sync pulse. In response to the first horizontal synchronization received from isolation device 134, output 181 switches from a low state to a high state, while output 182 simultaneously switches from a high state to a low state. The next horizontal sync pulse produces the opposite signal level condition. Phase controlled ringing oscillator 171 is designed to respond only to output states of outputs 181 and 182 that indicate a change from a low level state to a high level state.

Each artificial burst following a horizontal sync pulse outputs 173
2 microsecond pulse output generated by switched control pulse generator 136' causes gate 176 to operate by leaving it set. Also, the black and white television selector switch 183 is connected to the burst detector 13.
7 is set to provide pulses from pulse generator 136 to control recirculable storage 123 instead of 7.

[Brief explanation of the drawing]

1 is a block diagram of a digital time base compensator associated with the present invention applied to a color television signal; FIG. 2 is a detailed block diagram illustrating the configuration of a recirculating digital storage device of the compensator of FIG. 1; FIG. , 3rd A
and 3B are timing diagrams showing signal time axis compensation operation when removing time axis errors from color television signals;
4 shows in block form a circuit that enables the time base compensator of FIG. 1 to correct errors larger than one cycle of a color synchronized burst of the signal; FIG. 5 is a diagram illustrating in block form the circuitry that enables the embodiments of the time base compensators of FIGS. 1 and 4 to operate when the signal is active; FIG. In the figure, 110 is a time axis compensation device, 111 is an analog/digital converter, 113 is a digital/analog converter, 1
16 is an output processing device, 123 is a recirculating digital storage device, 126 is a switching device, 128 is an X3 reference clock source, 129 is a storage circuit, 131 is an X3 signal clock circuit,
132 is a bandpass filter, 133 is a digital/analog converter, 134 is a synchronous separator, 136 is a pulse generator,
137 is a burst detector, 139 is a random access memory, 141 is an address generator, 143 is a write clock generator, 145 is a counter, 148 is a reference signal processing device, 149 is an x1 reference clock generator, 151 is a bypass switch, 156 is a time buffer, 157 is a 1-word serial/3-word parallel converter, 158 is a 3-word parallel/1-word serial converter, 159 is an X1 signal clock, 163 is a clock separation device, and 164 is a random access memory. 'J,
166 is a write address generator, 167 is a read address generator, 168 is a counter, 171 is a burst generator, 176 is a gate, and 179 is a flip-flop.

Claims (1)

[Scope of Claims] (1) In a device for changing the time axis of a digital information signal, the information signal has a first time axis cyclic component defining the period and a frequency higher than the nominal frequency of the first time axis cyclic component. a second time axis periodic component having a nominal frequency, and having addressable storage locations for receiving and storing digital information; randomly addressable digital storage means (
164), means (164) for causing storage of successive portions of said digital information signal for respective periods in different addressed storage devices of said digital storage means (164) at times determined by a clock signal;
49, 166) and means (149, 167) for causing reproduction of the stored portion of the information signal from the storage location addressed at a time determined by the clock signal.
and at an address that is responsive to the first time base periodic component of the information signal and the time base reference signal during respective periods of the digital information signal. The time between storing each portion of said digital information signal and reproducing said portion from said address is equal to said first time axis periodic component in an integral number of cycles of said second time axis periodic component and said reference signal. (167, 16) for adjusting according to the time difference between
8) The above-mentioned device comprising: (2. The device according to claim 1, wherein said randomly addressable digital storage means (164)
has a data storage address input (WA), a data reproduction addressable (RA) and an input/output data terminal, and means (149, 166) for causing said storage to input said data storage address input in response to a clock signal. a write address generator (166) for generating a sequence of memory locations for identifying the write address signals applied to the address signal (WA); means for responsively storing the digital information signal at the input terminal in the addressed storage device and causing said reproduction;
149, 167) includes a read address generator (167) for generating a sequence of memory devices responsive to said clock signal to identify a read address signal applied to a read address input (RA); Apparatus as described above, characterized in that the digital storage means (164), in response to each applied read address signal, provides at the output data terminal a digital information signal stored in the addressed storage device. (3) The apparatus according to claim 2, wherein the read address generator (167) generates a respective read address signal at a time between occurrences of successive write address signals in response to a reference signal. The above device characterized by: (4) A device according to claim 1, wherein said storage and playback time adjustment means (167, 168) activate said read address generator (167) at the beginning of each successive period of said digital information signal. and providing a first read address signal in a sequence selected according to the time relationship between the first time axis component of the information signal and the reference signal. (5) The apparatus according to claim 4, wherein the information signal is a television signal and the first time axis component includes a periodically occurring scanning line pulse defining a period thereof, The two time axis interphase components follow each scanning line pulse (amplitude change synchronization signal), and the storage and reproduction time adjustment means (167, 168) record the time relationship between each scanning line pulse and the time axis reference signal. means (168) for comparing and providing a time-related signal in an integer number of cycles of the nominal frequency of said amplitude varying synchronization signal, said read address generator (167) responsive to said time-related signal in said integer number of cycles; The device as described above, characterized in that it provides the first read address signal in a sequence corresponding to cycles.